1bca28f8fSTomasz Figa /* 2bca28f8fSTomasz Figa * Copyright (C) 2012 Samsung Electronics. 3bca28f8fSTomasz Figa * Kyungmin Park <kyungmin.park@samsung.com> 4bca28f8fSTomasz Figa * Tomasz Figa <t.figa@samsung.com> 5bca28f8fSTomasz Figa * 6bca28f8fSTomasz Figa * This program is free software,you can redistribute it and/or modify 7bca28f8fSTomasz Figa * it under the terms of the GNU General Public License version 2 as 8bca28f8fSTomasz Figa * published by the Free Software Foundation. 9bca28f8fSTomasz Figa */ 10bca28f8fSTomasz Figa 11bca28f8fSTomasz Figa #include <linux/kernel.h> 12bca28f8fSTomasz Figa #include <linux/io.h> 13bca28f8fSTomasz Figa #include <linux/init.h> 14bca28f8fSTomasz Figa #include <linux/of.h> 15bca28f8fSTomasz Figa #include <linux/of_address.h> 16bca28f8fSTomasz Figa 172b9d9c32STomasz Figa #include <asm/cacheflush.h> 182b9d9c32STomasz Figa #include <asm/cputype.h> 19bca28f8fSTomasz Figa #include <asm/firmware.h> 205445b640STomasz Figa #include <asm/hardware/cache-l2x0.h> 212b9d9c32STomasz Figa #include <asm/suspend.h> 22bca28f8fSTomasz Figa 23bca28f8fSTomasz Figa #include <mach/map.h> 24bca28f8fSTomasz Figa 25b3205deaSSachin Kamat #include "common.h" 26bca28f8fSTomasz Figa #include "smc.h" 27bca28f8fSTomasz Figa 282b9d9c32STomasz Figa #define EXYNOS_SLEEP_MAGIC 0x00000bad 29a135e201SBartlomiej Zolnierkiewicz #define EXYNOS_AFTR_MAGIC 0xfcba0d10 302b9d9c32STomasz Figa #define EXYNOS_BOOT_ADDR 0x8 312b9d9c32STomasz Figa #define EXYNOS_BOOT_FLAG 0xc 322b9d9c32STomasz Figa 33a135e201SBartlomiej Zolnierkiewicz static void exynos_save_cp15(void) 34a135e201SBartlomiej Zolnierkiewicz { 35a135e201SBartlomiej Zolnierkiewicz /* Save Power control and Diagnostic registers */ 36a135e201SBartlomiej Zolnierkiewicz asm ("mrc p15, 0, %0, c15, c0, 0\n" 37a135e201SBartlomiej Zolnierkiewicz "mrc p15, 0, %1, c15, c0, 1\n" 38a135e201SBartlomiej Zolnierkiewicz : "=r" (cp15_save_power), "=r" (cp15_save_diag) 39a135e201SBartlomiej Zolnierkiewicz : : "cc"); 40a135e201SBartlomiej Zolnierkiewicz } 41a135e201SBartlomiej Zolnierkiewicz 420b7778a8SBartlomiej Zolnierkiewicz static int exynos_do_idle(unsigned long mode) 43bca28f8fSTomasz Figa { 440b7778a8SBartlomiej Zolnierkiewicz switch (mode) { 450b7778a8SBartlomiej Zolnierkiewicz case FW_DO_IDLE_AFTR: 46a135e201SBartlomiej Zolnierkiewicz if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 47a135e201SBartlomiej Zolnierkiewicz exynos_save_cp15(); 48a135e201SBartlomiej Zolnierkiewicz __raw_writel(virt_to_phys(exynos_cpu_resume_ns), 49a135e201SBartlomiej Zolnierkiewicz sysram_ns_base_addr + 0x24); 50a135e201SBartlomiej Zolnierkiewicz __raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20); 5189366409SBartlomiej Zolnierkiewicz if (soc_is_exynos3250()) { 5289366409SBartlomiej Zolnierkiewicz exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE, 5389366409SBartlomiej Zolnierkiewicz SMC_POWERSTATE_IDLE, 0); 5489366409SBartlomiej Zolnierkiewicz exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER, 5589366409SBartlomiej Zolnierkiewicz SMC_POWERSTATE_IDLE, 0); 5689366409SBartlomiej Zolnierkiewicz } else 570b7778a8SBartlomiej Zolnierkiewicz exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0); 580b7778a8SBartlomiej Zolnierkiewicz break; 590b7778a8SBartlomiej Zolnierkiewicz case FW_DO_IDLE_SLEEP: 60bca28f8fSTomasz Figa exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); 610b7778a8SBartlomiej Zolnierkiewicz } 62bca28f8fSTomasz Figa return 0; 63bca28f8fSTomasz Figa } 64bca28f8fSTomasz Figa 65bca28f8fSTomasz Figa static int exynos_cpu_boot(int cpu) 66bca28f8fSTomasz Figa { 67989ff3fdSKyungmin Park /* 686457158aSChanwoo Choi * Exynos3250 doesn't need to send smc command for secondary CPU boot 696457158aSChanwoo Choi * because Exynos3250 removes WFE in secure mode. 706457158aSChanwoo Choi */ 716457158aSChanwoo Choi if (soc_is_exynos3250()) 726457158aSChanwoo Choi return 0; 736457158aSChanwoo Choi 746457158aSChanwoo Choi /* 75989ff3fdSKyungmin Park * The second parameter of SMC_CMD_CPU1BOOT command means CPU id. 76989ff3fdSKyungmin Park * But, Exynos4212 has only one secondary CPU so second parameter 77989ff3fdSKyungmin Park * isn't used for informing secure firmware about CPU id. 78989ff3fdSKyungmin Park */ 79989ff3fdSKyungmin Park if (soc_is_exynos4212()) 80989ff3fdSKyungmin Park cpu = 0; 81989ff3fdSKyungmin Park 82bca28f8fSTomasz Figa exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); 83bca28f8fSTomasz Figa return 0; 84bca28f8fSTomasz Figa } 85bca28f8fSTomasz Figa 86bca28f8fSTomasz Figa static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) 87bca28f8fSTomasz Figa { 88b3205deaSSachin Kamat void __iomem *boot_reg; 89b3205deaSSachin Kamat 90b3205deaSSachin Kamat if (!sysram_ns_base_addr) 91b3205deaSSachin Kamat return -ENODEV; 92b3205deaSSachin Kamat 93fe388facSOlof Johansson boot_reg = sysram_ns_base_addr + 0x1c; 94989ff3fdSKyungmin Park 9535e75645SSachin Kamat /* 9635e75645SSachin Kamat * Almost all Exynos-series of SoCs that run in secure mode don't need 9735e75645SSachin Kamat * additional offset for every CPU, with Exynos4412 being the only 9835e75645SSachin Kamat * exception. 9935e75645SSachin Kamat */ 10035e75645SSachin Kamat if (soc_is_exynos4412()) 101989ff3fdSKyungmin Park boot_reg += 4 * cpu; 102bca28f8fSTomasz Figa 103bca28f8fSTomasz Figa __raw_writel(boot_addr, boot_reg); 104bca28f8fSTomasz Figa return 0; 105bca28f8fSTomasz Figa } 106bca28f8fSTomasz Figa 1071225ad72SBartlomiej Zolnierkiewicz static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr) 1081225ad72SBartlomiej Zolnierkiewicz { 1091225ad72SBartlomiej Zolnierkiewicz void __iomem *boot_reg; 1101225ad72SBartlomiej Zolnierkiewicz 1111225ad72SBartlomiej Zolnierkiewicz if (!sysram_ns_base_addr) 1121225ad72SBartlomiej Zolnierkiewicz return -ENODEV; 1131225ad72SBartlomiej Zolnierkiewicz 1141225ad72SBartlomiej Zolnierkiewicz boot_reg = sysram_ns_base_addr + 0x1c; 1151225ad72SBartlomiej Zolnierkiewicz 1161225ad72SBartlomiej Zolnierkiewicz if (soc_is_exynos4412()) 1171225ad72SBartlomiej Zolnierkiewicz boot_reg += 4 * cpu; 1181225ad72SBartlomiej Zolnierkiewicz 1191225ad72SBartlomiej Zolnierkiewicz *boot_addr = __raw_readl(boot_reg); 1201225ad72SBartlomiej Zolnierkiewicz return 0; 1211225ad72SBartlomiej Zolnierkiewicz } 1221225ad72SBartlomiej Zolnierkiewicz 1232b9d9c32STomasz Figa static int exynos_cpu_suspend(unsigned long arg) 1242b9d9c32STomasz Figa { 1252b9d9c32STomasz Figa flush_cache_all(); 1262b9d9c32STomasz Figa outer_flush_all(); 1272b9d9c32STomasz Figa 1282b9d9c32STomasz Figa exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); 1292b9d9c32STomasz Figa 1302b9d9c32STomasz Figa pr_info("Failed to suspend the system\n"); 1312b9d9c32STomasz Figa writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); 1322b9d9c32STomasz Figa return 1; 1332b9d9c32STomasz Figa } 1342b9d9c32STomasz Figa 1352b9d9c32STomasz Figa static int exynos_suspend(void) 1362b9d9c32STomasz Figa { 137a135e201SBartlomiej Zolnierkiewicz if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 138a135e201SBartlomiej Zolnierkiewicz exynos_save_cp15(); 1392b9d9c32STomasz Figa 1402b9d9c32STomasz Figa writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); 1412b9d9c32STomasz Figa writel(virt_to_phys(exynos_cpu_resume_ns), 1422b9d9c32STomasz Figa sysram_ns_base_addr + EXYNOS_BOOT_ADDR); 1432b9d9c32STomasz Figa 1442b9d9c32STomasz Figa return cpu_suspend(0, exynos_cpu_suspend); 1452b9d9c32STomasz Figa } 1462b9d9c32STomasz Figa 1472b9d9c32STomasz Figa static int exynos_resume(void) 1482b9d9c32STomasz Figa { 1492b9d9c32STomasz Figa writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); 1502b9d9c32STomasz Figa 1512b9d9c32STomasz Figa return 0; 1522b9d9c32STomasz Figa } 1532b9d9c32STomasz Figa 154bca28f8fSTomasz Figa static const struct firmware_ops exynos_firmware_ops = { 15503c1b760SArnd Bergmann .do_idle = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_do_idle : NULL, 156bca28f8fSTomasz Figa .set_cpu_boot_addr = exynos_set_cpu_boot_addr, 1571225ad72SBartlomiej Zolnierkiewicz .get_cpu_boot_addr = exynos_get_cpu_boot_addr, 158bca28f8fSTomasz Figa .cpu_boot = exynos_cpu_boot, 15903c1b760SArnd Bergmann .suspend = IS_ENABLED(CONFIG_PM_SLEEP) ? exynos_suspend : NULL, 16003c1b760SArnd Bergmann .resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL, 161bca28f8fSTomasz Figa }; 162bca28f8fSTomasz Figa 1635445b640STomasz Figa static void exynos_l2_write_sec(unsigned long val, unsigned reg) 1645445b640STomasz Figa { 1655445b640STomasz Figa static int l2cache_enabled; 1665445b640STomasz Figa 1675445b640STomasz Figa switch (reg) { 1685445b640STomasz Figa case L2X0_CTRL: 1695445b640STomasz Figa if (val & L2X0_CTRL_EN) { 1705445b640STomasz Figa /* 1715445b640STomasz Figa * Before the cache can be enabled, due to firmware 1725445b640STomasz Figa * design, SMC_CMD_L2X0INVALL must be called. 1735445b640STomasz Figa */ 1745445b640STomasz Figa if (!l2cache_enabled) { 1755445b640STomasz Figa exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); 1765445b640STomasz Figa l2cache_enabled = 1; 1775445b640STomasz Figa } 1785445b640STomasz Figa } else { 1795445b640STomasz Figa l2cache_enabled = 0; 1805445b640STomasz Figa } 1815445b640STomasz Figa exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0); 1825445b640STomasz Figa break; 1835445b640STomasz Figa 1845445b640STomasz Figa case L2X0_DEBUG_CTRL: 1855445b640STomasz Figa exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0); 1865445b640STomasz Figa break; 1875445b640STomasz Figa 1885445b640STomasz Figa default: 1895445b640STomasz Figa WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg); 1905445b640STomasz Figa } 1915445b640STomasz Figa } 1925445b640STomasz Figa 1935445b640STomasz Figa static void exynos_l2_configure(const struct l2x0_regs *regs) 1945445b640STomasz Figa { 1955445b640STomasz Figa exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency, 1965445b640STomasz Figa regs->prefetch_ctrl); 1975445b640STomasz Figa exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0); 1985445b640STomasz Figa } 1995445b640STomasz Figa 200bca28f8fSTomasz Figa void __init exynos_firmware_init(void) 201bca28f8fSTomasz Figa { 202bca28f8fSTomasz Figa struct device_node *nd; 203bca28f8fSTomasz Figa const __be32 *addr; 204bca28f8fSTomasz Figa 205bca28f8fSTomasz Figa nd = of_find_compatible_node(NULL, NULL, 206bca28f8fSTomasz Figa "samsung,secure-firmware"); 207bca28f8fSTomasz Figa if (!nd) 208bca28f8fSTomasz Figa return; 209bca28f8fSTomasz Figa 210bca28f8fSTomasz Figa addr = of_get_address(nd, 0, NULL, NULL); 211bca28f8fSTomasz Figa if (!addr) { 212bca28f8fSTomasz Figa pr_err("%s: No address specified.\n", __func__); 213bca28f8fSTomasz Figa return; 214bca28f8fSTomasz Figa } 215bca28f8fSTomasz Figa 216bca28f8fSTomasz Figa pr_info("Running under secure firmware.\n"); 217bca28f8fSTomasz Figa 218bca28f8fSTomasz Figa register_firmware_ops(&exynos_firmware_ops); 2195445b640STomasz Figa 2205445b640STomasz Figa /* 2215445b640STomasz Figa * Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310), 2225445b640STomasz Figa * running under secure firmware, require certain registers of L2 2235445b640STomasz Figa * cache controller to be written in secure mode. Here .write_sec 2245445b640STomasz Figa * callback is provided to perform necessary SMC calls. 2255445b640STomasz Figa */ 2265445b640STomasz Figa if (IS_ENABLED(CONFIG_CACHE_L2X0) && 2275445b640STomasz Figa read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { 2285445b640STomasz Figa outer_cache.write_sec = exynos_l2_write_sec; 2295445b640STomasz Figa outer_cache.configure = exynos_l2_configure; 2305445b640STomasz Figa } 231bca28f8fSTomasz Figa } 232dc1b9448SBartlomiej Zolnierkiewicz 233dc1b9448SBartlomiej Zolnierkiewicz #define REG_CPU_STATE_ADDR (sysram_ns_base_addr + 0x28) 234dc1b9448SBartlomiej Zolnierkiewicz #define BOOT_MODE_MASK 0x1f 235dc1b9448SBartlomiej Zolnierkiewicz 236dc1b9448SBartlomiej Zolnierkiewicz void exynos_set_boot_flag(unsigned int cpu, unsigned int mode) 237dc1b9448SBartlomiej Zolnierkiewicz { 238dc1b9448SBartlomiej Zolnierkiewicz unsigned int tmp; 239dc1b9448SBartlomiej Zolnierkiewicz 240dc1b9448SBartlomiej Zolnierkiewicz tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4); 241dc1b9448SBartlomiej Zolnierkiewicz 242dc1b9448SBartlomiej Zolnierkiewicz if (mode & BOOT_MODE_MASK) 243dc1b9448SBartlomiej Zolnierkiewicz tmp &= ~BOOT_MODE_MASK; 244dc1b9448SBartlomiej Zolnierkiewicz 245dc1b9448SBartlomiej Zolnierkiewicz tmp |= mode; 246dc1b9448SBartlomiej Zolnierkiewicz __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4); 247dc1b9448SBartlomiej Zolnierkiewicz } 248dc1b9448SBartlomiej Zolnierkiewicz 249dc1b9448SBartlomiej Zolnierkiewicz void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode) 250dc1b9448SBartlomiej Zolnierkiewicz { 251dc1b9448SBartlomiej Zolnierkiewicz unsigned int tmp; 252dc1b9448SBartlomiej Zolnierkiewicz 253dc1b9448SBartlomiej Zolnierkiewicz tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4); 254dc1b9448SBartlomiej Zolnierkiewicz tmp &= ~mode; 255dc1b9448SBartlomiej Zolnierkiewicz __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4); 256dc1b9448SBartlomiej Zolnierkiewicz } 257