1347863d4SKrzysztof Kozlowski // SPDX-License-Identifier: GPL-2.0
2347863d4SKrzysztof Kozlowski //
3347863d4SKrzysztof Kozlowski // Copyright (C) 2012 Samsung Electronics.
4347863d4SKrzysztof Kozlowski // Kyungmin Park <kyungmin.park@samsung.com>
5347863d4SKrzysztof Kozlowski // Tomasz Figa <t.figa@samsung.com>
6bca28f8fSTomasz Figa
7bca28f8fSTomasz Figa #include <linux/kernel.h>
8bca28f8fSTomasz Figa #include <linux/io.h>
9bca28f8fSTomasz Figa #include <linux/init.h>
10bca28f8fSTomasz Figa #include <linux/of.h>
11bca28f8fSTomasz Figa #include <linux/of_address.h>
12bca28f8fSTomasz Figa
132b9d9c32STomasz Figa #include <asm/cacheflush.h>
142b9d9c32STomasz Figa #include <asm/cputype.h>
15bca28f8fSTomasz Figa #include <asm/firmware.h>
165445b640STomasz Figa #include <asm/hardware/cache-l2x0.h>
172b9d9c32STomasz Figa #include <asm/suspend.h>
18bca28f8fSTomasz Figa
19b3205deaSSachin Kamat #include "common.h"
20bca28f8fSTomasz Figa #include "smc.h"
21bca28f8fSTomasz Figa
222b9d9c32STomasz Figa #define EXYNOS_BOOT_ADDR 0x8
232b9d9c32STomasz Figa #define EXYNOS_BOOT_FLAG 0xc
242b9d9c32STomasz Figa
exynos_save_cp15(void)25a135e201SBartlomiej Zolnierkiewicz static void exynos_save_cp15(void)
26a135e201SBartlomiej Zolnierkiewicz {
27a135e201SBartlomiej Zolnierkiewicz /* Save Power control and Diagnostic registers */
28a135e201SBartlomiej Zolnierkiewicz asm ("mrc p15, 0, %0, c15, c0, 0\n"
29a135e201SBartlomiej Zolnierkiewicz "mrc p15, 0, %1, c15, c0, 1\n"
30a135e201SBartlomiej Zolnierkiewicz : "=r" (cp15_save_power), "=r" (cp15_save_diag)
31a135e201SBartlomiej Zolnierkiewicz : : "cc");
32a135e201SBartlomiej Zolnierkiewicz }
33a135e201SBartlomiej Zolnierkiewicz
exynos_do_idle(unsigned long mode)340b7778a8SBartlomiej Zolnierkiewicz static int exynos_do_idle(unsigned long mode)
35bca28f8fSTomasz Figa {
360b7778a8SBartlomiej Zolnierkiewicz switch (mode) {
370b7778a8SBartlomiej Zolnierkiewicz case FW_DO_IDLE_AFTR:
38a135e201SBartlomiej Zolnierkiewicz if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
39a135e201SBartlomiej Zolnierkiewicz exynos_save_cp15();
4064fc2a94SFlorian Fainelli writel_relaxed(__pa_symbol(exynos_cpu_resume_ns),
41a135e201SBartlomiej Zolnierkiewicz sysram_ns_base_addr + 0x24);
42458ad21dSBen Dooks writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
4389366409SBartlomiej Zolnierkiewicz if (soc_is_exynos3250()) {
44af997114SBartlomiej Zolnierkiewicz flush_cache_all();
4589366409SBartlomiej Zolnierkiewicz exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
4689366409SBartlomiej Zolnierkiewicz SMC_POWERSTATE_IDLE, 0);
4789366409SBartlomiej Zolnierkiewicz exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,
4889366409SBartlomiej Zolnierkiewicz SMC_POWERSTATE_IDLE, 0);
4989366409SBartlomiej Zolnierkiewicz } else
500b7778a8SBartlomiej Zolnierkiewicz exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
510b7778a8SBartlomiej Zolnierkiewicz break;
520b7778a8SBartlomiej Zolnierkiewicz case FW_DO_IDLE_SLEEP:
53bca28f8fSTomasz Figa exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
540b7778a8SBartlomiej Zolnierkiewicz }
55bca28f8fSTomasz Figa return 0;
56bca28f8fSTomasz Figa }
57bca28f8fSTomasz Figa
exynos_cpu_boot(int cpu)58bca28f8fSTomasz Figa static int exynos_cpu_boot(int cpu)
59bca28f8fSTomasz Figa {
60989ff3fdSKyungmin Park /*
616457158aSChanwoo Choi * Exynos3250 doesn't need to send smc command for secondary CPU boot
626457158aSChanwoo Choi * because Exynos3250 removes WFE in secure mode.
63534aaa18SHenrik Grimler *
64534aaa18SHenrik Grimler * On Exynos5 devices the call is ignored by trustzone firmware.
656457158aSChanwoo Choi */
66*4e486a65SArtur Weber if (!soc_is_exynos4210() && !soc_is_exynos4212() &&
67*4e486a65SArtur Weber !soc_is_exynos4412())
686457158aSChanwoo Choi return 0;
696457158aSChanwoo Choi
706457158aSChanwoo Choi /*
71989ff3fdSKyungmin Park * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
72*4e486a65SArtur Weber * But, Exynos4212 has only one secondary CPU so second parameter
73*4e486a65SArtur Weber * isn't used for informing secure firmware about CPU id.
74989ff3fdSKyungmin Park */
75*4e486a65SArtur Weber if (soc_is_exynos4212())
76*4e486a65SArtur Weber cpu = 0;
77*4e486a65SArtur Weber
78bca28f8fSTomasz Figa exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
79bca28f8fSTomasz Figa return 0;
80bca28f8fSTomasz Figa }
81bca28f8fSTomasz Figa
exynos_set_cpu_boot_addr(int cpu,unsigned long boot_addr)82bca28f8fSTomasz Figa static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
83bca28f8fSTomasz Figa {
84b3205deaSSachin Kamat void __iomem *boot_reg;
85b3205deaSSachin Kamat
86b3205deaSSachin Kamat if (!sysram_ns_base_addr)
87b3205deaSSachin Kamat return -ENODEV;
88b3205deaSSachin Kamat
89fe388facSOlof Johansson boot_reg = sysram_ns_base_addr + 0x1c;
90989ff3fdSKyungmin Park
9135e75645SSachin Kamat /*
9235e75645SSachin Kamat * Almost all Exynos-series of SoCs that run in secure mode don't need
9335e75645SSachin Kamat * additional offset for every CPU, with Exynos4412 being the only
9435e75645SSachin Kamat * exception.
9535e75645SSachin Kamat */
9635e75645SSachin Kamat if (soc_is_exynos4412())
97989ff3fdSKyungmin Park boot_reg += 4 * cpu;
98bca28f8fSTomasz Figa
99458ad21dSBen Dooks writel_relaxed(boot_addr, boot_reg);
100bca28f8fSTomasz Figa return 0;
101bca28f8fSTomasz Figa }
102bca28f8fSTomasz Figa
exynos_get_cpu_boot_addr(int cpu,unsigned long * boot_addr)1031225ad72SBartlomiej Zolnierkiewicz static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr)
1041225ad72SBartlomiej Zolnierkiewicz {
1051225ad72SBartlomiej Zolnierkiewicz void __iomem *boot_reg;
1061225ad72SBartlomiej Zolnierkiewicz
1071225ad72SBartlomiej Zolnierkiewicz if (!sysram_ns_base_addr)
1081225ad72SBartlomiej Zolnierkiewicz return -ENODEV;
1091225ad72SBartlomiej Zolnierkiewicz
1101225ad72SBartlomiej Zolnierkiewicz boot_reg = sysram_ns_base_addr + 0x1c;
1111225ad72SBartlomiej Zolnierkiewicz
1121225ad72SBartlomiej Zolnierkiewicz if (soc_is_exynos4412())
1131225ad72SBartlomiej Zolnierkiewicz boot_reg += 4 * cpu;
1141225ad72SBartlomiej Zolnierkiewicz
115458ad21dSBen Dooks *boot_addr = readl_relaxed(boot_reg);
1161225ad72SBartlomiej Zolnierkiewicz return 0;
1171225ad72SBartlomiej Zolnierkiewicz }
1181225ad72SBartlomiej Zolnierkiewicz
exynos_cpu_suspend(unsigned long arg)1192b9d9c32STomasz Figa static int exynos_cpu_suspend(unsigned long arg)
1202b9d9c32STomasz Figa {
1212b9d9c32STomasz Figa flush_cache_all();
1222b9d9c32STomasz Figa outer_flush_all();
1232b9d9c32STomasz Figa
1242b9d9c32STomasz Figa exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
1252b9d9c32STomasz Figa
1262b9d9c32STomasz Figa pr_info("Failed to suspend the system\n");
1272b9d9c32STomasz Figa writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
1282b9d9c32STomasz Figa return 1;
1292b9d9c32STomasz Figa }
1302b9d9c32STomasz Figa
exynos_suspend(void)1312b9d9c32STomasz Figa static int exynos_suspend(void)
1322b9d9c32STomasz Figa {
133a135e201SBartlomiej Zolnierkiewicz if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
134a135e201SBartlomiej Zolnierkiewicz exynos_save_cp15();
1352b9d9c32STomasz Figa
1362b9d9c32STomasz Figa writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
13764fc2a94SFlorian Fainelli writel(__pa_symbol(exynos_cpu_resume_ns),
1382b9d9c32STomasz Figa sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
1392b9d9c32STomasz Figa
1402b9d9c32STomasz Figa return cpu_suspend(0, exynos_cpu_suspend);
1412b9d9c32STomasz Figa }
1422b9d9c32STomasz Figa
exynos_resume(void)1432b9d9c32STomasz Figa static int exynos_resume(void)
1442b9d9c32STomasz Figa {
1452b9d9c32STomasz Figa writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
1462b9d9c32STomasz Figa
1472b9d9c32STomasz Figa return 0;
1482b9d9c32STomasz Figa }
1492b9d9c32STomasz Figa
150bca28f8fSTomasz Figa static const struct firmware_ops exynos_firmware_ops = {
15103c1b760SArnd Bergmann .do_idle = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_do_idle : NULL,
152bca28f8fSTomasz Figa .set_cpu_boot_addr = exynos_set_cpu_boot_addr,
1531225ad72SBartlomiej Zolnierkiewicz .get_cpu_boot_addr = exynos_get_cpu_boot_addr,
154bca28f8fSTomasz Figa .cpu_boot = exynos_cpu_boot,
15503c1b760SArnd Bergmann .suspend = IS_ENABLED(CONFIG_PM_SLEEP) ? exynos_suspend : NULL,
15603c1b760SArnd Bergmann .resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL,
157bca28f8fSTomasz Figa };
158bca28f8fSTomasz Figa
exynos_l2_write_sec(unsigned long val,unsigned reg)1595445b640STomasz Figa static void exynos_l2_write_sec(unsigned long val, unsigned reg)
1605445b640STomasz Figa {
1615445b640STomasz Figa static int l2cache_enabled;
1625445b640STomasz Figa
1635445b640STomasz Figa switch (reg) {
1645445b640STomasz Figa case L2X0_CTRL:
1655445b640STomasz Figa if (val & L2X0_CTRL_EN) {
1665445b640STomasz Figa /*
1675445b640STomasz Figa * Before the cache can be enabled, due to firmware
1685445b640STomasz Figa * design, SMC_CMD_L2X0INVALL must be called.
1695445b640STomasz Figa */
1705445b640STomasz Figa if (!l2cache_enabled) {
1715445b640STomasz Figa exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
1725445b640STomasz Figa l2cache_enabled = 1;
1735445b640STomasz Figa }
1745445b640STomasz Figa } else {
1755445b640STomasz Figa l2cache_enabled = 0;
1765445b640STomasz Figa }
1775445b640STomasz Figa exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
1785445b640STomasz Figa break;
1795445b640STomasz Figa
1805445b640STomasz Figa case L2X0_DEBUG_CTRL:
1815445b640STomasz Figa exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
1825445b640STomasz Figa break;
1835445b640STomasz Figa
1845445b640STomasz Figa default:
1855445b640STomasz Figa WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg);
1865445b640STomasz Figa }
1875445b640STomasz Figa }
1885445b640STomasz Figa
exynos_l2_configure(const struct l2x0_regs * regs)1895445b640STomasz Figa static void exynos_l2_configure(const struct l2x0_regs *regs)
1905445b640STomasz Figa {
1915445b640STomasz Figa exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency,
1925445b640STomasz Figa regs->prefetch_ctrl);
1935445b640STomasz Figa exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
1945445b640STomasz Figa }
1955445b640STomasz Figa
exynos_secure_firmware_available(void)196e0b35c1aSKrzysztof Kozlowski bool __init exynos_secure_firmware_available(void)
197bca28f8fSTomasz Figa {
198bca28f8fSTomasz Figa struct device_node *nd;
199bca28f8fSTomasz Figa const __be32 *addr;
200bca28f8fSTomasz Figa
201bca28f8fSTomasz Figa nd = of_find_compatible_node(NULL, NULL,
202bca28f8fSTomasz Figa "samsung,secure-firmware");
203bca28f8fSTomasz Figa if (!nd)
204e0b35c1aSKrzysztof Kozlowski return false;
205bca28f8fSTomasz Figa
206bca28f8fSTomasz Figa addr = of_get_address(nd, 0, NULL, NULL);
207629266bfSWen Yang of_node_put(nd);
208bca28f8fSTomasz Figa if (!addr) {
209bca28f8fSTomasz Figa pr_err("%s: No address specified.\n", __func__);
210e0b35c1aSKrzysztof Kozlowski return false;
211bca28f8fSTomasz Figa }
212bca28f8fSTomasz Figa
213e0b35c1aSKrzysztof Kozlowski return true;
214e0b35c1aSKrzysztof Kozlowski }
215e0b35c1aSKrzysztof Kozlowski
exynos_firmware_init(void)216e0b35c1aSKrzysztof Kozlowski void __init exynos_firmware_init(void)
217e0b35c1aSKrzysztof Kozlowski {
218e0b35c1aSKrzysztof Kozlowski if (!exynos_secure_firmware_available())
219e0b35c1aSKrzysztof Kozlowski return;
220e0b35c1aSKrzysztof Kozlowski
221bca28f8fSTomasz Figa pr_info("Running under secure firmware.\n");
222bca28f8fSTomasz Figa
223bca28f8fSTomasz Figa register_firmware_ops(&exynos_firmware_ops);
2245445b640STomasz Figa
2255445b640STomasz Figa /*
2265445b640STomasz Figa * Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310),
2275445b640STomasz Figa * running under secure firmware, require certain registers of L2
2285445b640STomasz Figa * cache controller to be written in secure mode. Here .write_sec
2295445b640STomasz Figa * callback is provided to perform necessary SMC calls.
2305445b640STomasz Figa */
2315445b640STomasz Figa if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
2325445b640STomasz Figa read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
2335445b640STomasz Figa outer_cache.write_sec = exynos_l2_write_sec;
2345445b640STomasz Figa outer_cache.configure = exynos_l2_configure;
2355445b640STomasz Figa }
236bca28f8fSTomasz Figa }
237dc1b9448SBartlomiej Zolnierkiewicz
238dc1b9448SBartlomiej Zolnierkiewicz #define REG_CPU_STATE_ADDR (sysram_ns_base_addr + 0x28)
239dc1b9448SBartlomiej Zolnierkiewicz #define BOOT_MODE_MASK 0x1f
240dc1b9448SBartlomiej Zolnierkiewicz
exynos_set_boot_flag(unsigned int cpu,unsigned int mode)241dc1b9448SBartlomiej Zolnierkiewicz void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
242dc1b9448SBartlomiej Zolnierkiewicz {
243dc1b9448SBartlomiej Zolnierkiewicz unsigned int tmp;
244dc1b9448SBartlomiej Zolnierkiewicz
245458ad21dSBen Dooks tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
246dc1b9448SBartlomiej Zolnierkiewicz
247dc1b9448SBartlomiej Zolnierkiewicz if (mode & BOOT_MODE_MASK)
248dc1b9448SBartlomiej Zolnierkiewicz tmp &= ~BOOT_MODE_MASK;
249dc1b9448SBartlomiej Zolnierkiewicz
250dc1b9448SBartlomiej Zolnierkiewicz tmp |= mode;
251458ad21dSBen Dooks writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
252dc1b9448SBartlomiej Zolnierkiewicz }
253dc1b9448SBartlomiej Zolnierkiewicz
exynos_clear_boot_flag(unsigned int cpu,unsigned int mode)254dc1b9448SBartlomiej Zolnierkiewicz void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
255dc1b9448SBartlomiej Zolnierkiewicz {
256dc1b9448SBartlomiej Zolnierkiewicz unsigned int tmp;
257dc1b9448SBartlomiej Zolnierkiewicz
258458ad21dSBen Dooks tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
259dc1b9448SBartlomiej Zolnierkiewicz tmp &= ~mode;
260458ad21dSBen Dooks writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
261dc1b9448SBartlomiej Zolnierkiewicz }
262