1 /* 2 * SAMSUNG EXYNOS Flattened Device Tree enabled machine 3 * 4 * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/init.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/serial_s3c.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_fdt.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_domain.h> 22 23 #include <asm/cacheflush.h> 24 #include <asm/hardware/cache-l2x0.h> 25 #include <asm/mach/arch.h> 26 #include <asm/mach/map.h> 27 #include <asm/memory.h> 28 29 #include "common.h" 30 #include "mfc.h" 31 #include "regs-pmu.h" 32 33 static struct map_desc exynos4_iodesc[] __initdata = { 34 { 35 .virtual = (unsigned long)S3C_VA_SYS, 36 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON), 37 .length = SZ_64K, 38 .type = MT_DEVICE, 39 }, { 40 .virtual = (unsigned long)S3C_VA_TIMER, 41 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER), 42 .length = SZ_16K, 43 .type = MT_DEVICE, 44 }, { 45 .virtual = (unsigned long)S3C_VA_WATCHDOG, 46 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG), 47 .length = SZ_4K, 48 .type = MT_DEVICE, 49 }, { 50 .virtual = (unsigned long)S5P_VA_SROMC, 51 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC), 52 .length = SZ_4K, 53 .type = MT_DEVICE, 54 }, { 55 .virtual = (unsigned long)S5P_VA_SYSTIMER, 56 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER), 57 .length = SZ_4K, 58 .type = MT_DEVICE, 59 }, { 60 .virtual = (unsigned long)S5P_VA_PMU, 61 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU), 62 .length = SZ_64K, 63 .type = MT_DEVICE, 64 }, { 65 .virtual = (unsigned long)S5P_VA_COMBINER_BASE, 66 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER), 67 .length = SZ_4K, 68 .type = MT_DEVICE, 69 }, { 70 .virtual = (unsigned long)S5P_VA_GIC_CPU, 71 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU), 72 .length = SZ_64K, 73 .type = MT_DEVICE, 74 }, { 75 .virtual = (unsigned long)S5P_VA_GIC_DIST, 76 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST), 77 .length = SZ_64K, 78 .type = MT_DEVICE, 79 }, { 80 .virtual = (unsigned long)S5P_VA_CMU, 81 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), 82 .length = SZ_128K, 83 .type = MT_DEVICE, 84 }, { 85 .virtual = (unsigned long)S5P_VA_COREPERI_BASE, 86 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI), 87 .length = SZ_8K, 88 .type = MT_DEVICE, 89 }, { 90 .virtual = (unsigned long)S5P_VA_L2CC, 91 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC), 92 .length = SZ_4K, 93 .type = MT_DEVICE, 94 }, { 95 .virtual = (unsigned long)S5P_VA_DMC0, 96 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), 97 .length = SZ_64K, 98 .type = MT_DEVICE, 99 }, { 100 .virtual = (unsigned long)S5P_VA_DMC1, 101 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1), 102 .length = SZ_64K, 103 .type = MT_DEVICE, 104 }, { 105 .virtual = (unsigned long)S3C_VA_USB_HSPHY, 106 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), 107 .length = SZ_4K, 108 .type = MT_DEVICE, 109 }, 110 }; 111 112 static struct map_desc exynos5_iodesc[] __initdata = { 113 { 114 .virtual = (unsigned long)S3C_VA_SYS, 115 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON), 116 .length = SZ_64K, 117 .type = MT_DEVICE, 118 }, { 119 .virtual = (unsigned long)S3C_VA_TIMER, 120 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER), 121 .length = SZ_16K, 122 .type = MT_DEVICE, 123 }, { 124 .virtual = (unsigned long)S3C_VA_WATCHDOG, 125 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG), 126 .length = SZ_4K, 127 .type = MT_DEVICE, 128 }, { 129 .virtual = (unsigned long)S5P_VA_SROMC, 130 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC), 131 .length = SZ_4K, 132 .type = MT_DEVICE, 133 }, { 134 .virtual = (unsigned long)S5P_VA_CMU, 135 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU), 136 .length = 144 * SZ_1K, 137 .type = MT_DEVICE, 138 }, { 139 .virtual = (unsigned long)S5P_VA_PMU, 140 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU), 141 .length = SZ_64K, 142 .type = MT_DEVICE, 143 }, 144 }; 145 146 void exynos_restart(enum reboot_mode mode, const char *cmd) 147 { 148 struct device_node *np; 149 u32 val = 0x1; 150 void __iomem *addr = EXYNOS_SWRESET; 151 152 if (of_machine_is_compatible("samsung,exynos5440")) { 153 u32 status; 154 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock"); 155 156 addr = of_iomap(np, 0) + 0xbc; 157 status = __raw_readl(addr); 158 159 addr = of_iomap(np, 0) + 0xcc; 160 val = __raw_readl(addr); 161 162 val = (val & 0xffff0000) | (status & 0xffff); 163 } 164 165 __raw_writel(val, addr); 166 } 167 168 static struct platform_device exynos_cpuidle = { 169 .name = "exynos_cpuidle", 170 .dev.platform_data = exynos_enter_aftr, 171 .id = -1, 172 }; 173 174 void __init exynos_cpuidle_init(void) 175 { 176 if (soc_is_exynos5440()) 177 return; 178 179 platform_device_register(&exynos_cpuidle); 180 } 181 182 void __init exynos_cpufreq_init(void) 183 { 184 platform_device_register_simple("exynos-cpufreq", -1, NULL, 0); 185 } 186 187 void __iomem *sysram_base_addr; 188 void __iomem *sysram_ns_base_addr; 189 190 void __init exynos_sysram_init(void) 191 { 192 struct device_node *node; 193 194 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") { 195 if (!of_device_is_available(node)) 196 continue; 197 sysram_base_addr = of_iomap(node, 0); 198 break; 199 } 200 201 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") { 202 if (!of_device_is_available(node)) 203 continue; 204 sysram_ns_base_addr = of_iomap(node, 0); 205 break; 206 } 207 } 208 209 void __init exynos_init_late(void) 210 { 211 if (of_machine_is_compatible("samsung,exynos5440")) 212 /* to be supported later */ 213 return; 214 215 pm_genpd_poweroff_unused(); 216 exynos_pm_init(); 217 } 218 219 static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, 220 int depth, void *data) 221 { 222 struct map_desc iodesc; 223 const __be32 *reg; 224 int len; 225 226 if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") && 227 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock")) 228 return 0; 229 230 reg = of_get_flat_dt_prop(node, "reg", &len); 231 if (reg == NULL || len != (sizeof(unsigned long) * 2)) 232 return 0; 233 234 iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0])); 235 iodesc.length = be32_to_cpu(reg[1]) - 1; 236 iodesc.virtual = (unsigned long)S5P_VA_CHIPID; 237 iodesc.type = MT_DEVICE; 238 iotable_init(&iodesc, 1); 239 return 1; 240 } 241 242 /* 243 * exynos_map_io 244 * 245 * register the standard cpu IO areas 246 */ 247 static void __init exynos_map_io(void) 248 { 249 if (soc_is_exynos4()) 250 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); 251 252 if (soc_is_exynos5()) 253 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); 254 } 255 256 void __init exynos_init_io(void) 257 { 258 debug_ll_io_init(); 259 260 of_scan_flat_dt(exynos_fdt_map_chipid, NULL); 261 262 /* detect cpu id and rev. */ 263 s5p_init_cpu(S5P_VA_CHIPID); 264 265 exynos_map_io(); 266 } 267 268 static void __init exynos_dt_machine_init(void) 269 { 270 struct device_node *i2c_np; 271 const char *i2c_compat = "samsung,s3c2440-i2c"; 272 unsigned int tmp; 273 int id; 274 275 /* 276 * Exynos5's legacy i2c controller and new high speed i2c 277 * controller have muxed interrupt sources. By default the 278 * interrupts for 4-channel HS-I2C controller are enabled. 279 * If node for first four channels of legacy i2c controller 280 * are available then re-configure the interrupts via the 281 * system register. 282 */ 283 if (soc_is_exynos5()) { 284 for_each_compatible_node(i2c_np, NULL, i2c_compat) { 285 if (of_device_is_available(i2c_np)) { 286 id = of_alias_get_id(i2c_np, "i2c"); 287 if (id < 4) { 288 tmp = readl(EXYNOS5_SYS_I2C_CFG); 289 writel(tmp & ~(0x1 << id), 290 EXYNOS5_SYS_I2C_CFG); 291 } 292 } 293 } 294 } 295 296 /* 297 * This is called from smp_prepare_cpus if we've built for SMP, but 298 * we still need to set it up for PM and firmware ops if not. 299 */ 300 if (!IS_ENABLED(SMP)) 301 exynos_sysram_init(); 302 303 exynos_cpuidle_init(); 304 exynos_cpufreq_init(); 305 306 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 307 } 308 309 static char const *exynos_dt_compat[] __initconst = { 310 "samsung,exynos3", 311 "samsung,exynos3250", 312 "samsung,exynos4", 313 "samsung,exynos4210", 314 "samsung,exynos4212", 315 "samsung,exynos4412", 316 "samsung,exynos5", 317 "samsung,exynos5250", 318 "samsung,exynos5260", 319 "samsung,exynos5420", 320 "samsung,exynos5440", 321 NULL 322 }; 323 324 static void __init exynos_reserve(void) 325 { 326 #ifdef CONFIG_S5P_DEV_MFC 327 int i; 328 char *mfc_mem[] = { 329 "samsung,mfc-v5", 330 "samsung,mfc-v6", 331 "samsung,mfc-v7", 332 }; 333 334 for (i = 0; i < ARRAY_SIZE(mfc_mem); i++) 335 if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i])) 336 break; 337 #endif 338 } 339 340 DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)") 341 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ 342 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 343 .l2c_aux_val = 0x3c400001, 344 .l2c_aux_mask = 0xc20fffff, 345 .smp = smp_ops(exynos_smp_ops), 346 .map_io = exynos_init_io, 347 .init_early = exynos_firmware_init, 348 .init_machine = exynos_dt_machine_init, 349 .init_late = exynos_init_late, 350 .dt_compat = exynos_dt_compat, 351 .restart = exynos_restart, 352 .reserve = exynos_reserve, 353 MACHINE_END 354