xref: /openbmc/linux/arch/arm/mach-exynos/exynos.c (revision 0e17c50f)
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Samsung Exynos Flattened Device Tree enabled machine
4 //
5 // Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
6 //		http://www.samsung.com
7 
8 #include <linux/init.h>
9 #include <linux/io.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_fdt.h>
13 #include <linux/platform_device.h>
14 #include <linux/irqchip.h>
15 #include <linux/soc/samsung/exynos-regs-pmu.h>
16 
17 #include <asm/cacheflush.h>
18 #include <asm/hardware/cache-l2x0.h>
19 #include <asm/mach/arch.h>
20 #include <asm/mach/map.h>
21 
22 #include <mach/map.h>
23 #include <plat/cpu.h>
24 
25 #include "common.h"
26 
27 static struct platform_device exynos_cpuidle = {
28 	.name              = "exynos_cpuidle",
29 #ifdef CONFIG_ARM_EXYNOS_CPUIDLE
30 	.dev.platform_data = exynos_enter_aftr,
31 #endif
32 	.id                = -1,
33 };
34 
35 void __iomem *sysram_base_addr __ro_after_init;
36 phys_addr_t sysram_base_phys __ro_after_init;
37 void __iomem *sysram_ns_base_addr __ro_after_init;
38 
39 void __init exynos_sysram_init(void)
40 {
41 	struct device_node *node;
42 
43 	for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
44 		if (!of_device_is_available(node))
45 			continue;
46 		sysram_base_addr = of_iomap(node, 0);
47 		sysram_base_phys = of_translate_address(node,
48 					   of_get_address(node, 0, NULL, NULL));
49 		break;
50 	}
51 
52 	for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") {
53 		if (!of_device_is_available(node))
54 			continue;
55 		sysram_ns_base_addr = of_iomap(node, 0);
56 		break;
57 	}
58 }
59 
60 static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
61 					int depth, void *data)
62 {
63 	struct map_desc iodesc;
64 	const __be32 *reg;
65 	int len;
66 
67 	if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid"))
68 		return 0;
69 
70 	reg = of_get_flat_dt_prop(node, "reg", &len);
71 	if (reg == NULL || len != (sizeof(unsigned long) * 2))
72 		return 0;
73 
74 	iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
75 	iodesc.length = be32_to_cpu(reg[1]) - 1;
76 	iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
77 	iodesc.type = MT_DEVICE;
78 	iotable_init(&iodesc, 1);
79 	return 1;
80 }
81 
82 static void __init exynos_init_io(void)
83 {
84 	debug_ll_io_init();
85 
86 	of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
87 
88 	/* detect cpu id and rev. */
89 	s5p_init_cpu(S5P_VA_CHIPID);
90 }
91 
92 /*
93  * Set or clear the USE_DELAYED_RESET_ASSERTION option. Used by smp code
94  * and suspend.
95  *
96  * This is necessary only on Exynos4 SoCs. When system is running
97  * USE_DELAYED_RESET_ASSERTION should be set so the ARM CLK clock down
98  * feature could properly detect global idle state when secondary CPU is
99  * powered down.
100  *
101  * However this should not be set when such system is going into suspend.
102  */
103 void exynos_set_delayed_reset_assertion(bool enable)
104 {
105 	if (of_machine_is_compatible("samsung,exynos4")) {
106 		unsigned int tmp, core_id;
107 
108 		for (core_id = 0; core_id < num_possible_cpus(); core_id++) {
109 			tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id));
110 			if (enable)
111 				tmp |= S5P_USE_DELAYED_RESET_ASSERTION;
112 			else
113 				tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION);
114 			pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id));
115 		}
116 	}
117 }
118 
119 /*
120  * Apparently, these SoCs are not able to wake-up from suspend using
121  * the PMU. Too bad. Should they suddenly become capable of such a
122  * feat, the matches below should be moved to suspend.c.
123  */
124 static const struct of_device_id exynos_dt_pmu_match[] = {
125 	{ .compatible = "samsung,exynos5260-pmu" },
126 	{ .compatible = "samsung,exynos5410-pmu" },
127 	{ /*sentinel*/ },
128 };
129 
130 static void exynos_map_pmu(void)
131 {
132 	struct device_node *np;
133 
134 	np = of_find_matching_node(NULL, exynos_dt_pmu_match);
135 	if (np)
136 		pmu_base_addr = of_iomap(np, 0);
137 }
138 
139 static void __init exynos_init_irq(void)
140 {
141 	irqchip_init();
142 	/*
143 	 * Since platsmp.c needs pmu base address by the time
144 	 * DT is not unflatten so we can't use DT APIs before
145 	 * init_irq
146 	 */
147 	exynos_map_pmu();
148 }
149 
150 static void __init exynos_dt_machine_init(void)
151 {
152 	/*
153 	 * This is called from smp_prepare_cpus if we've built for SMP, but
154 	 * we still need to set it up for PM and firmware ops if not.
155 	 */
156 	if (!IS_ENABLED(CONFIG_SMP))
157 		exynos_sysram_init();
158 
159 #if defined(CONFIG_SMP) && defined(CONFIG_ARM_EXYNOS_CPUIDLE)
160 	if (of_machine_is_compatible("samsung,exynos4210") ||
161 	    of_machine_is_compatible("samsung,exynos3250"))
162 		exynos_cpuidle.dev.platform_data = &cpuidle_coupled_exynos_data;
163 #endif
164 	if (of_machine_is_compatible("samsung,exynos4210") ||
165 	    (of_machine_is_compatible("samsung,exynos4412") &&
166 	     (of_machine_is_compatible("samsung,trats2") ||
167 		  of_machine_is_compatible("samsung,midas"))) ||
168 	    of_machine_is_compatible("samsung,exynos3250") ||
169 	    of_machine_is_compatible("samsung,exynos5250"))
170 		platform_device_register(&exynos_cpuidle);
171 }
172 
173 static char const *const exynos_dt_compat[] __initconst = {
174 	"samsung,exynos3",
175 	"samsung,exynos3250",
176 	"samsung,exynos4",
177 	"samsung,exynos4210",
178 	"samsung,exynos4412",
179 	"samsung,exynos5",
180 	"samsung,exynos5250",
181 	"samsung,exynos5260",
182 	"samsung,exynos5420",
183 	NULL
184 };
185 
186 static void __init exynos_dt_fixup(void)
187 {
188 	/*
189 	 * Some versions of uboot pass garbage entries in the memory node,
190 	 * use the old CONFIG_ARM_NR_BANKS
191 	 */
192 	of_fdt_limit_memory(8);
193 }
194 
195 DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)")
196 	.l2c_aux_val	= 0x3c400001,
197 	.l2c_aux_mask	= 0xc20fffff,
198 	.smp		= smp_ops(exynos_smp_ops),
199 	.map_io		= exynos_init_io,
200 	.init_early	= exynos_firmware_init,
201 	.init_irq	= exynos_init_irq,
202 	.init_machine	= exynos_dt_machine_init,
203 	.init_late	= exynos_pm_init,
204 	.dt_compat	= exynos_dt_compat,
205 	.dt_fixup	= exynos_dt_fixup,
206 MACHINE_END
207