1 /* 2 * arch/arm/mach-ep93xx/ts72xx.c 3 * Technologic Systems TS72xx SBC support. 4 * 5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or (at 10 * your option) any later version. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/platform_device.h> 18 #include <linux/io.h> 19 #include <linux/mtd/platnand.h> 20 #include <linux/spi/spi.h> 21 #include <linux/spi/flash.h> 22 #include <linux/spi/mmc_spi.h> 23 #include <linux/mmc/host.h> 24 #include <linux/platform_data/spi-ep93xx.h> 25 26 #include <mach/gpio-ep93xx.h> 27 #include <mach/hardware.h> 28 #include <mach/irqs.h> 29 30 #include <asm/mach-types.h> 31 #include <asm/mach/map.h> 32 #include <asm/mach/arch.h> 33 34 #include "soc.h" 35 #include "ts72xx.h" 36 37 /************************************************************************* 38 * IO map 39 *************************************************************************/ 40 static struct map_desc ts72xx_io_desc[] __initdata = { 41 { 42 .virtual = (unsigned long)TS72XX_MODEL_VIRT_BASE, 43 .pfn = __phys_to_pfn(TS72XX_MODEL_PHYS_BASE), 44 .length = TS72XX_MODEL_SIZE, 45 .type = MT_DEVICE, 46 }, { 47 .virtual = (unsigned long)TS72XX_OPTIONS_VIRT_BASE, 48 .pfn = __phys_to_pfn(TS72XX_OPTIONS_PHYS_BASE), 49 .length = TS72XX_OPTIONS_SIZE, 50 .type = MT_DEVICE, 51 }, { 52 .virtual = (unsigned long)TS72XX_OPTIONS2_VIRT_BASE, 53 .pfn = __phys_to_pfn(TS72XX_OPTIONS2_PHYS_BASE), 54 .length = TS72XX_OPTIONS2_SIZE, 55 .type = MT_DEVICE, 56 }, { 57 .virtual = (unsigned long)TS72XX_CPLDVER_VIRT_BASE, 58 .pfn = __phys_to_pfn(TS72XX_CPLDVER_PHYS_BASE), 59 .length = TS72XX_CPLDVER_SIZE, 60 .type = MT_DEVICE, 61 } 62 }; 63 64 static void __init ts72xx_map_io(void) 65 { 66 ep93xx_map_io(); 67 iotable_init(ts72xx_io_desc, ARRAY_SIZE(ts72xx_io_desc)); 68 } 69 70 71 /************************************************************************* 72 * NAND flash 73 *************************************************************************/ 74 #define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */ 75 #define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */ 76 77 static void ts72xx_nand_hwcontrol(struct nand_chip *chip, 78 int cmd, unsigned int ctrl) 79 { 80 if (ctrl & NAND_CTRL_CHANGE) { 81 void __iomem *addr = chip->legacy.IO_ADDR_R; 82 unsigned char bits; 83 84 addr += (1 << TS72XX_NAND_CONTROL_ADDR_LINE); 85 86 bits = __raw_readb(addr) & ~0x07; 87 bits |= (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ 88 bits |= (ctrl & NAND_CLE); /* bit 1 -> bit 1 */ 89 bits |= (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ 90 91 __raw_writeb(bits, addr); 92 } 93 94 if (cmd != NAND_CMD_NONE) 95 __raw_writeb(cmd, chip->legacy.IO_ADDR_W); 96 } 97 98 static int ts72xx_nand_device_ready(struct nand_chip *chip) 99 { 100 void __iomem *addr = chip->legacy.IO_ADDR_R; 101 102 addr += (1 << TS72XX_NAND_BUSY_ADDR_LINE); 103 104 return !!(__raw_readb(addr) & 0x20); 105 } 106 107 #define TS72XX_BOOTROM_PART_SIZE (SZ_16K) 108 #define TS72XX_REDBOOT_PART_SIZE (SZ_2M + SZ_1M) 109 110 static struct mtd_partition ts72xx_nand_parts[] = { 111 { 112 .name = "TS-BOOTROM", 113 .offset = 0, 114 .size = TS72XX_BOOTROM_PART_SIZE, 115 .mask_flags = MTD_WRITEABLE, /* force read-only */ 116 }, { 117 .name = "Linux", 118 .offset = MTDPART_OFS_RETAIN, 119 .size = TS72XX_REDBOOT_PART_SIZE, 120 /* leave so much for last partition */ 121 }, { 122 .name = "RedBoot", 123 .offset = MTDPART_OFS_APPEND, 124 .size = MTDPART_SIZ_FULL, 125 .mask_flags = MTD_WRITEABLE, /* force read-only */ 126 }, 127 }; 128 129 static struct platform_nand_data ts72xx_nand_data = { 130 .chip = { 131 .nr_chips = 1, 132 .chip_offset = 0, 133 .chip_delay = 15, 134 }, 135 .ctrl = { 136 .cmd_ctrl = ts72xx_nand_hwcontrol, 137 .dev_ready = ts72xx_nand_device_ready, 138 }, 139 }; 140 141 static struct resource ts72xx_nand_resource[] = { 142 { 143 .start = 0, /* filled in later */ 144 .end = 0, /* filled in later */ 145 .flags = IORESOURCE_MEM, 146 }, 147 }; 148 149 static struct platform_device ts72xx_nand_flash = { 150 .name = "gen_nand", 151 .id = -1, 152 .dev.platform_data = &ts72xx_nand_data, 153 .resource = ts72xx_nand_resource, 154 .num_resources = ARRAY_SIZE(ts72xx_nand_resource), 155 }; 156 157 void __init ts72xx_register_flash(struct mtd_partition *parts, int n, 158 resource_size_t start) 159 { 160 /* 161 * TS7200 has NOR flash all other TS72xx board have NAND flash. 162 */ 163 if (board_is_ts7200()) { 164 ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M); 165 } else { 166 ts72xx_nand_resource[0].start = start; 167 ts72xx_nand_resource[0].end = start + SZ_16M - 1; 168 169 ts72xx_nand_data.chip.partitions = parts; 170 ts72xx_nand_data.chip.nr_partitions = n; 171 172 platform_device_register(&ts72xx_nand_flash); 173 } 174 } 175 176 /************************************************************************* 177 * RTC M48T86 178 *************************************************************************/ 179 #define TS72XX_RTC_INDEX_PHYS_BASE (EP93XX_CS1_PHYS_BASE + 0x00800000) 180 #define TS72XX_RTC_DATA_PHYS_BASE (EP93XX_CS1_PHYS_BASE + 0x01700000) 181 182 static struct resource ts72xx_rtc_resources[] = { 183 DEFINE_RES_MEM(TS72XX_RTC_INDEX_PHYS_BASE, 0x01), 184 DEFINE_RES_MEM(TS72XX_RTC_DATA_PHYS_BASE, 0x01), 185 }; 186 187 static struct platform_device ts72xx_rtc_device = { 188 .name = "rtc-m48t86", 189 .id = -1, 190 .resource = ts72xx_rtc_resources, 191 .num_resources = ARRAY_SIZE(ts72xx_rtc_resources), 192 }; 193 194 /************************************************************************* 195 * Watchdog (in CPLD) 196 *************************************************************************/ 197 #define TS72XX_WDT_CONTROL_PHYS_BASE (EP93XX_CS2_PHYS_BASE + 0x03800000) 198 #define TS72XX_WDT_FEED_PHYS_BASE (EP93XX_CS2_PHYS_BASE + 0x03c00000) 199 200 static struct resource ts72xx_wdt_resources[] = { 201 DEFINE_RES_MEM(TS72XX_WDT_CONTROL_PHYS_BASE, 0x01), 202 DEFINE_RES_MEM(TS72XX_WDT_FEED_PHYS_BASE, 0x01), 203 }; 204 205 static struct platform_device ts72xx_wdt_device = { 206 .name = "ts72xx-wdt", 207 .id = -1, 208 .resource = ts72xx_wdt_resources, 209 .num_resources = ARRAY_SIZE(ts72xx_wdt_resources), 210 }; 211 212 /************************************************************************* 213 * ETH 214 *************************************************************************/ 215 static struct ep93xx_eth_data __initdata ts72xx_eth_data = { 216 .phy_id = 1, 217 }; 218 219 /************************************************************************* 220 * SPI SD/MMC host 221 *************************************************************************/ 222 #define BK3_EN_SDCARD_PHYS_BASE 0x12400000 223 #define BK3_EN_SDCARD_PWR 0x0 224 #define BK3_DIS_SDCARD_PWR 0x0C 225 static void bk3_mmc_spi_setpower(struct device *dev, unsigned int vdd) 226 { 227 void __iomem *pwr_sd = ioremap(BK3_EN_SDCARD_PHYS_BASE, SZ_4K); 228 229 if (!pwr_sd) { 230 pr_err("Failed to enable SD card power!"); 231 return; 232 } 233 234 pr_debug("%s: SD card pwr %s VDD:0x%x\n", __func__, 235 !!vdd ? "ON" : "OFF", vdd); 236 237 if (!!vdd) 238 __raw_writeb(BK3_EN_SDCARD_PWR, pwr_sd); 239 else 240 __raw_writeb(BK3_DIS_SDCARD_PWR, pwr_sd); 241 242 iounmap(pwr_sd); 243 } 244 245 static struct mmc_spi_platform_data bk3_spi_mmc_data = { 246 .detect_delay = 500, 247 .powerup_msecs = 100, 248 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, 249 .caps = MMC_CAP_NONREMOVABLE, 250 .setpower = bk3_mmc_spi_setpower, 251 }; 252 253 /************************************************************************* 254 * SPI Bus - SD card access 255 *************************************************************************/ 256 static struct spi_board_info bk3_spi_board_info[] __initdata = { 257 { 258 .modalias = "mmc_spi", 259 .platform_data = &bk3_spi_mmc_data, 260 .max_speed_hz = 7.4E6, 261 .bus_num = 0, 262 .chip_select = 0, 263 .mode = SPI_MODE_0, 264 }, 265 }; 266 267 /* 268 * This is a stub -> the FGPIO[3] pin is not connected on the schematic 269 * The all work is performed automatically by !SPI_FRAME (SFRM1) and 270 * goes through CPLD 271 */ 272 static int bk3_spi_chipselects[] __initdata = { 273 EP93XX_GPIO_LINE_F(3), 274 }; 275 276 static struct ep93xx_spi_info bk3_spi_master __initdata = { 277 .chipselect = bk3_spi_chipselects, 278 .num_chipselect = ARRAY_SIZE(bk3_spi_chipselects), 279 .use_dma = 1, 280 }; 281 282 /************************************************************************* 283 * TS72XX support code 284 *************************************************************************/ 285 #if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX) 286 287 /* Relative to EP93XX_CS1_PHYS_BASE */ 288 #define TS73XX_FPGA_LOADER_BASE 0x03c00000 289 290 static struct resource ts73xx_fpga_resources[] = { 291 { 292 .start = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE, 293 .end = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1, 294 .flags = IORESOURCE_MEM, 295 }, 296 }; 297 298 static struct platform_device ts73xx_fpga_device = { 299 .name = "ts73xx-fpga-mgr", 300 .id = -1, 301 .resource = ts73xx_fpga_resources, 302 .num_resources = ARRAY_SIZE(ts73xx_fpga_resources), 303 }; 304 305 #endif 306 307 /************************************************************************* 308 * SPI Bus 309 *************************************************************************/ 310 static struct spi_board_info ts72xx_spi_devices[] __initdata = { 311 { 312 .modalias = "tmp122", 313 .max_speed_hz = 2 * 1000 * 1000, 314 .bus_num = 0, 315 .chip_select = 0, 316 }, 317 }; 318 319 static int ts72xx_spi_chipselects[] __initdata = { 320 EP93XX_GPIO_LINE_F(2), /* DIO_17 */ 321 }; 322 323 static struct ep93xx_spi_info ts72xx_spi_info __initdata = { 324 .chipselect = ts72xx_spi_chipselects, 325 .num_chipselect = ARRAY_SIZE(ts72xx_spi_chipselects), 326 }; 327 328 static void __init ts72xx_init_machine(void) 329 { 330 ep93xx_init_devices(); 331 ts72xx_register_flash(ts72xx_nand_parts, ARRAY_SIZE(ts72xx_nand_parts), 332 is_ts9420_installed() ? 333 EP93XX_CS7_PHYS_BASE : EP93XX_CS6_PHYS_BASE); 334 platform_device_register(&ts72xx_rtc_device); 335 platform_device_register(&ts72xx_wdt_device); 336 337 ep93xx_register_eth(&ts72xx_eth_data, 1); 338 #if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX) 339 if (board_is_ts7300()) 340 platform_device_register(&ts73xx_fpga_device); 341 #endif 342 ep93xx_register_spi(&ts72xx_spi_info, ts72xx_spi_devices, 343 ARRAY_SIZE(ts72xx_spi_devices)); 344 } 345 346 MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC") 347 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 348 .atag_offset = 0x100, 349 .map_io = ts72xx_map_io, 350 .init_irq = ep93xx_init_irq, 351 .init_time = ep93xx_timer_init, 352 .init_machine = ts72xx_init_machine, 353 .init_late = ep93xx_init_late, 354 .restart = ep93xx_restart, 355 MACHINE_END 356 357 /************************************************************************* 358 * EP93xx I2S audio peripheral handling 359 *************************************************************************/ 360 static struct resource ep93xx_i2s_resource[] = { 361 DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100), 362 DEFINE_RES_IRQ_NAMED(IRQ_EP93XX_SAI, "spilink i2s slave"), 363 }; 364 365 static struct platform_device ep93xx_i2s_device = { 366 .name = "ep93xx-spilink-i2s", 367 .id = -1, 368 .num_resources = ARRAY_SIZE(ep93xx_i2s_resource), 369 .resource = ep93xx_i2s_resource, 370 }; 371 372 /************************************************************************* 373 * BK3 support code 374 *************************************************************************/ 375 static struct mtd_partition bk3_nand_parts[] = { 376 { 377 .name = "System", 378 .offset = 0x00000000, 379 .size = 0x01e00000, 380 }, { 381 .name = "Data", 382 .offset = 0x01e00000, 383 .size = 0x05f20000 384 }, { 385 .name = "RedBoot", 386 .offset = 0x07d20000, 387 .size = 0x002e0000, 388 .mask_flags = MTD_WRITEABLE, /* force RO */ 389 }, 390 }; 391 392 static void __init bk3_init_machine(void) 393 { 394 ep93xx_init_devices(); 395 396 ts72xx_register_flash(bk3_nand_parts, ARRAY_SIZE(bk3_nand_parts), 397 EP93XX_CS6_PHYS_BASE); 398 399 ep93xx_register_eth(&ts72xx_eth_data, 1); 400 401 ep93xx_register_spi(&bk3_spi_master, bk3_spi_board_info, 402 ARRAY_SIZE(bk3_spi_board_info)); 403 404 /* Configure ep93xx's I2S to use AC97 pins */ 405 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97); 406 platform_device_register(&ep93xx_i2s_device); 407 } 408 409 MACHINE_START(BK3, "Liebherr controller BK3.1") 410 /* Maintainer: Lukasz Majewski <lukma@denx.de> */ 411 .atag_offset = 0x100, 412 .map_io = ts72xx_map_io, 413 .init_irq = ep93xx_init_irq, 414 .init_time = ep93xx_timer_init, 415 .init_machine = bk3_init_machine, 416 .init_late = ep93xx_init_late, 417 .restart = ep93xx_restart, 418 MACHINE_END 419