1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
3 #include <linux/init.h>
4 #include <linux/clocksource.h>
5 #include <linux/clockchips.h>
6 #include <linux/sched_clock.h>
7 #include <linux/interrupt.h>
8 #include <linux/irq.h>
9 #include <linux/io.h>
10 #include <asm/mach/time.h>
11 #include "soc.h"
12 
13 /*************************************************************************
14  * Timer handling for EP93xx
15  *************************************************************************
16  * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and
17  * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
18  * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,
19  * is free-running, and can't generate interrupts.
20  *
21  * The 508 kHz timers are ideal for use for the timer interrupt, as the
22  * most common values of HZ divide 508 kHz nicely.  We pick the 32 bit
23  * timer (timer 3) to get as long sleep intervals as possible when using
24  * CONFIG_NO_HZ.
25  *
26  * The higher clock rate of timer 4 makes it a better choice than the
27  * other timers for use as clock source and for sched_clock(), providing
28  * a stable 40 bit time base.
29  *************************************************************************
30  */
31 #define EP93XX_TIMER_REG(x)		(EP93XX_TIMER_BASE + (x))
32 #define EP93XX_TIMER1_LOAD		EP93XX_TIMER_REG(0x00)
33 #define EP93XX_TIMER1_VALUE		EP93XX_TIMER_REG(0x04)
34 #define EP93XX_TIMER1_CONTROL		EP93XX_TIMER_REG(0x08)
35 #define EP93XX_TIMER123_CONTROL_ENABLE	(1 << 7)
36 #define EP93XX_TIMER123_CONTROL_MODE	(1 << 6)
37 #define EP93XX_TIMER123_CONTROL_CLKSEL	(1 << 3)
38 #define EP93XX_TIMER1_CLEAR		EP93XX_TIMER_REG(0x0c)
39 #define EP93XX_TIMER2_LOAD		EP93XX_TIMER_REG(0x20)
40 #define EP93XX_TIMER2_VALUE		EP93XX_TIMER_REG(0x24)
41 #define EP93XX_TIMER2_CONTROL		EP93XX_TIMER_REG(0x28)
42 #define EP93XX_TIMER2_CLEAR		EP93XX_TIMER_REG(0x2c)
43 #define EP93XX_TIMER4_VALUE_LOW		EP93XX_TIMER_REG(0x60)
44 #define EP93XX_TIMER4_VALUE_HIGH	EP93XX_TIMER_REG(0x64)
45 #define EP93XX_TIMER4_VALUE_HIGH_ENABLE	(1 << 8)
46 #define EP93XX_TIMER3_LOAD		EP93XX_TIMER_REG(0x80)
47 #define EP93XX_TIMER3_VALUE		EP93XX_TIMER_REG(0x84)
48 #define EP93XX_TIMER3_CONTROL		EP93XX_TIMER_REG(0x88)
49 #define EP93XX_TIMER3_CLEAR		EP93XX_TIMER_REG(0x8c)
50 
51 #define EP93XX_TIMER123_RATE		508469
52 #define EP93XX_TIMER4_RATE		983040
53 
54 static u64 notrace ep93xx_read_sched_clock(void)
55 {
56 	u64 ret;
57 
58 	ret = readl(EP93XX_TIMER4_VALUE_LOW);
59 	ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
60 	return ret;
61 }
62 
63 u64 ep93xx_clocksource_read(struct clocksource *c)
64 {
65 	u64 ret;
66 
67 	ret = readl(EP93XX_TIMER4_VALUE_LOW);
68 	ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
69 	return (u64) ret;
70 }
71 
72 static int ep93xx_clkevt_set_next_event(unsigned long next,
73 					struct clock_event_device *evt)
74 {
75 	/* Default mode: periodic, off, 508 kHz */
76 	u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
77 		    EP93XX_TIMER123_CONTROL_CLKSEL;
78 
79 	/* Clear timer */
80 	writel(tmode, EP93XX_TIMER3_CONTROL);
81 
82 	/* Set next event */
83 	writel(next, EP93XX_TIMER3_LOAD);
84 	writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
85 	       EP93XX_TIMER3_CONTROL);
86         return 0;
87 }
88 
89 
90 static int ep93xx_clkevt_shutdown(struct clock_event_device *evt)
91 {
92 	/* Disable timer */
93 	writel(0, EP93XX_TIMER3_CONTROL);
94 
95 	return 0;
96 }
97 
98 static struct clock_event_device ep93xx_clockevent = {
99 	.name			= "timer1",
100 	.features		= CLOCK_EVT_FEAT_ONESHOT,
101 	.set_state_shutdown	= ep93xx_clkevt_shutdown,
102 	.set_state_oneshot	= ep93xx_clkevt_shutdown,
103 	.tick_resume		= ep93xx_clkevt_shutdown,
104 	.set_next_event		= ep93xx_clkevt_set_next_event,
105 	.rating			= 300,
106 };
107 
108 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
109 {
110 	struct clock_event_device *evt = dev_id;
111 
112 	/* Writing any value clears the timer interrupt */
113 	writel(1, EP93XX_TIMER3_CLEAR);
114 
115 	evt->event_handler(evt);
116 
117 	return IRQ_HANDLED;
118 }
119 
120 void __init ep93xx_timer_init(void)
121 {
122 	int irq = IRQ_EP93XX_TIMER3;
123 	unsigned long flags = IRQF_TIMER | IRQF_IRQPOLL;
124 
125 	/* Enable and register clocksource and sched_clock on timer 4 */
126 	writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
127 	       EP93XX_TIMER4_VALUE_HIGH);
128 	clocksource_mmio_init(NULL, "timer4",
129 			      EP93XX_TIMER4_RATE, 200, 40,
130 			      ep93xx_clocksource_read);
131 	sched_clock_register(ep93xx_read_sched_clock, 40,
132 			     EP93XX_TIMER4_RATE);
133 
134 	/* Set up clockevent on timer 3 */
135 	if (request_irq(irq, ep93xx_timer_interrupt, flags, "ep93xx timer",
136 			&ep93xx_clockevent))
137 		pr_err("Failed to request irq %d (ep93xx timer)\n", irq);
138 	clockevents_config_and_register(&ep93xx_clockevent,
139 					EP93XX_TIMER123_RATE,
140 					1,
141 					0xffffffffU);
142 }
143