1 /* 2 * arch/arm/mach-ep93xx/core.c 3 * Core routines for Cirrus EP93xx chips. 4 * 5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> 6 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> 7 * 8 * Thanks go to Michael Burian and Ray Lehtiniemi for their key 9 * role in the ep93xx linux community. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/interrupt.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/timex.h> 23 #include <linux/io.h> 24 #include <linux/gpio.h> 25 #include <linux/leds.h> 26 #include <linux/termios.h> 27 #include <linux/amba/bus.h> 28 #include <linux/amba/serial.h> 29 #include <linux/i2c.h> 30 #include <linux/i2c-gpio.h> 31 32 #include <mach/hardware.h> 33 34 #include <asm/mach/map.h> 35 #include <asm/mach/time.h> 36 #include <asm/mach/irq.h> 37 38 #include <asm/hardware/vic.h> 39 40 41 /************************************************************************* 42 * Static I/O mappings that are needed for all EP93xx platforms 43 *************************************************************************/ 44 static struct map_desc ep93xx_io_desc[] __initdata = { 45 { 46 .virtual = EP93XX_AHB_VIRT_BASE, 47 .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE), 48 .length = EP93XX_AHB_SIZE, 49 .type = MT_DEVICE, 50 }, { 51 .virtual = EP93XX_APB_VIRT_BASE, 52 .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE), 53 .length = EP93XX_APB_SIZE, 54 .type = MT_DEVICE, 55 }, 56 }; 57 58 void __init ep93xx_map_io(void) 59 { 60 iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc)); 61 } 62 63 64 /************************************************************************* 65 * Timer handling for EP93xx 66 ************************************************************************* 67 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and 68 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate 69 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, 70 * is free-running, and can't generate interrupts. 71 * 72 * The 508 kHz timers are ideal for use for the timer interrupt, as the 73 * most common values of HZ divide 508 kHz nicely. We pick one of the 16 74 * bit timers (timer 1) since we don't need more than 16 bits of reload 75 * value as long as HZ >= 8. 76 * 77 * The higher clock rate of timer 4 makes it a better choice than the 78 * other timers for use in gettimeoffset(), while the fact that it can't 79 * generate interrupts means we don't have to worry about not being able 80 * to use this timer for something else. We also use timer 4 for keeping 81 * track of lost jiffies. 82 */ 83 static unsigned int last_jiffy_time; 84 85 #define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ) 86 87 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) 88 { 89 __raw_writel(1, EP93XX_TIMER1_CLEAR); 90 while ((signed long) 91 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time) 92 >= TIMER4_TICKS_PER_JIFFY) { 93 last_jiffy_time += TIMER4_TICKS_PER_JIFFY; 94 timer_tick(); 95 } 96 97 return IRQ_HANDLED; 98 } 99 100 static struct irqaction ep93xx_timer_irq = { 101 .name = "ep93xx timer", 102 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 103 .handler = ep93xx_timer_interrupt, 104 }; 105 106 static void __init ep93xx_timer_init(void) 107 { 108 /* Enable periodic HZ timer. */ 109 __raw_writel(0x48, EP93XX_TIMER1_CONTROL); 110 __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD); 111 __raw_writel(0xc8, EP93XX_TIMER1_CONTROL); 112 113 /* Enable lost jiffy timer. */ 114 __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH); 115 116 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq); 117 } 118 119 static unsigned long ep93xx_gettimeoffset(void) 120 { 121 int offset; 122 123 offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time; 124 125 /* Calculate (1000000 / 983040) * offset. */ 126 return offset + (53 * offset / 3072); 127 } 128 129 struct sys_timer ep93xx_timer = { 130 .init = ep93xx_timer_init, 131 .offset = ep93xx_gettimeoffset, 132 }; 133 134 135 /************************************************************************* 136 * GPIO handling for EP93xx 137 *************************************************************************/ 138 static unsigned char gpio_int_unmasked[3]; 139 static unsigned char gpio_int_enabled[3]; 140 static unsigned char gpio_int_type1[3]; 141 static unsigned char gpio_int_type2[3]; 142 static unsigned char gpio_int_debounce[3]; 143 144 /* Port ordering is: A B F */ 145 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c }; 146 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 }; 147 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; 148 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 }; 149 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 }; 150 151 void ep93xx_gpio_update_int_params(unsigned port) 152 { 153 BUG_ON(port > 2); 154 155 __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port])); 156 157 __raw_writeb(gpio_int_type2[port], 158 EP93XX_GPIO_REG(int_type2_register_offset[port])); 159 160 __raw_writeb(gpio_int_type1[port], 161 EP93XX_GPIO_REG(int_type1_register_offset[port])); 162 163 __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port], 164 EP93XX_GPIO_REG(int_en_register_offset[port])); 165 } 166 167 void ep93xx_gpio_int_mask(unsigned line) 168 { 169 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7)); 170 } 171 172 void ep93xx_gpio_int_debounce(unsigned int irq, int enable) 173 { 174 int line = irq_to_gpio(irq); 175 int port = line >> 3; 176 int port_mask = 1 << (line & 7); 177 178 if (enable) 179 gpio_int_debounce[port] |= port_mask; 180 else 181 gpio_int_debounce[port] &= ~port_mask; 182 183 __raw_writeb(gpio_int_debounce[port], 184 EP93XX_GPIO_REG(int_debounce_register_offset[port])); 185 } 186 EXPORT_SYMBOL(ep93xx_gpio_int_debounce); 187 188 /************************************************************************* 189 * EP93xx IRQ handling 190 *************************************************************************/ 191 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc) 192 { 193 unsigned char status; 194 int i; 195 196 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS); 197 for (i = 0; i < 8; i++) { 198 if (status & (1 << i)) { 199 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i; 200 generic_handle_irq(gpio_irq); 201 } 202 } 203 204 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS); 205 for (i = 0; i < 8; i++) { 206 if (status & (1 << i)) { 207 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i; 208 desc = irq_desc + gpio_irq; 209 generic_handle_irq(gpio_irq); 210 } 211 } 212 } 213 214 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc) 215 { 216 /* 217 * map discontiguous hw irq range to continous sw irq range: 218 * 219 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7}) 220 */ 221 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ 222 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx; 223 224 generic_handle_irq(gpio_irq); 225 } 226 227 static void ep93xx_gpio_irq_ack(unsigned int irq) 228 { 229 int line = irq_to_gpio(irq); 230 int port = line >> 3; 231 int port_mask = 1 << (line & 7); 232 233 if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 234 gpio_int_type2[port] ^= port_mask; /* switch edge direction */ 235 ep93xx_gpio_update_int_params(port); 236 } 237 238 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); 239 } 240 241 static void ep93xx_gpio_irq_mask_ack(unsigned int irq) 242 { 243 int line = irq_to_gpio(irq); 244 int port = line >> 3; 245 int port_mask = 1 << (line & 7); 246 247 if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 248 gpio_int_type2[port] ^= port_mask; /* switch edge direction */ 249 250 gpio_int_unmasked[port] &= ~port_mask; 251 ep93xx_gpio_update_int_params(port); 252 253 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); 254 } 255 256 static void ep93xx_gpio_irq_mask(unsigned int irq) 257 { 258 int line = irq_to_gpio(irq); 259 int port = line >> 3; 260 261 gpio_int_unmasked[port] &= ~(1 << (line & 7)); 262 ep93xx_gpio_update_int_params(port); 263 } 264 265 static void ep93xx_gpio_irq_unmask(unsigned int irq) 266 { 267 int line = irq_to_gpio(irq); 268 int port = line >> 3; 269 270 gpio_int_unmasked[port] |= 1 << (line & 7); 271 ep93xx_gpio_update_int_params(port); 272 } 273 274 275 /* 276 * gpio_int_type1 controls whether the interrupt is level (0) or 277 * edge (1) triggered, while gpio_int_type2 controls whether it 278 * triggers on low/falling (0) or high/rising (1). 279 */ 280 static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type) 281 { 282 struct irq_desc *desc = irq_desc + irq; 283 const int gpio = irq_to_gpio(irq); 284 const int port = gpio >> 3; 285 const int port_mask = 1 << (gpio & 7); 286 287 gpio_direction_input(gpio); 288 289 switch (type) { 290 case IRQ_TYPE_EDGE_RISING: 291 gpio_int_type1[port] |= port_mask; 292 gpio_int_type2[port] |= port_mask; 293 desc->handle_irq = handle_edge_irq; 294 break; 295 case IRQ_TYPE_EDGE_FALLING: 296 gpio_int_type1[port] |= port_mask; 297 gpio_int_type2[port] &= ~port_mask; 298 desc->handle_irq = handle_edge_irq; 299 break; 300 case IRQ_TYPE_LEVEL_HIGH: 301 gpio_int_type1[port] &= ~port_mask; 302 gpio_int_type2[port] |= port_mask; 303 desc->handle_irq = handle_level_irq; 304 break; 305 case IRQ_TYPE_LEVEL_LOW: 306 gpio_int_type1[port] &= ~port_mask; 307 gpio_int_type2[port] &= ~port_mask; 308 desc->handle_irq = handle_level_irq; 309 break; 310 case IRQ_TYPE_EDGE_BOTH: 311 gpio_int_type1[port] |= port_mask; 312 /* set initial polarity based on current input level */ 313 if (gpio_get_value(gpio)) 314 gpio_int_type2[port] &= ~port_mask; /* falling */ 315 else 316 gpio_int_type2[port] |= port_mask; /* rising */ 317 desc->handle_irq = handle_edge_irq; 318 break; 319 default: 320 pr_err("ep93xx: failed to set irq type %d for gpio %d\n", 321 type, gpio); 322 return -EINVAL; 323 } 324 325 gpio_int_enabled[port] |= port_mask; 326 327 desc->status &= ~IRQ_TYPE_SENSE_MASK; 328 desc->status |= type & IRQ_TYPE_SENSE_MASK; 329 330 ep93xx_gpio_update_int_params(port); 331 332 return 0; 333 } 334 335 static struct irq_chip ep93xx_gpio_irq_chip = { 336 .name = "GPIO", 337 .ack = ep93xx_gpio_irq_ack, 338 .mask_ack = ep93xx_gpio_irq_mask_ack, 339 .mask = ep93xx_gpio_irq_mask, 340 .unmask = ep93xx_gpio_irq_unmask, 341 .set_type = ep93xx_gpio_irq_type, 342 }; 343 344 345 void __init ep93xx_init_irq(void) 346 { 347 int gpio_irq; 348 349 vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); 350 vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); 351 352 for (gpio_irq = gpio_to_irq(0); 353 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { 354 set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip); 355 set_irq_handler(gpio_irq, handle_level_irq); 356 set_irq_flags(gpio_irq, IRQF_VALID); 357 } 358 359 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); 360 set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler); 361 set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler); 362 set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler); 363 set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler); 364 set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler); 365 set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler); 366 set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler); 367 set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler); 368 } 369 370 371 /************************************************************************* 372 * EP93xx System Controller Software Locked register handling 373 *************************************************************************/ 374 375 /* 376 * syscon_swlock prevents anything else from writing to the syscon 377 * block while a software locked register is being written. 378 */ 379 static DEFINE_SPINLOCK(syscon_swlock); 380 381 void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg) 382 { 383 unsigned long flags; 384 385 spin_lock_irqsave(&syscon_swlock, flags); 386 387 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); 388 __raw_writel(val, reg); 389 390 spin_unlock_irqrestore(&syscon_swlock, flags); 391 } 392 EXPORT_SYMBOL(ep93xx_syscon_swlocked_write); 393 394 void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits) 395 { 396 unsigned long flags; 397 unsigned int val; 398 399 spin_lock_irqsave(&syscon_swlock, flags); 400 401 val = __raw_readl(EP93XX_SYSCON_DEVCFG); 402 val |= set_bits; 403 val &= ~clear_bits; 404 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); 405 __raw_writel(val, EP93XX_SYSCON_DEVCFG); 406 407 spin_unlock_irqrestore(&syscon_swlock, flags); 408 } 409 EXPORT_SYMBOL(ep93xx_devcfg_set_clear); 410 411 412 /************************************************************************* 413 * EP93xx peripheral handling 414 *************************************************************************/ 415 #define EP93XX_UART_MCR_OFFSET (0x0100) 416 417 static void ep93xx_uart_set_mctrl(struct amba_device *dev, 418 void __iomem *base, unsigned int mctrl) 419 { 420 unsigned int mcr; 421 422 mcr = 0; 423 if (!(mctrl & TIOCM_RTS)) 424 mcr |= 2; 425 if (!(mctrl & TIOCM_DTR)) 426 mcr |= 1; 427 428 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); 429 } 430 431 static struct amba_pl010_data ep93xx_uart_data = { 432 .set_mctrl = ep93xx_uart_set_mctrl, 433 }; 434 435 static struct amba_device uart1_device = { 436 .dev = { 437 .init_name = "apb:uart1", 438 .platform_data = &ep93xx_uart_data, 439 }, 440 .res = { 441 .start = EP93XX_UART1_PHYS_BASE, 442 .end = EP93XX_UART1_PHYS_BASE + 0x0fff, 443 .flags = IORESOURCE_MEM, 444 }, 445 .irq = { IRQ_EP93XX_UART1, NO_IRQ }, 446 .periphid = 0x00041010, 447 }; 448 449 static struct amba_device uart2_device = { 450 .dev = { 451 .init_name = "apb:uart2", 452 .platform_data = &ep93xx_uart_data, 453 }, 454 .res = { 455 .start = EP93XX_UART2_PHYS_BASE, 456 .end = EP93XX_UART2_PHYS_BASE + 0x0fff, 457 .flags = IORESOURCE_MEM, 458 }, 459 .irq = { IRQ_EP93XX_UART2, NO_IRQ }, 460 .periphid = 0x00041010, 461 }; 462 463 static struct amba_device uart3_device = { 464 .dev = { 465 .init_name = "apb:uart3", 466 .platform_data = &ep93xx_uart_data, 467 }, 468 .res = { 469 .start = EP93XX_UART3_PHYS_BASE, 470 .end = EP93XX_UART3_PHYS_BASE + 0x0fff, 471 .flags = IORESOURCE_MEM, 472 }, 473 .irq = { IRQ_EP93XX_UART3, NO_IRQ }, 474 .periphid = 0x00041010, 475 }; 476 477 478 static struct resource ep93xx_rtc_resource[] = { 479 { 480 .start = EP93XX_RTC_PHYS_BASE, 481 .end = EP93XX_RTC_PHYS_BASE + 0x10c - 1, 482 .flags = IORESOURCE_MEM, 483 }, 484 }; 485 486 static struct platform_device ep93xx_rtc_device = { 487 .name = "ep93xx-rtc", 488 .id = -1, 489 .num_resources = ARRAY_SIZE(ep93xx_rtc_resource), 490 .resource = ep93xx_rtc_resource, 491 }; 492 493 494 static struct resource ep93xx_ohci_resources[] = { 495 [0] = { 496 .start = EP93XX_USB_PHYS_BASE, 497 .end = EP93XX_USB_PHYS_BASE + 0x0fff, 498 .flags = IORESOURCE_MEM, 499 }, 500 [1] = { 501 .start = IRQ_EP93XX_USB, 502 .end = IRQ_EP93XX_USB, 503 .flags = IORESOURCE_IRQ, 504 }, 505 }; 506 507 508 static struct platform_device ep93xx_ohci_device = { 509 .name = "ep93xx-ohci", 510 .id = -1, 511 .dev = { 512 .dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask, 513 .coherent_dma_mask = DMA_BIT_MASK(32), 514 }, 515 .num_resources = ARRAY_SIZE(ep93xx_ohci_resources), 516 .resource = ep93xx_ohci_resources, 517 }; 518 519 static struct ep93xx_eth_data ep93xx_eth_data; 520 521 static struct resource ep93xx_eth_resource[] = { 522 { 523 .start = EP93XX_ETHERNET_PHYS_BASE, 524 .end = EP93XX_ETHERNET_PHYS_BASE + 0xffff, 525 .flags = IORESOURCE_MEM, 526 }, { 527 .start = IRQ_EP93XX_ETHERNET, 528 .end = IRQ_EP93XX_ETHERNET, 529 .flags = IORESOURCE_IRQ, 530 } 531 }; 532 533 static struct platform_device ep93xx_eth_device = { 534 .name = "ep93xx-eth", 535 .id = -1, 536 .dev = { 537 .platform_data = &ep93xx_eth_data, 538 }, 539 .num_resources = ARRAY_SIZE(ep93xx_eth_resource), 540 .resource = ep93xx_eth_resource, 541 }; 542 543 void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr) 544 { 545 if (copy_addr) 546 memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6); 547 548 ep93xx_eth_data = *data; 549 platform_device_register(&ep93xx_eth_device); 550 } 551 552 static struct i2c_gpio_platform_data ep93xx_i2c_data = { 553 .sda_pin = EP93XX_GPIO_LINE_EEDAT, 554 .sda_is_open_drain = 0, 555 .scl_pin = EP93XX_GPIO_LINE_EECLK, 556 .scl_is_open_drain = 0, 557 .udelay = 2, 558 }; 559 560 static struct platform_device ep93xx_i2c_device = { 561 .name = "i2c-gpio", 562 .id = 0, 563 .dev.platform_data = &ep93xx_i2c_data, 564 }; 565 566 void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num) 567 { 568 i2c_register_board_info(0, devices, num); 569 platform_device_register(&ep93xx_i2c_device); 570 } 571 572 573 /************************************************************************* 574 * EP93xx LEDs 575 *************************************************************************/ 576 static struct gpio_led ep93xx_led_pins[] = { 577 { 578 .name = "platform:grled", 579 .gpio = EP93XX_GPIO_LINE_GRLED, 580 }, { 581 .name = "platform:rdled", 582 .gpio = EP93XX_GPIO_LINE_RDLED, 583 }, 584 }; 585 586 static struct gpio_led_platform_data ep93xx_led_data = { 587 .num_leds = ARRAY_SIZE(ep93xx_led_pins), 588 .leds = ep93xx_led_pins, 589 }; 590 591 static struct platform_device ep93xx_leds = { 592 .name = "leds-gpio", 593 .id = -1, 594 .dev = { 595 .platform_data = &ep93xx_led_data, 596 }, 597 }; 598 599 600 /************************************************************************* 601 * EP93xx pwm peripheral handling 602 *************************************************************************/ 603 static struct resource ep93xx_pwm0_resource[] = { 604 { 605 .start = EP93XX_PWM_PHYS_BASE, 606 .end = EP93XX_PWM_PHYS_BASE + 0x10 - 1, 607 .flags = IORESOURCE_MEM, 608 }, 609 }; 610 611 static struct platform_device ep93xx_pwm0_device = { 612 .name = "ep93xx-pwm", 613 .id = 0, 614 .num_resources = ARRAY_SIZE(ep93xx_pwm0_resource), 615 .resource = ep93xx_pwm0_resource, 616 }; 617 618 static struct resource ep93xx_pwm1_resource[] = { 619 { 620 .start = EP93XX_PWM_PHYS_BASE + 0x20, 621 .end = EP93XX_PWM_PHYS_BASE + 0x30 - 1, 622 .flags = IORESOURCE_MEM, 623 }, 624 }; 625 626 static struct platform_device ep93xx_pwm1_device = { 627 .name = "ep93xx-pwm", 628 .id = 1, 629 .num_resources = ARRAY_SIZE(ep93xx_pwm1_resource), 630 .resource = ep93xx_pwm1_resource, 631 }; 632 633 void __init ep93xx_register_pwm(int pwm0, int pwm1) 634 { 635 if (pwm0) 636 platform_device_register(&ep93xx_pwm0_device); 637 638 /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */ 639 if (pwm1) 640 platform_device_register(&ep93xx_pwm1_device); 641 } 642 643 int ep93xx_pwm_acquire_gpio(struct platform_device *pdev) 644 { 645 int err; 646 647 if (pdev->id == 0) { 648 err = 0; 649 } else if (pdev->id == 1) { 650 err = gpio_request(EP93XX_GPIO_LINE_EGPIO14, 651 dev_name(&pdev->dev)); 652 if (err) 653 return err; 654 err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0); 655 if (err) 656 goto fail; 657 658 /* PWM 1 output on EGPIO[14] */ 659 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG); 660 } else { 661 err = -ENODEV; 662 } 663 664 return err; 665 666 fail: 667 gpio_free(EP93XX_GPIO_LINE_EGPIO14); 668 return err; 669 } 670 EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio); 671 672 void ep93xx_pwm_release_gpio(struct platform_device *pdev) 673 { 674 if (pdev->id == 1) { 675 gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14); 676 gpio_free(EP93XX_GPIO_LINE_EGPIO14); 677 678 /* EGPIO[14] used for GPIO */ 679 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG); 680 } 681 } 682 EXPORT_SYMBOL(ep93xx_pwm_release_gpio); 683 684 685 extern void ep93xx_gpio_init(void); 686 687 void __init ep93xx_init_devices(void) 688 { 689 /* Disallow access to MaverickCrunch initially */ 690 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA); 691 692 ep93xx_gpio_init(); 693 694 amba_device_register(&uart1_device, &iomem_resource); 695 amba_device_register(&uart2_device, &iomem_resource); 696 amba_device_register(&uart3_device, &iomem_resource); 697 698 platform_device_register(&ep93xx_rtc_device); 699 platform_device_register(&ep93xx_ohci_device); 700 platform_device_register(&ep93xx_leds); 701 } 702