1 /* 2 * arch/arm/mach-ep93xx/core.c 3 * Core routines for Cirrus EP93xx chips. 4 * 5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> 6 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> 7 * 8 * Thanks go to Michael Burian and Ray Lehtiniemi for their key 9 * role in the ep93xx linux community. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/spinlock.h> 20 #include <linux/sched.h> 21 #include <linux/interrupt.h> 22 #include <linux/serial.h> 23 #include <linux/tty.h> 24 #include <linux/bitops.h> 25 #include <linux/serial_8250.h> 26 #include <linux/serial_core.h> 27 #include <linux/device.h> 28 #include <linux/mm.h> 29 #include <linux/time.h> 30 #include <linux/timex.h> 31 #include <linux/delay.h> 32 #include <linux/termios.h> 33 #include <linux/amba/bus.h> 34 #include <linux/amba/serial.h> 35 36 #include <asm/types.h> 37 #include <asm/setup.h> 38 #include <asm/memory.h> 39 #include <asm/hardware.h> 40 #include <asm/irq.h> 41 #include <asm/system.h> 42 #include <asm/tlbflush.h> 43 #include <asm/pgtable.h> 44 #include <asm/io.h> 45 46 #include <asm/mach/map.h> 47 #include <asm/mach/time.h> 48 #include <asm/mach/irq.h> 49 #include <asm/arch/gpio.h> 50 51 #include <asm/hardware/vic.h> 52 53 54 /************************************************************************* 55 * Static I/O mappings that are needed for all EP93xx platforms 56 *************************************************************************/ 57 static struct map_desc ep93xx_io_desc[] __initdata = { 58 { 59 .virtual = EP93XX_AHB_VIRT_BASE, 60 .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE), 61 .length = EP93XX_AHB_SIZE, 62 .type = MT_DEVICE, 63 }, { 64 .virtual = EP93XX_APB_VIRT_BASE, 65 .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE), 66 .length = EP93XX_APB_SIZE, 67 .type = MT_DEVICE, 68 }, 69 }; 70 71 void __init ep93xx_map_io(void) 72 { 73 iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc)); 74 } 75 76 77 /************************************************************************* 78 * Timer handling for EP93xx 79 ************************************************************************* 80 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and 81 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate 82 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, 83 * is free-running, and can't generate interrupts. 84 * 85 * The 508 kHz timers are ideal for use for the timer interrupt, as the 86 * most common values of HZ divide 508 kHz nicely. We pick one of the 16 87 * bit timers (timer 1) since we don't need more than 16 bits of reload 88 * value as long as HZ >= 8. 89 * 90 * The higher clock rate of timer 4 makes it a better choice than the 91 * other timers for use in gettimeoffset(), while the fact that it can't 92 * generate interrupts means we don't have to worry about not being able 93 * to use this timer for something else. We also use timer 4 for keeping 94 * track of lost jiffies. 95 */ 96 static unsigned int last_jiffy_time; 97 98 #define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ) 99 100 static int ep93xx_timer_interrupt(int irq, void *dev_id) 101 { 102 __raw_writel(1, EP93XX_TIMER1_CLEAR); 103 while ((signed long) 104 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time) 105 >= TIMER4_TICKS_PER_JIFFY) { 106 last_jiffy_time += TIMER4_TICKS_PER_JIFFY; 107 timer_tick(); 108 } 109 110 return IRQ_HANDLED; 111 } 112 113 static struct irqaction ep93xx_timer_irq = { 114 .name = "ep93xx timer", 115 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 116 .handler = ep93xx_timer_interrupt, 117 }; 118 119 static void __init ep93xx_timer_init(void) 120 { 121 /* Enable periodic HZ timer. */ 122 __raw_writel(0x48, EP93XX_TIMER1_CONTROL); 123 __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD); 124 __raw_writel(0xc8, EP93XX_TIMER1_CONTROL); 125 126 /* Enable lost jiffy timer. */ 127 __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH); 128 129 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq); 130 } 131 132 static unsigned long ep93xx_gettimeoffset(void) 133 { 134 int offset; 135 136 offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time; 137 138 /* Calculate (1000000 / 983040) * offset. */ 139 return offset + (53 * offset / 3072); 140 } 141 142 struct sys_timer ep93xx_timer = { 143 .init = ep93xx_timer_init, 144 .offset = ep93xx_gettimeoffset, 145 }; 146 147 148 /************************************************************************* 149 * GPIO handling for EP93xx 150 *************************************************************************/ 151 static unsigned char gpio_int_unmasked[3]; 152 static unsigned char gpio_int_enabled[3]; 153 static unsigned char gpio_int_type1[3]; 154 static unsigned char gpio_int_type2[3]; 155 156 /* Port ordering is: A B F */ 157 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c }; 158 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 }; 159 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; 160 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x5c }; 161 162 void ep93xx_gpio_update_int_params(unsigned port) 163 { 164 BUG_ON(port > 2); 165 166 __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port])); 167 168 __raw_writeb(gpio_int_type2[port], 169 EP93XX_GPIO_REG(int_type2_register_offset[port])); 170 171 __raw_writeb(gpio_int_type1[port], 172 EP93XX_GPIO_REG(int_type1_register_offset[port])); 173 174 __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port], 175 EP93XX_GPIO_REG(int_en_register_offset[port])); 176 } 177 178 void ep93xx_gpio_int_mask(unsigned line) 179 { 180 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7)); 181 } 182 183 /************************************************************************* 184 * EP93xx IRQ handling 185 *************************************************************************/ 186 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc) 187 { 188 unsigned char status; 189 int i; 190 191 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS); 192 for (i = 0; i < 8; i++) { 193 if (status & (1 << i)) { 194 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i; 195 desc = irq_desc + gpio_irq; 196 desc_handle_irq(gpio_irq, desc); 197 } 198 } 199 200 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS); 201 for (i = 0; i < 8; i++) { 202 if (status & (1 << i)) { 203 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i; 204 desc = irq_desc + gpio_irq; 205 desc_handle_irq(gpio_irq, desc); 206 } 207 } 208 } 209 210 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc) 211 { 212 /* 213 * map discontiguous hw irq range to continous sw irq range: 214 * 215 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7}) 216 */ 217 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ 218 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx; 219 220 desc_handle_irq(gpio_irq, irq_desc + gpio_irq); 221 } 222 223 static void ep93xx_gpio_irq_ack(unsigned int irq) 224 { 225 int line = irq_to_gpio(irq); 226 int port = line >> 3; 227 int port_mask = 1 << (line & 7); 228 229 if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 230 gpio_int_type2[port] ^= port_mask; /* switch edge direction */ 231 ep93xx_gpio_update_int_params(port); 232 } 233 234 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); 235 } 236 237 static void ep93xx_gpio_irq_mask_ack(unsigned int irq) 238 { 239 int line = irq_to_gpio(irq); 240 int port = line >> 3; 241 int port_mask = 1 << (line & 7); 242 243 if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 244 gpio_int_type2[port] ^= port_mask; /* switch edge direction */ 245 246 gpio_int_unmasked[port] &= ~port_mask; 247 ep93xx_gpio_update_int_params(port); 248 249 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); 250 } 251 252 static void ep93xx_gpio_irq_mask(unsigned int irq) 253 { 254 int line = irq_to_gpio(irq); 255 int port = line >> 3; 256 257 gpio_int_unmasked[port] &= ~(1 << (line & 7)); 258 ep93xx_gpio_update_int_params(port); 259 } 260 261 static void ep93xx_gpio_irq_unmask(unsigned int irq) 262 { 263 int line = irq_to_gpio(irq); 264 int port = line >> 3; 265 266 gpio_int_unmasked[port] |= 1 << (line & 7); 267 ep93xx_gpio_update_int_params(port); 268 } 269 270 271 /* 272 * gpio_int_type1 controls whether the interrupt is level (0) or 273 * edge (1) triggered, while gpio_int_type2 controls whether it 274 * triggers on low/falling (0) or high/rising (1). 275 */ 276 static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type) 277 { 278 struct irq_desc *desc = irq_desc + irq; 279 const int gpio = irq_to_gpio(irq); 280 const int port = gpio >> 3; 281 const int port_mask = 1 << (gpio & 7); 282 283 gpio_direction_input(gpio); 284 285 switch (type) { 286 case IRQ_TYPE_EDGE_RISING: 287 gpio_int_type1[port] |= port_mask; 288 gpio_int_type2[port] |= port_mask; 289 desc->handle_irq = handle_edge_irq; 290 break; 291 case IRQ_TYPE_EDGE_FALLING: 292 gpio_int_type1[port] |= port_mask; 293 gpio_int_type2[port] &= ~port_mask; 294 desc->handle_irq = handle_edge_irq; 295 break; 296 case IRQ_TYPE_LEVEL_HIGH: 297 gpio_int_type1[port] &= ~port_mask; 298 gpio_int_type2[port] |= port_mask; 299 desc->handle_irq = handle_level_irq; 300 break; 301 case IRQ_TYPE_LEVEL_LOW: 302 gpio_int_type1[port] &= ~port_mask; 303 gpio_int_type2[port] &= ~port_mask; 304 desc->handle_irq = handle_level_irq; 305 break; 306 case IRQ_TYPE_EDGE_BOTH: 307 gpio_int_type1[port] |= port_mask; 308 /* set initial polarity based on current input level */ 309 if (gpio_get_value(gpio)) 310 gpio_int_type2[port] &= ~port_mask; /* falling */ 311 else 312 gpio_int_type2[port] |= port_mask; /* rising */ 313 desc->handle_irq = handle_edge_irq; 314 break; 315 default: 316 pr_err("ep93xx: failed to set irq type %d for gpio %d\n", 317 type, gpio); 318 return -EINVAL; 319 } 320 321 gpio_int_enabled[port] |= port_mask; 322 323 desc->status &= ~IRQ_TYPE_SENSE_MASK; 324 desc->status |= type & IRQ_TYPE_SENSE_MASK; 325 326 ep93xx_gpio_update_int_params(port); 327 328 return 0; 329 } 330 331 static struct irq_chip ep93xx_gpio_irq_chip = { 332 .name = "GPIO", 333 .ack = ep93xx_gpio_irq_ack, 334 .mask_ack = ep93xx_gpio_irq_mask_ack, 335 .mask = ep93xx_gpio_irq_mask, 336 .unmask = ep93xx_gpio_irq_unmask, 337 .set_type = ep93xx_gpio_irq_type, 338 }; 339 340 341 void __init ep93xx_init_irq(void) 342 { 343 int gpio_irq; 344 345 vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK); 346 vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK); 347 348 for (gpio_irq = gpio_to_irq(0); 349 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { 350 set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip); 351 set_irq_handler(gpio_irq, handle_level_irq); 352 set_irq_flags(gpio_irq, IRQF_VALID); 353 } 354 355 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); 356 set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler); 357 set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler); 358 set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler); 359 set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler); 360 set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler); 361 set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler); 362 set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler); 363 set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler); 364 } 365 366 367 /************************************************************************* 368 * EP93xx peripheral handling 369 *************************************************************************/ 370 #define EP93XX_UART_MCR_OFFSET (0x0100) 371 372 static void ep93xx_uart_set_mctrl(struct amba_device *dev, 373 void __iomem *base, unsigned int mctrl) 374 { 375 unsigned int mcr; 376 377 mcr = 0; 378 if (!(mctrl & TIOCM_RTS)) 379 mcr |= 2; 380 if (!(mctrl & TIOCM_DTR)) 381 mcr |= 1; 382 383 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); 384 } 385 386 static struct amba_pl010_data ep93xx_uart_data = { 387 .set_mctrl = ep93xx_uart_set_mctrl, 388 }; 389 390 static struct amba_device uart1_device = { 391 .dev = { 392 .bus_id = "apb:uart1", 393 .platform_data = &ep93xx_uart_data, 394 }, 395 .res = { 396 .start = EP93XX_UART1_PHYS_BASE, 397 .end = EP93XX_UART1_PHYS_BASE + 0x0fff, 398 .flags = IORESOURCE_MEM, 399 }, 400 .irq = { IRQ_EP93XX_UART1, NO_IRQ }, 401 .periphid = 0x00041010, 402 }; 403 404 static struct amba_device uart2_device = { 405 .dev = { 406 .bus_id = "apb:uart2", 407 .platform_data = &ep93xx_uart_data, 408 }, 409 .res = { 410 .start = EP93XX_UART2_PHYS_BASE, 411 .end = EP93XX_UART2_PHYS_BASE + 0x0fff, 412 .flags = IORESOURCE_MEM, 413 }, 414 .irq = { IRQ_EP93XX_UART2, NO_IRQ }, 415 .periphid = 0x00041010, 416 }; 417 418 static struct amba_device uart3_device = { 419 .dev = { 420 .bus_id = "apb:uart3", 421 .platform_data = &ep93xx_uart_data, 422 }, 423 .res = { 424 .start = EP93XX_UART3_PHYS_BASE, 425 .end = EP93XX_UART3_PHYS_BASE + 0x0fff, 426 .flags = IORESOURCE_MEM, 427 }, 428 .irq = { IRQ_EP93XX_UART3, NO_IRQ }, 429 .periphid = 0x00041010, 430 }; 431 432 433 static struct platform_device ep93xx_rtc_device = { 434 .name = "ep93xx-rtc", 435 .id = -1, 436 .num_resources = 0, 437 }; 438 439 440 static struct resource ep93xx_ohci_resources[] = { 441 [0] = { 442 .start = EP93XX_USB_PHYS_BASE, 443 .end = EP93XX_USB_PHYS_BASE + 0x0fff, 444 .flags = IORESOURCE_MEM, 445 }, 446 [1] = { 447 .start = IRQ_EP93XX_USB, 448 .end = IRQ_EP93XX_USB, 449 .flags = IORESOURCE_IRQ, 450 }, 451 }; 452 453 static struct platform_device ep93xx_ohci_device = { 454 .name = "ep93xx-ohci", 455 .id = -1, 456 .dev = { 457 .dma_mask = (void *)0xffffffff, 458 .coherent_dma_mask = 0xffffffff, 459 }, 460 .num_resources = ARRAY_SIZE(ep93xx_ohci_resources), 461 .resource = ep93xx_ohci_resources, 462 }; 463 464 extern void ep93xx_gpio_init(void); 465 466 void __init ep93xx_init_devices(void) 467 { 468 unsigned int v; 469 470 /* 471 * Disallow access to MaverickCrunch initially. 472 */ 473 v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG); 474 v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE; 475 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); 476 __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG); 477 478 ep93xx_gpio_init(); 479 480 amba_device_register(&uart1_device, &iomem_resource); 481 amba_device_register(&uart2_device, &iomem_resource); 482 amba_device_register(&uart3_device, &iomem_resource); 483 484 platform_device_register(&ep93xx_rtc_device); 485 platform_device_register(&ep93xx_ohci_device); 486 } 487