1 /* 2 * arch/arm/mach-ep93xx/core.c 3 * Core routines for Cirrus EP93xx chips. 4 * 5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> 6 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> 7 * 8 * Thanks go to Michael Burian and Ray Lehtiniemi for their key 9 * role in the ep93xx linux community. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 */ 16 17 #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt 18 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/interrupt.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/timex.h> 25 #include <linux/irq.h> 26 #include <linux/io.h> 27 #include <linux/gpio.h> 28 #include <linux/leds.h> 29 #include <linux/termios.h> 30 #include <linux/amba/bus.h> 31 #include <linux/amba/serial.h> 32 #include <linux/mtd/physmap.h> 33 #include <linux/i2c.h> 34 #include <linux/i2c-gpio.h> 35 #include <linux/spi/spi.h> 36 #include <linux/export.h> 37 38 #include <mach/hardware.h> 39 #include <mach/fb.h> 40 #include <mach/ep93xx_keypad.h> 41 #include <mach/ep93xx_spi.h> 42 #include <mach/gpio-ep93xx.h> 43 44 #include <asm/mach/map.h> 45 #include <asm/mach/time.h> 46 47 #include <asm/hardware/vic.h> 48 49 #include "soc.h" 50 51 /************************************************************************* 52 * Static I/O mappings that are needed for all EP93xx platforms 53 *************************************************************************/ 54 static struct map_desc ep93xx_io_desc[] __initdata = { 55 { 56 .virtual = EP93XX_AHB_VIRT_BASE, 57 .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE), 58 .length = EP93XX_AHB_SIZE, 59 .type = MT_DEVICE, 60 }, { 61 .virtual = EP93XX_APB_VIRT_BASE, 62 .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE), 63 .length = EP93XX_APB_SIZE, 64 .type = MT_DEVICE, 65 }, 66 }; 67 68 void __init ep93xx_map_io(void) 69 { 70 iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc)); 71 } 72 73 74 /************************************************************************* 75 * Timer handling for EP93xx 76 ************************************************************************* 77 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and 78 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate 79 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, 80 * is free-running, and can't generate interrupts. 81 * 82 * The 508 kHz timers are ideal for use for the timer interrupt, as the 83 * most common values of HZ divide 508 kHz nicely. We pick one of the 16 84 * bit timers (timer 1) since we don't need more than 16 bits of reload 85 * value as long as HZ >= 8. 86 * 87 * The higher clock rate of timer 4 makes it a better choice than the 88 * other timers for use in gettimeoffset(), while the fact that it can't 89 * generate interrupts means we don't have to worry about not being able 90 * to use this timer for something else. We also use timer 4 for keeping 91 * track of lost jiffies. 92 */ 93 #define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) 94 #define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) 95 #define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) 96 #define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08) 97 #define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7) 98 #define EP93XX_TIMER123_CONTROL_MODE (1 << 6) 99 #define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3) 100 #define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c) 101 #define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20) 102 #define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24) 103 #define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28) 104 #define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c) 105 #define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60) 106 #define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64) 107 #define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8) 108 #define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80) 109 #define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84) 110 #define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) 111 #define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) 112 113 #define EP93XX_TIMER123_CLOCK 508469 114 #define EP93XX_TIMER4_CLOCK 983040 115 116 #define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1) 117 #define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ) 118 119 static unsigned int last_jiffy_time; 120 121 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) 122 { 123 /* Writing any value clears the timer interrupt */ 124 __raw_writel(1, EP93XX_TIMER1_CLEAR); 125 126 /* Recover lost jiffies */ 127 while ((signed long) 128 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time) 129 >= TIMER4_TICKS_PER_JIFFY) { 130 last_jiffy_time += TIMER4_TICKS_PER_JIFFY; 131 timer_tick(); 132 } 133 134 return IRQ_HANDLED; 135 } 136 137 static struct irqaction ep93xx_timer_irq = { 138 .name = "ep93xx timer", 139 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 140 .handler = ep93xx_timer_interrupt, 141 }; 142 143 static void __init ep93xx_timer_init(void) 144 { 145 u32 tmode = EP93XX_TIMER123_CONTROL_MODE | 146 EP93XX_TIMER123_CONTROL_CLKSEL; 147 148 /* Enable periodic HZ timer. */ 149 __raw_writel(tmode, EP93XX_TIMER1_CONTROL); 150 __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD); 151 __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, 152 EP93XX_TIMER1_CONTROL); 153 154 /* Enable lost jiffy timer. */ 155 __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, 156 EP93XX_TIMER4_VALUE_HIGH); 157 158 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq); 159 } 160 161 static unsigned long ep93xx_gettimeoffset(void) 162 { 163 int offset; 164 165 offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time; 166 167 /* Calculate (1000000 / 983040) * offset. */ 168 return offset + (53 * offset / 3072); 169 } 170 171 struct sys_timer ep93xx_timer = { 172 .init = ep93xx_timer_init, 173 .offset = ep93xx_gettimeoffset, 174 }; 175 176 177 /************************************************************************* 178 * EP93xx IRQ handling 179 *************************************************************************/ 180 void __init ep93xx_init_irq(void) 181 { 182 vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); 183 vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); 184 } 185 186 187 /************************************************************************* 188 * EP93xx System Controller Software Locked register handling 189 *************************************************************************/ 190 191 /* 192 * syscon_swlock prevents anything else from writing to the syscon 193 * block while a software locked register is being written. 194 */ 195 static DEFINE_SPINLOCK(syscon_swlock); 196 197 void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg) 198 { 199 unsigned long flags; 200 201 spin_lock_irqsave(&syscon_swlock, flags); 202 203 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); 204 __raw_writel(val, reg); 205 206 spin_unlock_irqrestore(&syscon_swlock, flags); 207 } 208 209 void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits) 210 { 211 unsigned long flags; 212 unsigned int val; 213 214 spin_lock_irqsave(&syscon_swlock, flags); 215 216 val = __raw_readl(EP93XX_SYSCON_DEVCFG); 217 val &= ~clear_bits; 218 val |= set_bits; 219 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); 220 __raw_writel(val, EP93XX_SYSCON_DEVCFG); 221 222 spin_unlock_irqrestore(&syscon_swlock, flags); 223 } 224 225 /** 226 * ep93xx_chip_revision() - returns the EP93xx chip revision 227 * 228 * See <mach/platform.h> for more information. 229 */ 230 unsigned int ep93xx_chip_revision(void) 231 { 232 unsigned int v; 233 234 v = __raw_readl(EP93XX_SYSCON_SYSCFG); 235 v &= EP93XX_SYSCON_SYSCFG_REV_MASK; 236 v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT; 237 return v; 238 } 239 240 /************************************************************************* 241 * EP93xx GPIO 242 *************************************************************************/ 243 static struct resource ep93xx_gpio_resource[] = { 244 DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc), 245 }; 246 247 static struct platform_device ep93xx_gpio_device = { 248 .name = "gpio-ep93xx", 249 .id = -1, 250 .num_resources = ARRAY_SIZE(ep93xx_gpio_resource), 251 .resource = ep93xx_gpio_resource, 252 }; 253 254 /************************************************************************* 255 * EP93xx peripheral handling 256 *************************************************************************/ 257 #define EP93XX_UART_MCR_OFFSET (0x0100) 258 259 static void ep93xx_uart_set_mctrl(struct amba_device *dev, 260 void __iomem *base, unsigned int mctrl) 261 { 262 unsigned int mcr; 263 264 mcr = 0; 265 if (mctrl & TIOCM_RTS) 266 mcr |= 2; 267 if (mctrl & TIOCM_DTR) 268 mcr |= 1; 269 270 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); 271 } 272 273 static struct amba_pl010_data ep93xx_uart_data = { 274 .set_mctrl = ep93xx_uart_set_mctrl, 275 }; 276 277 static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_BASE, 278 { IRQ_EP93XX_UART1 }, &ep93xx_uart_data); 279 280 static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_BASE, 281 { IRQ_EP93XX_UART2 }, &ep93xx_uart_data); 282 283 static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE, 284 { IRQ_EP93XX_UART3 }, &ep93xx_uart_data); 285 286 static struct resource ep93xx_rtc_resource[] = { 287 DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c), 288 }; 289 290 static struct platform_device ep93xx_rtc_device = { 291 .name = "ep93xx-rtc", 292 .id = -1, 293 .num_resources = ARRAY_SIZE(ep93xx_rtc_resource), 294 .resource = ep93xx_rtc_resource, 295 }; 296 297 298 static struct resource ep93xx_ohci_resources[] = { 299 DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000), 300 DEFINE_RES_IRQ(IRQ_EP93XX_USB), 301 }; 302 303 304 static struct platform_device ep93xx_ohci_device = { 305 .name = "ep93xx-ohci", 306 .id = -1, 307 .dev = { 308 .dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask, 309 .coherent_dma_mask = DMA_BIT_MASK(32), 310 }, 311 .num_resources = ARRAY_SIZE(ep93xx_ohci_resources), 312 .resource = ep93xx_ohci_resources, 313 }; 314 315 316 /************************************************************************* 317 * EP93xx physmap'ed flash 318 *************************************************************************/ 319 static struct physmap_flash_data ep93xx_flash_data; 320 321 static struct resource ep93xx_flash_resource = { 322 .flags = IORESOURCE_MEM, 323 }; 324 325 static struct platform_device ep93xx_flash = { 326 .name = "physmap-flash", 327 .id = 0, 328 .dev = { 329 .platform_data = &ep93xx_flash_data, 330 }, 331 .num_resources = 1, 332 .resource = &ep93xx_flash_resource, 333 }; 334 335 /** 336 * ep93xx_register_flash() - Register the external flash device. 337 * @width: bank width in octets 338 * @start: resource start address 339 * @size: resource size 340 */ 341 void __init ep93xx_register_flash(unsigned int width, 342 resource_size_t start, resource_size_t size) 343 { 344 ep93xx_flash_data.width = width; 345 346 ep93xx_flash_resource.start = start; 347 ep93xx_flash_resource.end = start + size - 1; 348 349 platform_device_register(&ep93xx_flash); 350 } 351 352 353 /************************************************************************* 354 * EP93xx ethernet peripheral handling 355 *************************************************************************/ 356 static struct ep93xx_eth_data ep93xx_eth_data; 357 358 static struct resource ep93xx_eth_resource[] = { 359 DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000), 360 DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET), 361 }; 362 363 static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32); 364 365 static struct platform_device ep93xx_eth_device = { 366 .name = "ep93xx-eth", 367 .id = -1, 368 .dev = { 369 .platform_data = &ep93xx_eth_data, 370 .coherent_dma_mask = DMA_BIT_MASK(32), 371 .dma_mask = &ep93xx_eth_dma_mask, 372 }, 373 .num_resources = ARRAY_SIZE(ep93xx_eth_resource), 374 .resource = ep93xx_eth_resource, 375 }; 376 377 /** 378 * ep93xx_register_eth - Register the built-in ethernet platform device. 379 * @data: platform specific ethernet configuration (__initdata) 380 * @copy_addr: flag indicating that the MAC address should be copied 381 * from the IndAd registers (as programmed by the bootloader) 382 */ 383 void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr) 384 { 385 if (copy_addr) 386 memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6); 387 388 ep93xx_eth_data = *data; 389 platform_device_register(&ep93xx_eth_device); 390 } 391 392 393 /************************************************************************* 394 * EP93xx i2c peripheral handling 395 *************************************************************************/ 396 static struct i2c_gpio_platform_data ep93xx_i2c_data; 397 398 static struct platform_device ep93xx_i2c_device = { 399 .name = "i2c-gpio", 400 .id = 0, 401 .dev = { 402 .platform_data = &ep93xx_i2c_data, 403 }, 404 }; 405 406 /** 407 * ep93xx_register_i2c - Register the i2c platform device. 408 * @data: platform specific i2c-gpio configuration (__initdata) 409 * @devices: platform specific i2c bus device information (__initdata) 410 * @num: the number of devices on the i2c bus 411 */ 412 void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data, 413 struct i2c_board_info *devices, int num) 414 { 415 /* 416 * Set the EEPROM interface pin drive type control. 417 * Defines the driver type for the EECLK and EEDAT pins as either 418 * open drain, which will require an external pull-up, or a normal 419 * CMOS driver. 420 */ 421 if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT) 422 pr_warning("sda != EEDAT, open drain has no effect\n"); 423 if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK) 424 pr_warning("scl != EECLK, open drain has no effect\n"); 425 426 __raw_writel((data->sda_is_open_drain << 1) | 427 (data->scl_is_open_drain << 0), 428 EP93XX_GPIO_EEDRIVE); 429 430 ep93xx_i2c_data = *data; 431 i2c_register_board_info(0, devices, num); 432 platform_device_register(&ep93xx_i2c_device); 433 } 434 435 /************************************************************************* 436 * EP93xx SPI peripheral handling 437 *************************************************************************/ 438 static struct ep93xx_spi_info ep93xx_spi_master_data; 439 440 static struct resource ep93xx_spi_resources[] = { 441 DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18), 442 DEFINE_RES_IRQ(IRQ_EP93XX_SSP), 443 }; 444 445 static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32); 446 447 static struct platform_device ep93xx_spi_device = { 448 .name = "ep93xx-spi", 449 .id = 0, 450 .dev = { 451 .platform_data = &ep93xx_spi_master_data, 452 .coherent_dma_mask = DMA_BIT_MASK(32), 453 .dma_mask = &ep93xx_spi_dma_mask, 454 }, 455 .num_resources = ARRAY_SIZE(ep93xx_spi_resources), 456 .resource = ep93xx_spi_resources, 457 }; 458 459 /** 460 * ep93xx_register_spi() - registers spi platform device 461 * @info: ep93xx board specific spi master info (__initdata) 462 * @devices: SPI devices to register (__initdata) 463 * @num: number of SPI devices to register 464 * 465 * This function registers platform device for the EP93xx SPI controller and 466 * also makes sure that SPI pins are muxed so that I2S is not using those pins. 467 */ 468 void __init ep93xx_register_spi(struct ep93xx_spi_info *info, 469 struct spi_board_info *devices, int num) 470 { 471 /* 472 * When SPI is used, we need to make sure that I2S is muxed off from 473 * SPI pins. 474 */ 475 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP); 476 477 ep93xx_spi_master_data = *info; 478 spi_register_board_info(devices, num); 479 platform_device_register(&ep93xx_spi_device); 480 } 481 482 /************************************************************************* 483 * EP93xx LEDs 484 *************************************************************************/ 485 static const struct gpio_led ep93xx_led_pins[] __initconst = { 486 { 487 .name = "platform:grled", 488 .gpio = EP93XX_GPIO_LINE_GRLED, 489 }, { 490 .name = "platform:rdled", 491 .gpio = EP93XX_GPIO_LINE_RDLED, 492 }, 493 }; 494 495 static const struct gpio_led_platform_data ep93xx_led_data __initconst = { 496 .num_leds = ARRAY_SIZE(ep93xx_led_pins), 497 .leds = ep93xx_led_pins, 498 }; 499 500 /************************************************************************* 501 * EP93xx pwm peripheral handling 502 *************************************************************************/ 503 static struct resource ep93xx_pwm0_resource[] = { 504 DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10), 505 }; 506 507 static struct platform_device ep93xx_pwm0_device = { 508 .name = "ep93xx-pwm", 509 .id = 0, 510 .num_resources = ARRAY_SIZE(ep93xx_pwm0_resource), 511 .resource = ep93xx_pwm0_resource, 512 }; 513 514 static struct resource ep93xx_pwm1_resource[] = { 515 DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10), 516 }; 517 518 static struct platform_device ep93xx_pwm1_device = { 519 .name = "ep93xx-pwm", 520 .id = 1, 521 .num_resources = ARRAY_SIZE(ep93xx_pwm1_resource), 522 .resource = ep93xx_pwm1_resource, 523 }; 524 525 void __init ep93xx_register_pwm(int pwm0, int pwm1) 526 { 527 if (pwm0) 528 platform_device_register(&ep93xx_pwm0_device); 529 530 /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */ 531 if (pwm1) 532 platform_device_register(&ep93xx_pwm1_device); 533 } 534 535 int ep93xx_pwm_acquire_gpio(struct platform_device *pdev) 536 { 537 int err; 538 539 if (pdev->id == 0) { 540 err = 0; 541 } else if (pdev->id == 1) { 542 err = gpio_request(EP93XX_GPIO_LINE_EGPIO14, 543 dev_name(&pdev->dev)); 544 if (err) 545 return err; 546 err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0); 547 if (err) 548 goto fail; 549 550 /* PWM 1 output on EGPIO[14] */ 551 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG); 552 } else { 553 err = -ENODEV; 554 } 555 556 return err; 557 558 fail: 559 gpio_free(EP93XX_GPIO_LINE_EGPIO14); 560 return err; 561 } 562 EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio); 563 564 void ep93xx_pwm_release_gpio(struct platform_device *pdev) 565 { 566 if (pdev->id == 1) { 567 gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14); 568 gpio_free(EP93XX_GPIO_LINE_EGPIO14); 569 570 /* EGPIO[14] used for GPIO */ 571 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG); 572 } 573 } 574 EXPORT_SYMBOL(ep93xx_pwm_release_gpio); 575 576 577 /************************************************************************* 578 * EP93xx video peripheral handling 579 *************************************************************************/ 580 static struct ep93xxfb_mach_info ep93xxfb_data; 581 582 static struct resource ep93xx_fb_resource[] = { 583 DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800), 584 }; 585 586 static struct platform_device ep93xx_fb_device = { 587 .name = "ep93xx-fb", 588 .id = -1, 589 .dev = { 590 .platform_data = &ep93xxfb_data, 591 .coherent_dma_mask = DMA_BIT_MASK(32), 592 .dma_mask = &ep93xx_fb_device.dev.coherent_dma_mask, 593 }, 594 .num_resources = ARRAY_SIZE(ep93xx_fb_resource), 595 .resource = ep93xx_fb_resource, 596 }; 597 598 /* The backlight use a single register in the framebuffer's register space */ 599 #define EP93XX_RASTER_REG_BRIGHTNESS 0x20 600 601 static struct resource ep93xx_bl_resources[] = { 602 DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE + 603 EP93XX_RASTER_REG_BRIGHTNESS, 0x04), 604 }; 605 606 static struct platform_device ep93xx_bl_device = { 607 .name = "ep93xx-bl", 608 .id = -1, 609 .num_resources = ARRAY_SIZE(ep93xx_bl_resources), 610 .resource = ep93xx_bl_resources, 611 }; 612 613 /** 614 * ep93xx_register_fb - Register the framebuffer platform device. 615 * @data: platform specific framebuffer configuration (__initdata) 616 */ 617 void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data) 618 { 619 ep93xxfb_data = *data; 620 platform_device_register(&ep93xx_fb_device); 621 platform_device_register(&ep93xx_bl_device); 622 } 623 624 625 /************************************************************************* 626 * EP93xx matrix keypad peripheral handling 627 *************************************************************************/ 628 static struct ep93xx_keypad_platform_data ep93xx_keypad_data; 629 630 static struct resource ep93xx_keypad_resource[] = { 631 DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c), 632 DEFINE_RES_IRQ(IRQ_EP93XX_KEY), 633 }; 634 635 static struct platform_device ep93xx_keypad_device = { 636 .name = "ep93xx-keypad", 637 .id = -1, 638 .dev = { 639 .platform_data = &ep93xx_keypad_data, 640 }, 641 .num_resources = ARRAY_SIZE(ep93xx_keypad_resource), 642 .resource = ep93xx_keypad_resource, 643 }; 644 645 /** 646 * ep93xx_register_keypad - Register the keypad platform device. 647 * @data: platform specific keypad configuration (__initdata) 648 */ 649 void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data) 650 { 651 ep93xx_keypad_data = *data; 652 platform_device_register(&ep93xx_keypad_device); 653 } 654 655 int ep93xx_keypad_acquire_gpio(struct platform_device *pdev) 656 { 657 int err; 658 int i; 659 660 for (i = 0; i < 8; i++) { 661 err = gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev)); 662 if (err) 663 goto fail_gpio_c; 664 err = gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev)); 665 if (err) 666 goto fail_gpio_d; 667 } 668 669 /* Enable the keypad controller; GPIO ports C and D used for keypad */ 670 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS | 671 EP93XX_SYSCON_DEVCFG_GONK); 672 673 return 0; 674 675 fail_gpio_d: 676 gpio_free(EP93XX_GPIO_LINE_C(i)); 677 fail_gpio_c: 678 for (--i; i >= 0; --i) { 679 gpio_free(EP93XX_GPIO_LINE_C(i)); 680 gpio_free(EP93XX_GPIO_LINE_D(i)); 681 } 682 return err; 683 } 684 EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio); 685 686 void ep93xx_keypad_release_gpio(struct platform_device *pdev) 687 { 688 int i; 689 690 for (i = 0; i < 8; i++) { 691 gpio_free(EP93XX_GPIO_LINE_C(i)); 692 gpio_free(EP93XX_GPIO_LINE_D(i)); 693 } 694 695 /* Disable the keypad controller; GPIO ports C and D used for GPIO */ 696 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS | 697 EP93XX_SYSCON_DEVCFG_GONK); 698 } 699 EXPORT_SYMBOL(ep93xx_keypad_release_gpio); 700 701 /************************************************************************* 702 * EP93xx I2S audio peripheral handling 703 *************************************************************************/ 704 static struct resource ep93xx_i2s_resource[] = { 705 DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100), 706 }; 707 708 static struct platform_device ep93xx_i2s_device = { 709 .name = "ep93xx-i2s", 710 .id = -1, 711 .num_resources = ARRAY_SIZE(ep93xx_i2s_resource), 712 .resource = ep93xx_i2s_resource, 713 }; 714 715 static struct platform_device ep93xx_pcm_device = { 716 .name = "ep93xx-pcm-audio", 717 .id = -1, 718 }; 719 720 void __init ep93xx_register_i2s(void) 721 { 722 platform_device_register(&ep93xx_i2s_device); 723 platform_device_register(&ep93xx_pcm_device); 724 } 725 726 #define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \ 727 EP93XX_SYSCON_DEVCFG_I2SONAC97) 728 729 #define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \ 730 EP93XX_SYSCON_I2SCLKDIV_SPOL) 731 732 int ep93xx_i2s_acquire(void) 733 { 734 unsigned val; 735 736 ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97, 737 EP93XX_SYSCON_DEVCFG_I2S_MASK); 738 739 /* 740 * This is potentially racy with the clock api for i2s_mclk, sclk and 741 * lrclk. Since the i2s driver is the only user of those clocks we 742 * rely on it to prevent parallel use of this function and the 743 * clock api for the i2s clocks. 744 */ 745 val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV); 746 val &= ~EP93XX_I2SCLKDIV_MASK; 747 val |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL; 748 ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV); 749 750 return 0; 751 } 752 EXPORT_SYMBOL(ep93xx_i2s_acquire); 753 754 void ep93xx_i2s_release(void) 755 { 756 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK); 757 } 758 EXPORT_SYMBOL(ep93xx_i2s_release); 759 760 /************************************************************************* 761 * EP93xx AC97 audio peripheral handling 762 *************************************************************************/ 763 static struct resource ep93xx_ac97_resources[] = { 764 DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac), 765 DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR), 766 }; 767 768 static struct platform_device ep93xx_ac97_device = { 769 .name = "ep93xx-ac97", 770 .id = -1, 771 .num_resources = ARRAY_SIZE(ep93xx_ac97_resources), 772 .resource = ep93xx_ac97_resources, 773 }; 774 775 void __init ep93xx_register_ac97(void) 776 { 777 /* 778 * Make sure that the AC97 pins are not used by I2S. 779 */ 780 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97); 781 782 platform_device_register(&ep93xx_ac97_device); 783 platform_device_register(&ep93xx_pcm_device); 784 } 785 786 /************************************************************************* 787 * EP93xx Watchdog 788 *************************************************************************/ 789 static struct resource ep93xx_wdt_resources[] = { 790 DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08), 791 }; 792 793 static struct platform_device ep93xx_wdt_device = { 794 .name = "ep93xx-wdt", 795 .id = -1, 796 .num_resources = ARRAY_SIZE(ep93xx_wdt_resources), 797 .resource = ep93xx_wdt_resources, 798 }; 799 800 /************************************************************************* 801 * EP93xx IDE 802 *************************************************************************/ 803 static struct resource ep93xx_ide_resources[] = { 804 DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38), 805 DEFINE_RES_IRQ(IRQ_EP93XX_EXT3), 806 }; 807 808 static struct platform_device ep93xx_ide_device = { 809 .name = "ep93xx-ide", 810 .id = -1, 811 .dev = { 812 .dma_mask = &ep93xx_ide_device.dev.coherent_dma_mask, 813 .coherent_dma_mask = DMA_BIT_MASK(32), 814 }, 815 .num_resources = ARRAY_SIZE(ep93xx_ide_resources), 816 .resource = ep93xx_ide_resources, 817 }; 818 819 void __init ep93xx_register_ide(void) 820 { 821 platform_device_register(&ep93xx_ide_device); 822 } 823 824 int ep93xx_ide_acquire_gpio(struct platform_device *pdev) 825 { 826 int err; 827 int i; 828 829 err = gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev)); 830 if (err) 831 return err; 832 err = gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev)); 833 if (err) 834 goto fail_egpio15; 835 for (i = 2; i < 8; i++) { 836 err = gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev)); 837 if (err) 838 goto fail_gpio_e; 839 } 840 for (i = 4; i < 8; i++) { 841 err = gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev)); 842 if (err) 843 goto fail_gpio_g; 844 } 845 for (i = 0; i < 8; i++) { 846 err = gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev)); 847 if (err) 848 goto fail_gpio_h; 849 } 850 851 /* GPIO ports E[7:2], G[7:4] and H used by IDE */ 852 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE | 853 EP93XX_SYSCON_DEVCFG_GONIDE | 854 EP93XX_SYSCON_DEVCFG_HONIDE); 855 return 0; 856 857 fail_gpio_h: 858 for (--i; i >= 0; --i) 859 gpio_free(EP93XX_GPIO_LINE_H(i)); 860 i = 8; 861 fail_gpio_g: 862 for (--i; i >= 4; --i) 863 gpio_free(EP93XX_GPIO_LINE_G(i)); 864 i = 8; 865 fail_gpio_e: 866 for (--i; i >= 2; --i) 867 gpio_free(EP93XX_GPIO_LINE_E(i)); 868 gpio_free(EP93XX_GPIO_LINE_EGPIO15); 869 fail_egpio15: 870 gpio_free(EP93XX_GPIO_LINE_EGPIO2); 871 return err; 872 } 873 EXPORT_SYMBOL(ep93xx_ide_acquire_gpio); 874 875 void ep93xx_ide_release_gpio(struct platform_device *pdev) 876 { 877 int i; 878 879 for (i = 2; i < 8; i++) 880 gpio_free(EP93XX_GPIO_LINE_E(i)); 881 for (i = 4; i < 8; i++) 882 gpio_free(EP93XX_GPIO_LINE_G(i)); 883 for (i = 0; i < 8; i++) 884 gpio_free(EP93XX_GPIO_LINE_H(i)); 885 gpio_free(EP93XX_GPIO_LINE_EGPIO15); 886 gpio_free(EP93XX_GPIO_LINE_EGPIO2); 887 888 889 /* GPIO ports E[7:2], G[7:4] and H used by GPIO */ 890 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE | 891 EP93XX_SYSCON_DEVCFG_GONIDE | 892 EP93XX_SYSCON_DEVCFG_HONIDE); 893 } 894 EXPORT_SYMBOL(ep93xx_ide_release_gpio); 895 896 void __init ep93xx_init_devices(void) 897 { 898 /* Disallow access to MaverickCrunch initially */ 899 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA); 900 901 /* Default all ports to GPIO */ 902 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS | 903 EP93XX_SYSCON_DEVCFG_GONK | 904 EP93XX_SYSCON_DEVCFG_EONIDE | 905 EP93XX_SYSCON_DEVCFG_GONIDE | 906 EP93XX_SYSCON_DEVCFG_HONIDE); 907 908 /* Get the GPIO working early, other devices need it */ 909 platform_device_register(&ep93xx_gpio_device); 910 911 amba_device_register(&uart1_device, &iomem_resource); 912 amba_device_register(&uart2_device, &iomem_resource); 913 amba_device_register(&uart3_device, &iomem_resource); 914 915 platform_device_register(&ep93xx_rtc_device); 916 platform_device_register(&ep93xx_ohci_device); 917 platform_device_register(&ep93xx_wdt_device); 918 919 gpio_led_register_device(-1, &ep93xx_led_data); 920 } 921 922 void ep93xx_restart(char mode, const char *cmd) 923 { 924 /* 925 * Set then clear the SWRST bit to initiate a software reset 926 */ 927 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST); 928 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST); 929 930 while (1) 931 ; 932 } 933 934 void __init ep93xx_init_late(void) 935 { 936 crunch_init(); 937 } 938