1 /* 2 * arch/arm/mach-ep93xx/core.c 3 * Core routines for Cirrus EP93xx chips. 4 * 5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> 6 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> 7 * 8 * Thanks go to Michael Burian and Ray Lehtiniemi for their key 9 * role in the ep93xx linux community. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 */ 16 17 #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt 18 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/interrupt.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/timex.h> 25 #include <linux/irq.h> 26 #include <linux/io.h> 27 #include <linux/gpio.h> 28 #include <linux/leds.h> 29 #include <linux/termios.h> 30 #include <linux/amba/bus.h> 31 #include <linux/amba/serial.h> 32 #include <linux/mtd/physmap.h> 33 #include <linux/i2c.h> 34 #include <linux/i2c-gpio.h> 35 #include <linux/spi/spi.h> 36 #include <linux/export.h> 37 #include <linux/irqchip/arm-vic.h> 38 #include <linux/reboot.h> 39 40 #include <mach/hardware.h> 41 #include <linux/platform_data/video-ep93xx.h> 42 #include <linux/platform_data/keypad-ep93xx.h> 43 #include <linux/platform_data/spi-ep93xx.h> 44 #include <mach/gpio-ep93xx.h> 45 46 #include <asm/mach/map.h> 47 #include <asm/mach/time.h> 48 49 #include "soc.h" 50 51 /************************************************************************* 52 * Static I/O mappings that are needed for all EP93xx platforms 53 *************************************************************************/ 54 static struct map_desc ep93xx_io_desc[] __initdata = { 55 { 56 .virtual = EP93XX_AHB_VIRT_BASE, 57 .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE), 58 .length = EP93XX_AHB_SIZE, 59 .type = MT_DEVICE, 60 }, { 61 .virtual = EP93XX_APB_VIRT_BASE, 62 .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE), 63 .length = EP93XX_APB_SIZE, 64 .type = MT_DEVICE, 65 }, 66 }; 67 68 void __init ep93xx_map_io(void) 69 { 70 iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc)); 71 } 72 73 74 /************************************************************************* 75 * Timer handling for EP93xx 76 ************************************************************************* 77 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and 78 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate 79 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, 80 * is free-running, and can't generate interrupts. 81 * 82 * The 508 kHz timers are ideal for use for the timer interrupt, as the 83 * most common values of HZ divide 508 kHz nicely. We pick one of the 16 84 * bit timers (timer 1) since we don't need more than 16 bits of reload 85 * value as long as HZ >= 8. 86 * 87 * The higher clock rate of timer 4 makes it a better choice than the 88 * other timers for use in gettimeoffset(), while the fact that it can't 89 * generate interrupts means we don't have to worry about not being able 90 * to use this timer for something else. We also use timer 4 for keeping 91 * track of lost jiffies. 92 */ 93 #define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) 94 #define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) 95 #define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) 96 #define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08) 97 #define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7) 98 #define EP93XX_TIMER123_CONTROL_MODE (1 << 6) 99 #define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3) 100 #define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c) 101 #define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20) 102 #define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24) 103 #define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28) 104 #define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c) 105 #define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60) 106 #define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64) 107 #define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8) 108 #define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80) 109 #define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84) 110 #define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) 111 #define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) 112 113 #define EP93XX_TIMER123_CLOCK 508469 114 #define EP93XX_TIMER4_CLOCK 983040 115 116 #define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1) 117 #define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ) 118 119 static unsigned int last_jiffy_time; 120 121 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) 122 { 123 /* Writing any value clears the timer interrupt */ 124 __raw_writel(1, EP93XX_TIMER1_CLEAR); 125 126 /* Recover lost jiffies */ 127 while ((signed long) 128 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time) 129 >= TIMER4_TICKS_PER_JIFFY) { 130 last_jiffy_time += TIMER4_TICKS_PER_JIFFY; 131 timer_tick(); 132 } 133 134 return IRQ_HANDLED; 135 } 136 137 static struct irqaction ep93xx_timer_irq = { 138 .name = "ep93xx timer", 139 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 140 .handler = ep93xx_timer_interrupt, 141 }; 142 143 static u32 ep93xx_gettimeoffset(void) 144 { 145 int offset; 146 147 offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time; 148 149 /* 150 * Timer 4 is based on a 983.04 kHz reference clock, 151 * so dividing by 983040 gives the fraction of a second, 152 * so dividing by 0.983040 converts to uS. 153 * Refactor the calculation to avoid overflow. 154 * Finally, multiply by 1000 to give nS. 155 */ 156 return (offset + (53 * offset / 3072)) * 1000; 157 } 158 159 void __init ep93xx_timer_init(void) 160 { 161 u32 tmode = EP93XX_TIMER123_CONTROL_MODE | 162 EP93XX_TIMER123_CONTROL_CLKSEL; 163 164 arch_gettimeoffset = ep93xx_gettimeoffset; 165 166 /* Enable periodic HZ timer. */ 167 __raw_writel(tmode, EP93XX_TIMER1_CONTROL); 168 __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD); 169 __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, 170 EP93XX_TIMER1_CONTROL); 171 172 /* Enable lost jiffy timer. */ 173 __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, 174 EP93XX_TIMER4_VALUE_HIGH); 175 176 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq); 177 } 178 179 180 /************************************************************************* 181 * EP93xx IRQ handling 182 *************************************************************************/ 183 void __init ep93xx_init_irq(void) 184 { 185 vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); 186 vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); 187 } 188 189 190 /************************************************************************* 191 * EP93xx System Controller Software Locked register handling 192 *************************************************************************/ 193 194 /* 195 * syscon_swlock prevents anything else from writing to the syscon 196 * block while a software locked register is being written. 197 */ 198 static DEFINE_SPINLOCK(syscon_swlock); 199 200 void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg) 201 { 202 unsigned long flags; 203 204 spin_lock_irqsave(&syscon_swlock, flags); 205 206 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); 207 __raw_writel(val, reg); 208 209 spin_unlock_irqrestore(&syscon_swlock, flags); 210 } 211 212 void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits) 213 { 214 unsigned long flags; 215 unsigned int val; 216 217 spin_lock_irqsave(&syscon_swlock, flags); 218 219 val = __raw_readl(EP93XX_SYSCON_DEVCFG); 220 val &= ~clear_bits; 221 val |= set_bits; 222 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); 223 __raw_writel(val, EP93XX_SYSCON_DEVCFG); 224 225 spin_unlock_irqrestore(&syscon_swlock, flags); 226 } 227 228 /** 229 * ep93xx_chip_revision() - returns the EP93xx chip revision 230 * 231 * See <mach/platform.h> for more information. 232 */ 233 unsigned int ep93xx_chip_revision(void) 234 { 235 unsigned int v; 236 237 v = __raw_readl(EP93XX_SYSCON_SYSCFG); 238 v &= EP93XX_SYSCON_SYSCFG_REV_MASK; 239 v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT; 240 return v; 241 } 242 243 /************************************************************************* 244 * EP93xx GPIO 245 *************************************************************************/ 246 static struct resource ep93xx_gpio_resource[] = { 247 DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc), 248 }; 249 250 static struct platform_device ep93xx_gpio_device = { 251 .name = "gpio-ep93xx", 252 .id = -1, 253 .num_resources = ARRAY_SIZE(ep93xx_gpio_resource), 254 .resource = ep93xx_gpio_resource, 255 }; 256 257 /************************************************************************* 258 * EP93xx peripheral handling 259 *************************************************************************/ 260 #define EP93XX_UART_MCR_OFFSET (0x0100) 261 262 static void ep93xx_uart_set_mctrl(struct amba_device *dev, 263 void __iomem *base, unsigned int mctrl) 264 { 265 unsigned int mcr; 266 267 mcr = 0; 268 if (mctrl & TIOCM_RTS) 269 mcr |= 2; 270 if (mctrl & TIOCM_DTR) 271 mcr |= 1; 272 273 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); 274 } 275 276 static struct amba_pl010_data ep93xx_uart_data = { 277 .set_mctrl = ep93xx_uart_set_mctrl, 278 }; 279 280 static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_BASE, 281 { IRQ_EP93XX_UART1 }, &ep93xx_uart_data); 282 283 static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_BASE, 284 { IRQ_EP93XX_UART2 }, &ep93xx_uart_data); 285 286 static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE, 287 { IRQ_EP93XX_UART3 }, &ep93xx_uart_data); 288 289 static struct resource ep93xx_rtc_resource[] = { 290 DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c), 291 }; 292 293 static struct platform_device ep93xx_rtc_device = { 294 .name = "ep93xx-rtc", 295 .id = -1, 296 .num_resources = ARRAY_SIZE(ep93xx_rtc_resource), 297 .resource = ep93xx_rtc_resource, 298 }; 299 300 301 static struct resource ep93xx_ohci_resources[] = { 302 DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000), 303 DEFINE_RES_IRQ(IRQ_EP93XX_USB), 304 }; 305 306 307 static struct platform_device ep93xx_ohci_device = { 308 .name = "ep93xx-ohci", 309 .id = -1, 310 .dev = { 311 .dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask, 312 .coherent_dma_mask = DMA_BIT_MASK(32), 313 }, 314 .num_resources = ARRAY_SIZE(ep93xx_ohci_resources), 315 .resource = ep93xx_ohci_resources, 316 }; 317 318 319 /************************************************************************* 320 * EP93xx physmap'ed flash 321 *************************************************************************/ 322 static struct physmap_flash_data ep93xx_flash_data; 323 324 static struct resource ep93xx_flash_resource = { 325 .flags = IORESOURCE_MEM, 326 }; 327 328 static struct platform_device ep93xx_flash = { 329 .name = "physmap-flash", 330 .id = 0, 331 .dev = { 332 .platform_data = &ep93xx_flash_data, 333 }, 334 .num_resources = 1, 335 .resource = &ep93xx_flash_resource, 336 }; 337 338 /** 339 * ep93xx_register_flash() - Register the external flash device. 340 * @width: bank width in octets 341 * @start: resource start address 342 * @size: resource size 343 */ 344 void __init ep93xx_register_flash(unsigned int width, 345 resource_size_t start, resource_size_t size) 346 { 347 ep93xx_flash_data.width = width; 348 349 ep93xx_flash_resource.start = start; 350 ep93xx_flash_resource.end = start + size - 1; 351 352 platform_device_register(&ep93xx_flash); 353 } 354 355 356 /************************************************************************* 357 * EP93xx ethernet peripheral handling 358 *************************************************************************/ 359 static struct ep93xx_eth_data ep93xx_eth_data; 360 361 static struct resource ep93xx_eth_resource[] = { 362 DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000), 363 DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET), 364 }; 365 366 static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32); 367 368 static struct platform_device ep93xx_eth_device = { 369 .name = "ep93xx-eth", 370 .id = -1, 371 .dev = { 372 .platform_data = &ep93xx_eth_data, 373 .coherent_dma_mask = DMA_BIT_MASK(32), 374 .dma_mask = &ep93xx_eth_dma_mask, 375 }, 376 .num_resources = ARRAY_SIZE(ep93xx_eth_resource), 377 .resource = ep93xx_eth_resource, 378 }; 379 380 /** 381 * ep93xx_register_eth - Register the built-in ethernet platform device. 382 * @data: platform specific ethernet configuration (__initdata) 383 * @copy_addr: flag indicating that the MAC address should be copied 384 * from the IndAd registers (as programmed by the bootloader) 385 */ 386 void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr) 387 { 388 if (copy_addr) 389 memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6); 390 391 ep93xx_eth_data = *data; 392 platform_device_register(&ep93xx_eth_device); 393 } 394 395 396 /************************************************************************* 397 * EP93xx i2c peripheral handling 398 *************************************************************************/ 399 static struct i2c_gpio_platform_data ep93xx_i2c_data; 400 401 static struct platform_device ep93xx_i2c_device = { 402 .name = "i2c-gpio", 403 .id = 0, 404 .dev = { 405 .platform_data = &ep93xx_i2c_data, 406 }, 407 }; 408 409 /** 410 * ep93xx_register_i2c - Register the i2c platform device. 411 * @data: platform specific i2c-gpio configuration (__initdata) 412 * @devices: platform specific i2c bus device information (__initdata) 413 * @num: the number of devices on the i2c bus 414 */ 415 void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data, 416 struct i2c_board_info *devices, int num) 417 { 418 /* 419 * Set the EEPROM interface pin drive type control. 420 * Defines the driver type for the EECLK and EEDAT pins as either 421 * open drain, which will require an external pull-up, or a normal 422 * CMOS driver. 423 */ 424 if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT) 425 pr_warning("sda != EEDAT, open drain has no effect\n"); 426 if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK) 427 pr_warning("scl != EECLK, open drain has no effect\n"); 428 429 __raw_writel((data->sda_is_open_drain << 1) | 430 (data->scl_is_open_drain << 0), 431 EP93XX_GPIO_EEDRIVE); 432 433 ep93xx_i2c_data = *data; 434 i2c_register_board_info(0, devices, num); 435 platform_device_register(&ep93xx_i2c_device); 436 } 437 438 /************************************************************************* 439 * EP93xx SPI peripheral handling 440 *************************************************************************/ 441 static struct ep93xx_spi_info ep93xx_spi_master_data; 442 443 static struct resource ep93xx_spi_resources[] = { 444 DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18), 445 DEFINE_RES_IRQ(IRQ_EP93XX_SSP), 446 }; 447 448 static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32); 449 450 static struct platform_device ep93xx_spi_device = { 451 .name = "ep93xx-spi", 452 .id = 0, 453 .dev = { 454 .platform_data = &ep93xx_spi_master_data, 455 .coherent_dma_mask = DMA_BIT_MASK(32), 456 .dma_mask = &ep93xx_spi_dma_mask, 457 }, 458 .num_resources = ARRAY_SIZE(ep93xx_spi_resources), 459 .resource = ep93xx_spi_resources, 460 }; 461 462 /** 463 * ep93xx_register_spi() - registers spi platform device 464 * @info: ep93xx board specific spi master info (__initdata) 465 * @devices: SPI devices to register (__initdata) 466 * @num: number of SPI devices to register 467 * 468 * This function registers platform device for the EP93xx SPI controller and 469 * also makes sure that SPI pins are muxed so that I2S is not using those pins. 470 */ 471 void __init ep93xx_register_spi(struct ep93xx_spi_info *info, 472 struct spi_board_info *devices, int num) 473 { 474 /* 475 * When SPI is used, we need to make sure that I2S is muxed off from 476 * SPI pins. 477 */ 478 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP); 479 480 ep93xx_spi_master_data = *info; 481 spi_register_board_info(devices, num); 482 platform_device_register(&ep93xx_spi_device); 483 } 484 485 /************************************************************************* 486 * EP93xx LEDs 487 *************************************************************************/ 488 static const struct gpio_led ep93xx_led_pins[] __initconst = { 489 { 490 .name = "platform:grled", 491 .gpio = EP93XX_GPIO_LINE_GRLED, 492 }, { 493 .name = "platform:rdled", 494 .gpio = EP93XX_GPIO_LINE_RDLED, 495 }, 496 }; 497 498 static const struct gpio_led_platform_data ep93xx_led_data __initconst = { 499 .num_leds = ARRAY_SIZE(ep93xx_led_pins), 500 .leds = ep93xx_led_pins, 501 }; 502 503 /************************************************************************* 504 * EP93xx pwm peripheral handling 505 *************************************************************************/ 506 static struct resource ep93xx_pwm0_resource[] = { 507 DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10), 508 }; 509 510 static struct platform_device ep93xx_pwm0_device = { 511 .name = "ep93xx-pwm", 512 .id = 0, 513 .num_resources = ARRAY_SIZE(ep93xx_pwm0_resource), 514 .resource = ep93xx_pwm0_resource, 515 }; 516 517 static struct resource ep93xx_pwm1_resource[] = { 518 DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10), 519 }; 520 521 static struct platform_device ep93xx_pwm1_device = { 522 .name = "ep93xx-pwm", 523 .id = 1, 524 .num_resources = ARRAY_SIZE(ep93xx_pwm1_resource), 525 .resource = ep93xx_pwm1_resource, 526 }; 527 528 void __init ep93xx_register_pwm(int pwm0, int pwm1) 529 { 530 if (pwm0) 531 platform_device_register(&ep93xx_pwm0_device); 532 533 /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */ 534 if (pwm1) 535 platform_device_register(&ep93xx_pwm1_device); 536 } 537 538 int ep93xx_pwm_acquire_gpio(struct platform_device *pdev) 539 { 540 int err; 541 542 if (pdev->id == 0) { 543 err = 0; 544 } else if (pdev->id == 1) { 545 err = gpio_request(EP93XX_GPIO_LINE_EGPIO14, 546 dev_name(&pdev->dev)); 547 if (err) 548 return err; 549 err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0); 550 if (err) 551 goto fail; 552 553 /* PWM 1 output on EGPIO[14] */ 554 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG); 555 } else { 556 err = -ENODEV; 557 } 558 559 return err; 560 561 fail: 562 gpio_free(EP93XX_GPIO_LINE_EGPIO14); 563 return err; 564 } 565 EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio); 566 567 void ep93xx_pwm_release_gpio(struct platform_device *pdev) 568 { 569 if (pdev->id == 1) { 570 gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14); 571 gpio_free(EP93XX_GPIO_LINE_EGPIO14); 572 573 /* EGPIO[14] used for GPIO */ 574 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG); 575 } 576 } 577 EXPORT_SYMBOL(ep93xx_pwm_release_gpio); 578 579 580 /************************************************************************* 581 * EP93xx video peripheral handling 582 *************************************************************************/ 583 static struct ep93xxfb_mach_info ep93xxfb_data; 584 585 static struct resource ep93xx_fb_resource[] = { 586 DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800), 587 }; 588 589 static struct platform_device ep93xx_fb_device = { 590 .name = "ep93xx-fb", 591 .id = -1, 592 .dev = { 593 .platform_data = &ep93xxfb_data, 594 .coherent_dma_mask = DMA_BIT_MASK(32), 595 .dma_mask = &ep93xx_fb_device.dev.coherent_dma_mask, 596 }, 597 .num_resources = ARRAY_SIZE(ep93xx_fb_resource), 598 .resource = ep93xx_fb_resource, 599 }; 600 601 /* The backlight use a single register in the framebuffer's register space */ 602 #define EP93XX_RASTER_REG_BRIGHTNESS 0x20 603 604 static struct resource ep93xx_bl_resources[] = { 605 DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE + 606 EP93XX_RASTER_REG_BRIGHTNESS, 0x04), 607 }; 608 609 static struct platform_device ep93xx_bl_device = { 610 .name = "ep93xx-bl", 611 .id = -1, 612 .num_resources = ARRAY_SIZE(ep93xx_bl_resources), 613 .resource = ep93xx_bl_resources, 614 }; 615 616 /** 617 * ep93xx_register_fb - Register the framebuffer platform device. 618 * @data: platform specific framebuffer configuration (__initdata) 619 */ 620 void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data) 621 { 622 ep93xxfb_data = *data; 623 platform_device_register(&ep93xx_fb_device); 624 platform_device_register(&ep93xx_bl_device); 625 } 626 627 628 /************************************************************************* 629 * EP93xx matrix keypad peripheral handling 630 *************************************************************************/ 631 static struct ep93xx_keypad_platform_data ep93xx_keypad_data; 632 633 static struct resource ep93xx_keypad_resource[] = { 634 DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c), 635 DEFINE_RES_IRQ(IRQ_EP93XX_KEY), 636 }; 637 638 static struct platform_device ep93xx_keypad_device = { 639 .name = "ep93xx-keypad", 640 .id = -1, 641 .dev = { 642 .platform_data = &ep93xx_keypad_data, 643 }, 644 .num_resources = ARRAY_SIZE(ep93xx_keypad_resource), 645 .resource = ep93xx_keypad_resource, 646 }; 647 648 /** 649 * ep93xx_register_keypad - Register the keypad platform device. 650 * @data: platform specific keypad configuration (__initdata) 651 */ 652 void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data) 653 { 654 ep93xx_keypad_data = *data; 655 platform_device_register(&ep93xx_keypad_device); 656 } 657 658 int ep93xx_keypad_acquire_gpio(struct platform_device *pdev) 659 { 660 int err; 661 int i; 662 663 for (i = 0; i < 8; i++) { 664 err = gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev)); 665 if (err) 666 goto fail_gpio_c; 667 err = gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev)); 668 if (err) 669 goto fail_gpio_d; 670 } 671 672 /* Enable the keypad controller; GPIO ports C and D used for keypad */ 673 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS | 674 EP93XX_SYSCON_DEVCFG_GONK); 675 676 return 0; 677 678 fail_gpio_d: 679 gpio_free(EP93XX_GPIO_LINE_C(i)); 680 fail_gpio_c: 681 for (--i; i >= 0; --i) { 682 gpio_free(EP93XX_GPIO_LINE_C(i)); 683 gpio_free(EP93XX_GPIO_LINE_D(i)); 684 } 685 return err; 686 } 687 EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio); 688 689 void ep93xx_keypad_release_gpio(struct platform_device *pdev) 690 { 691 int i; 692 693 for (i = 0; i < 8; i++) { 694 gpio_free(EP93XX_GPIO_LINE_C(i)); 695 gpio_free(EP93XX_GPIO_LINE_D(i)); 696 } 697 698 /* Disable the keypad controller; GPIO ports C and D used for GPIO */ 699 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS | 700 EP93XX_SYSCON_DEVCFG_GONK); 701 } 702 EXPORT_SYMBOL(ep93xx_keypad_release_gpio); 703 704 /************************************************************************* 705 * EP93xx I2S audio peripheral handling 706 *************************************************************************/ 707 static struct resource ep93xx_i2s_resource[] = { 708 DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100), 709 }; 710 711 static struct platform_device ep93xx_i2s_device = { 712 .name = "ep93xx-i2s", 713 .id = -1, 714 .num_resources = ARRAY_SIZE(ep93xx_i2s_resource), 715 .resource = ep93xx_i2s_resource, 716 }; 717 718 static struct platform_device ep93xx_pcm_device = { 719 .name = "ep93xx-pcm-audio", 720 .id = -1, 721 }; 722 723 void __init ep93xx_register_i2s(void) 724 { 725 platform_device_register(&ep93xx_i2s_device); 726 platform_device_register(&ep93xx_pcm_device); 727 } 728 729 #define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \ 730 EP93XX_SYSCON_DEVCFG_I2SONAC97) 731 732 #define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \ 733 EP93XX_SYSCON_I2SCLKDIV_SPOL) 734 735 int ep93xx_i2s_acquire(void) 736 { 737 unsigned val; 738 739 ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97, 740 EP93XX_SYSCON_DEVCFG_I2S_MASK); 741 742 /* 743 * This is potentially racy with the clock api for i2s_mclk, sclk and 744 * lrclk. Since the i2s driver is the only user of those clocks we 745 * rely on it to prevent parallel use of this function and the 746 * clock api for the i2s clocks. 747 */ 748 val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV); 749 val &= ~EP93XX_I2SCLKDIV_MASK; 750 val |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL; 751 ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV); 752 753 return 0; 754 } 755 EXPORT_SYMBOL(ep93xx_i2s_acquire); 756 757 void ep93xx_i2s_release(void) 758 { 759 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK); 760 } 761 EXPORT_SYMBOL(ep93xx_i2s_release); 762 763 /************************************************************************* 764 * EP93xx AC97 audio peripheral handling 765 *************************************************************************/ 766 static struct resource ep93xx_ac97_resources[] = { 767 DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac), 768 DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR), 769 }; 770 771 static struct platform_device ep93xx_ac97_device = { 772 .name = "ep93xx-ac97", 773 .id = -1, 774 .num_resources = ARRAY_SIZE(ep93xx_ac97_resources), 775 .resource = ep93xx_ac97_resources, 776 }; 777 778 void __init ep93xx_register_ac97(void) 779 { 780 /* 781 * Make sure that the AC97 pins are not used by I2S. 782 */ 783 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97); 784 785 platform_device_register(&ep93xx_ac97_device); 786 platform_device_register(&ep93xx_pcm_device); 787 } 788 789 /************************************************************************* 790 * EP93xx Watchdog 791 *************************************************************************/ 792 static struct resource ep93xx_wdt_resources[] = { 793 DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08), 794 }; 795 796 static struct platform_device ep93xx_wdt_device = { 797 .name = "ep93xx-wdt", 798 .id = -1, 799 .num_resources = ARRAY_SIZE(ep93xx_wdt_resources), 800 .resource = ep93xx_wdt_resources, 801 }; 802 803 /************************************************************************* 804 * EP93xx IDE 805 *************************************************************************/ 806 static struct resource ep93xx_ide_resources[] = { 807 DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38), 808 DEFINE_RES_IRQ(IRQ_EP93XX_EXT3), 809 }; 810 811 static struct platform_device ep93xx_ide_device = { 812 .name = "ep93xx-ide", 813 .id = -1, 814 .dev = { 815 .dma_mask = &ep93xx_ide_device.dev.coherent_dma_mask, 816 .coherent_dma_mask = DMA_BIT_MASK(32), 817 }, 818 .num_resources = ARRAY_SIZE(ep93xx_ide_resources), 819 .resource = ep93xx_ide_resources, 820 }; 821 822 void __init ep93xx_register_ide(void) 823 { 824 platform_device_register(&ep93xx_ide_device); 825 } 826 827 int ep93xx_ide_acquire_gpio(struct platform_device *pdev) 828 { 829 int err; 830 int i; 831 832 err = gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev)); 833 if (err) 834 return err; 835 err = gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev)); 836 if (err) 837 goto fail_egpio15; 838 for (i = 2; i < 8; i++) { 839 err = gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev)); 840 if (err) 841 goto fail_gpio_e; 842 } 843 for (i = 4; i < 8; i++) { 844 err = gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev)); 845 if (err) 846 goto fail_gpio_g; 847 } 848 for (i = 0; i < 8; i++) { 849 err = gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev)); 850 if (err) 851 goto fail_gpio_h; 852 } 853 854 /* GPIO ports E[7:2], G[7:4] and H used by IDE */ 855 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE | 856 EP93XX_SYSCON_DEVCFG_GONIDE | 857 EP93XX_SYSCON_DEVCFG_HONIDE); 858 return 0; 859 860 fail_gpio_h: 861 for (--i; i >= 0; --i) 862 gpio_free(EP93XX_GPIO_LINE_H(i)); 863 i = 8; 864 fail_gpio_g: 865 for (--i; i >= 4; --i) 866 gpio_free(EP93XX_GPIO_LINE_G(i)); 867 i = 8; 868 fail_gpio_e: 869 for (--i; i >= 2; --i) 870 gpio_free(EP93XX_GPIO_LINE_E(i)); 871 gpio_free(EP93XX_GPIO_LINE_EGPIO15); 872 fail_egpio15: 873 gpio_free(EP93XX_GPIO_LINE_EGPIO2); 874 return err; 875 } 876 EXPORT_SYMBOL(ep93xx_ide_acquire_gpio); 877 878 void ep93xx_ide_release_gpio(struct platform_device *pdev) 879 { 880 int i; 881 882 for (i = 2; i < 8; i++) 883 gpio_free(EP93XX_GPIO_LINE_E(i)); 884 for (i = 4; i < 8; i++) 885 gpio_free(EP93XX_GPIO_LINE_G(i)); 886 for (i = 0; i < 8; i++) 887 gpio_free(EP93XX_GPIO_LINE_H(i)); 888 gpio_free(EP93XX_GPIO_LINE_EGPIO15); 889 gpio_free(EP93XX_GPIO_LINE_EGPIO2); 890 891 892 /* GPIO ports E[7:2], G[7:4] and H used by GPIO */ 893 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE | 894 EP93XX_SYSCON_DEVCFG_GONIDE | 895 EP93XX_SYSCON_DEVCFG_HONIDE); 896 } 897 EXPORT_SYMBOL(ep93xx_ide_release_gpio); 898 899 void __init ep93xx_init_devices(void) 900 { 901 /* Disallow access to MaverickCrunch initially */ 902 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA); 903 904 /* Default all ports to GPIO */ 905 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS | 906 EP93XX_SYSCON_DEVCFG_GONK | 907 EP93XX_SYSCON_DEVCFG_EONIDE | 908 EP93XX_SYSCON_DEVCFG_GONIDE | 909 EP93XX_SYSCON_DEVCFG_HONIDE); 910 911 /* Get the GPIO working early, other devices need it */ 912 platform_device_register(&ep93xx_gpio_device); 913 914 amba_device_register(&uart1_device, &iomem_resource); 915 amba_device_register(&uart2_device, &iomem_resource); 916 amba_device_register(&uart3_device, &iomem_resource); 917 918 platform_device_register(&ep93xx_rtc_device); 919 platform_device_register(&ep93xx_ohci_device); 920 platform_device_register(&ep93xx_wdt_device); 921 922 gpio_led_register_device(-1, &ep93xx_led_data); 923 } 924 925 void ep93xx_restart(enum reboot_mode mode, const char *cmd) 926 { 927 /* 928 * Set then clear the SWRST bit to initiate a software reset 929 */ 930 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST); 931 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST); 932 933 while (1) 934 ; 935 } 936 937 void __init ep93xx_init_late(void) 938 { 939 crunch_init(); 940 } 941