xref: /openbmc/linux/arch/arm/mach-ep93xx/core.c (revision 31b90347)
1 /*
2  * arch/arm/mach-ep93xx/core.c
3  * Core routines for Cirrus EP93xx chips.
4  *
5  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6  * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
7  *
8  * Thanks go to Michael Burian and Ray Lehtiniemi for their key
9  * role in the ep93xx linux community.
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or (at
14  * your option) any later version.
15  */
16 
17 #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
18 
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/interrupt.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/timex.h>
25 #include <linux/irq.h>
26 #include <linux/io.h>
27 #include <linux/gpio.h>
28 #include <linux/leds.h>
29 #include <linux/termios.h>
30 #include <linux/amba/bus.h>
31 #include <linux/amba/serial.h>
32 #include <linux/mtd/physmap.h>
33 #include <linux/i2c.h>
34 #include <linux/i2c-gpio.h>
35 #include <linux/spi/spi.h>
36 #include <linux/export.h>
37 #include <linux/irqchip/arm-vic.h>
38 #include <linux/reboot.h>
39 #include <linux/usb/ohci_pdriver.h>
40 
41 #include <mach/hardware.h>
42 #include <linux/platform_data/video-ep93xx.h>
43 #include <linux/platform_data/keypad-ep93xx.h>
44 #include <linux/platform_data/spi-ep93xx.h>
45 #include <mach/gpio-ep93xx.h>
46 
47 #include <asm/mach/map.h>
48 #include <asm/mach/time.h>
49 
50 #include "soc.h"
51 
52 /*************************************************************************
53  * Static I/O mappings that are needed for all EP93xx platforms
54  *************************************************************************/
55 static struct map_desc ep93xx_io_desc[] __initdata = {
56 	{
57 		.virtual	= EP93XX_AHB_VIRT_BASE,
58 		.pfn		= __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
59 		.length		= EP93XX_AHB_SIZE,
60 		.type		= MT_DEVICE,
61 	}, {
62 		.virtual	= EP93XX_APB_VIRT_BASE,
63 		.pfn		= __phys_to_pfn(EP93XX_APB_PHYS_BASE),
64 		.length		= EP93XX_APB_SIZE,
65 		.type		= MT_DEVICE,
66 	},
67 };
68 
69 void __init ep93xx_map_io(void)
70 {
71 	iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
72 }
73 
74 
75 /*************************************************************************
76  * Timer handling for EP93xx
77  *************************************************************************
78  * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and
79  * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
80  * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,
81  * is free-running, and can't generate interrupts.
82  *
83  * The 508 kHz timers are ideal for use for the timer interrupt, as the
84  * most common values of HZ divide 508 kHz nicely.  We pick one of the 16
85  * bit timers (timer 1) since we don't need more than 16 bits of reload
86  * value as long as HZ >= 8.
87  *
88  * The higher clock rate of timer 4 makes it a better choice than the
89  * other timers for use in gettimeoffset(), while the fact that it can't
90  * generate interrupts means we don't have to worry about not being able
91  * to use this timer for something else.  We also use timer 4 for keeping
92  * track of lost jiffies.
93  */
94 #define EP93XX_TIMER_REG(x)		(EP93XX_TIMER_BASE + (x))
95 #define EP93XX_TIMER1_LOAD		EP93XX_TIMER_REG(0x00)
96 #define EP93XX_TIMER1_VALUE		EP93XX_TIMER_REG(0x04)
97 #define EP93XX_TIMER1_CONTROL		EP93XX_TIMER_REG(0x08)
98 #define EP93XX_TIMER123_CONTROL_ENABLE	(1 << 7)
99 #define EP93XX_TIMER123_CONTROL_MODE	(1 << 6)
100 #define EP93XX_TIMER123_CONTROL_CLKSEL	(1 << 3)
101 #define EP93XX_TIMER1_CLEAR		EP93XX_TIMER_REG(0x0c)
102 #define EP93XX_TIMER2_LOAD		EP93XX_TIMER_REG(0x20)
103 #define EP93XX_TIMER2_VALUE		EP93XX_TIMER_REG(0x24)
104 #define EP93XX_TIMER2_CONTROL		EP93XX_TIMER_REG(0x28)
105 #define EP93XX_TIMER2_CLEAR		EP93XX_TIMER_REG(0x2c)
106 #define EP93XX_TIMER4_VALUE_LOW		EP93XX_TIMER_REG(0x60)
107 #define EP93XX_TIMER4_VALUE_HIGH	EP93XX_TIMER_REG(0x64)
108 #define EP93XX_TIMER4_VALUE_HIGH_ENABLE	(1 << 8)
109 #define EP93XX_TIMER3_LOAD		EP93XX_TIMER_REG(0x80)
110 #define EP93XX_TIMER3_VALUE		EP93XX_TIMER_REG(0x84)
111 #define EP93XX_TIMER3_CONTROL		EP93XX_TIMER_REG(0x88)
112 #define EP93XX_TIMER3_CLEAR		EP93XX_TIMER_REG(0x8c)
113 
114 #define EP93XX_TIMER123_CLOCK		508469
115 #define EP93XX_TIMER4_CLOCK		983040
116 
117 #define TIMER1_RELOAD			((EP93XX_TIMER123_CLOCK / HZ) - 1)
118 #define TIMER4_TICKS_PER_JIFFY		DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
119 
120 static unsigned int last_jiffy_time;
121 
122 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
123 {
124 	/* Writing any value clears the timer interrupt */
125 	__raw_writel(1, EP93XX_TIMER1_CLEAR);
126 
127 	/* Recover lost jiffies */
128 	while ((signed long)
129 		(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
130 						>= TIMER4_TICKS_PER_JIFFY) {
131 		last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
132 		timer_tick();
133 	}
134 
135 	return IRQ_HANDLED;
136 }
137 
138 static struct irqaction ep93xx_timer_irq = {
139 	.name		= "ep93xx timer",
140 	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
141 	.handler	= ep93xx_timer_interrupt,
142 };
143 
144 static u32 ep93xx_gettimeoffset(void)
145 {
146 	int offset;
147 
148 	offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
149 
150 	/*
151 	 * Timer 4 is based on a 983.04 kHz reference clock,
152 	 * so dividing by 983040 gives the fraction of a second,
153 	 * so dividing by 0.983040 converts to uS.
154 	 * Refactor the calculation to avoid overflow.
155 	 * Finally, multiply by 1000 to give nS.
156 	 */
157 	return (offset + (53 * offset / 3072)) * 1000;
158 }
159 
160 void __init ep93xx_timer_init(void)
161 {
162 	u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
163 		    EP93XX_TIMER123_CONTROL_CLKSEL;
164 
165 	arch_gettimeoffset = ep93xx_gettimeoffset;
166 
167 	/* Enable periodic HZ timer.  */
168 	__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
169 	__raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
170 	__raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
171 			EP93XX_TIMER1_CONTROL);
172 
173 	/* Enable lost jiffy timer.  */
174 	__raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
175 			EP93XX_TIMER4_VALUE_HIGH);
176 
177 	setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
178 }
179 
180 
181 /*************************************************************************
182  * EP93xx IRQ handling
183  *************************************************************************/
184 void __init ep93xx_init_irq(void)
185 {
186 	vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
187 	vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
188 }
189 
190 
191 /*************************************************************************
192  * EP93xx System Controller Software Locked register handling
193  *************************************************************************/
194 
195 /*
196  * syscon_swlock prevents anything else from writing to the syscon
197  * block while a software locked register is being written.
198  */
199 static DEFINE_SPINLOCK(syscon_swlock);
200 
201 void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
202 {
203 	unsigned long flags;
204 
205 	spin_lock_irqsave(&syscon_swlock, flags);
206 
207 	__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
208 	__raw_writel(val, reg);
209 
210 	spin_unlock_irqrestore(&syscon_swlock, flags);
211 }
212 
213 void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
214 {
215 	unsigned long flags;
216 	unsigned int val;
217 
218 	spin_lock_irqsave(&syscon_swlock, flags);
219 
220 	val = __raw_readl(EP93XX_SYSCON_DEVCFG);
221 	val &= ~clear_bits;
222 	val |= set_bits;
223 	__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
224 	__raw_writel(val, EP93XX_SYSCON_DEVCFG);
225 
226 	spin_unlock_irqrestore(&syscon_swlock, flags);
227 }
228 
229 /**
230  * ep93xx_chip_revision() - returns the EP93xx chip revision
231  *
232  * See <mach/platform.h> for more information.
233  */
234 unsigned int ep93xx_chip_revision(void)
235 {
236 	unsigned int v;
237 
238 	v = __raw_readl(EP93XX_SYSCON_SYSCFG);
239 	v &= EP93XX_SYSCON_SYSCFG_REV_MASK;
240 	v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT;
241 	return v;
242 }
243 
244 /*************************************************************************
245  * EP93xx GPIO
246  *************************************************************************/
247 static struct resource ep93xx_gpio_resource[] = {
248 	DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc),
249 };
250 
251 static struct platform_device ep93xx_gpio_device = {
252 	.name		= "gpio-ep93xx",
253 	.id		= -1,
254 	.num_resources	= ARRAY_SIZE(ep93xx_gpio_resource),
255 	.resource	= ep93xx_gpio_resource,
256 };
257 
258 /*************************************************************************
259  * EP93xx peripheral handling
260  *************************************************************************/
261 #define EP93XX_UART_MCR_OFFSET		(0x0100)
262 
263 static void ep93xx_uart_set_mctrl(struct amba_device *dev,
264 				  void __iomem *base, unsigned int mctrl)
265 {
266 	unsigned int mcr;
267 
268 	mcr = 0;
269 	if (mctrl & TIOCM_RTS)
270 		mcr |= 2;
271 	if (mctrl & TIOCM_DTR)
272 		mcr |= 1;
273 
274 	__raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
275 }
276 
277 static struct amba_pl010_data ep93xx_uart_data = {
278 	.set_mctrl	= ep93xx_uart_set_mctrl,
279 };
280 
281 static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_BASE,
282 	{ IRQ_EP93XX_UART1 }, &ep93xx_uart_data);
283 
284 static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_BASE,
285 	{ IRQ_EP93XX_UART2 }, NULL);
286 
287 static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE,
288 	{ IRQ_EP93XX_UART3 }, &ep93xx_uart_data);
289 
290 static struct resource ep93xx_rtc_resource[] = {
291 	DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c),
292 };
293 
294 static struct platform_device ep93xx_rtc_device = {
295 	.name		= "ep93xx-rtc",
296 	.id		= -1,
297 	.num_resources	= ARRAY_SIZE(ep93xx_rtc_resource),
298 	.resource	= ep93xx_rtc_resource,
299 };
300 
301 /*************************************************************************
302  * EP93xx OHCI USB Host
303  *************************************************************************/
304 
305 static struct clk *ep93xx_ohci_host_clock;
306 
307 static int ep93xx_ohci_power_on(struct platform_device *pdev)
308 {
309 	if (!ep93xx_ohci_host_clock) {
310 		ep93xx_ohci_host_clock = devm_clk_get(&pdev->dev, NULL);
311 		if (IS_ERR(ep93xx_ohci_host_clock))
312 			return PTR_ERR(ep93xx_ohci_host_clock);
313 	}
314 
315 	return clk_enable(ep93xx_ohci_host_clock);
316 }
317 
318 static void ep93xx_ohci_power_off(struct platform_device *pdev)
319 {
320 	clk_disable(ep93xx_ohci_host_clock);
321 }
322 
323 static struct usb_ohci_pdata ep93xx_ohci_pdata = {
324 	.power_on	= ep93xx_ohci_power_on,
325 	.power_off	= ep93xx_ohci_power_off,
326 	.power_suspend	= ep93xx_ohci_power_off,
327 };
328 
329 static struct resource ep93xx_ohci_resources[] = {
330 	DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000),
331 	DEFINE_RES_IRQ(IRQ_EP93XX_USB),
332 };
333 
334 static u64 ep93xx_ohci_dma_mask = DMA_BIT_MASK(32);
335 
336 static struct platform_device ep93xx_ohci_device = {
337 	.name		= "ohci-platform",
338 	.id		= -1,
339 	.num_resources	= ARRAY_SIZE(ep93xx_ohci_resources),
340 	.resource	= ep93xx_ohci_resources,
341 	.dev		= {
342 		.dma_mask		= &ep93xx_ohci_dma_mask,
343 		.coherent_dma_mask	= DMA_BIT_MASK(32),
344 		.platform_data		= &ep93xx_ohci_pdata,
345 	},
346 };
347 
348 /*************************************************************************
349  * EP93xx physmap'ed flash
350  *************************************************************************/
351 static struct physmap_flash_data ep93xx_flash_data;
352 
353 static struct resource ep93xx_flash_resource = {
354 	.flags		= IORESOURCE_MEM,
355 };
356 
357 static struct platform_device ep93xx_flash = {
358 	.name		= "physmap-flash",
359 	.id		= 0,
360 	.dev		= {
361 		.platform_data	= &ep93xx_flash_data,
362 	},
363 	.num_resources	= 1,
364 	.resource	= &ep93xx_flash_resource,
365 };
366 
367 /**
368  * ep93xx_register_flash() - Register the external flash device.
369  * @width:	bank width in octets
370  * @start:	resource start address
371  * @size:	resource size
372  */
373 void __init ep93xx_register_flash(unsigned int width,
374 				  resource_size_t start, resource_size_t size)
375 {
376 	ep93xx_flash_data.width		= width;
377 
378 	ep93xx_flash_resource.start	= start;
379 	ep93xx_flash_resource.end	= start + size - 1;
380 
381 	platform_device_register(&ep93xx_flash);
382 }
383 
384 
385 /*************************************************************************
386  * EP93xx ethernet peripheral handling
387  *************************************************************************/
388 static struct ep93xx_eth_data ep93xx_eth_data;
389 
390 static struct resource ep93xx_eth_resource[] = {
391 	DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000),
392 	DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET),
393 };
394 
395 static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32);
396 
397 static struct platform_device ep93xx_eth_device = {
398 	.name		= "ep93xx-eth",
399 	.id		= -1,
400 	.dev		= {
401 		.platform_data		= &ep93xx_eth_data,
402 		.coherent_dma_mask	= DMA_BIT_MASK(32),
403 		.dma_mask		= &ep93xx_eth_dma_mask,
404 	},
405 	.num_resources	= ARRAY_SIZE(ep93xx_eth_resource),
406 	.resource	= ep93xx_eth_resource,
407 };
408 
409 /**
410  * ep93xx_register_eth - Register the built-in ethernet platform device.
411  * @data:	platform specific ethernet configuration (__initdata)
412  * @copy_addr:	flag indicating that the MAC address should be copied
413  *		from the IndAd registers (as programmed by the bootloader)
414  */
415 void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
416 {
417 	if (copy_addr)
418 		memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6);
419 
420 	ep93xx_eth_data = *data;
421 	platform_device_register(&ep93xx_eth_device);
422 }
423 
424 
425 /*************************************************************************
426  * EP93xx i2c peripheral handling
427  *************************************************************************/
428 static struct i2c_gpio_platform_data ep93xx_i2c_data;
429 
430 static struct platform_device ep93xx_i2c_device = {
431 	.name		= "i2c-gpio",
432 	.id		= 0,
433 	.dev		= {
434 		.platform_data	= &ep93xx_i2c_data,
435 	},
436 };
437 
438 /**
439  * ep93xx_register_i2c - Register the i2c platform device.
440  * @data:	platform specific i2c-gpio configuration (__initdata)
441  * @devices:	platform specific i2c bus device information (__initdata)
442  * @num:	the number of devices on the i2c bus
443  */
444 void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
445 				struct i2c_board_info *devices, int num)
446 {
447 	/*
448 	 * Set the EEPROM interface pin drive type control.
449 	 * Defines the driver type for the EECLK and EEDAT pins as either
450 	 * open drain, which will require an external pull-up, or a normal
451 	 * CMOS driver.
452 	 */
453 	if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT)
454 		pr_warning("sda != EEDAT, open drain has no effect\n");
455 	if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK)
456 		pr_warning("scl != EECLK, open drain has no effect\n");
457 
458 	__raw_writel((data->sda_is_open_drain << 1) |
459 		     (data->scl_is_open_drain << 0),
460 		     EP93XX_GPIO_EEDRIVE);
461 
462 	ep93xx_i2c_data = *data;
463 	i2c_register_board_info(0, devices, num);
464 	platform_device_register(&ep93xx_i2c_device);
465 }
466 
467 /*************************************************************************
468  * EP93xx SPI peripheral handling
469  *************************************************************************/
470 static struct ep93xx_spi_info ep93xx_spi_master_data;
471 
472 static struct resource ep93xx_spi_resources[] = {
473 	DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18),
474 	DEFINE_RES_IRQ(IRQ_EP93XX_SSP),
475 };
476 
477 static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32);
478 
479 static struct platform_device ep93xx_spi_device = {
480 	.name		= "ep93xx-spi",
481 	.id		= 0,
482 	.dev		= {
483 		.platform_data		= &ep93xx_spi_master_data,
484 		.coherent_dma_mask	= DMA_BIT_MASK(32),
485 		.dma_mask		= &ep93xx_spi_dma_mask,
486 	},
487 	.num_resources	= ARRAY_SIZE(ep93xx_spi_resources),
488 	.resource	= ep93xx_spi_resources,
489 };
490 
491 /**
492  * ep93xx_register_spi() - registers spi platform device
493  * @info: ep93xx board specific spi master info (__initdata)
494  * @devices: SPI devices to register (__initdata)
495  * @num: number of SPI devices to register
496  *
497  * This function registers platform device for the EP93xx SPI controller and
498  * also makes sure that SPI pins are muxed so that I2S is not using those pins.
499  */
500 void __init ep93xx_register_spi(struct ep93xx_spi_info *info,
501 				struct spi_board_info *devices, int num)
502 {
503 	/*
504 	 * When SPI is used, we need to make sure that I2S is muxed off from
505 	 * SPI pins.
506 	 */
507 	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP);
508 
509 	ep93xx_spi_master_data = *info;
510 	spi_register_board_info(devices, num);
511 	platform_device_register(&ep93xx_spi_device);
512 }
513 
514 /*************************************************************************
515  * EP93xx LEDs
516  *************************************************************************/
517 static const struct gpio_led ep93xx_led_pins[] __initconst = {
518 	{
519 		.name	= "platform:grled",
520 		.gpio	= EP93XX_GPIO_LINE_GRLED,
521 	}, {
522 		.name	= "platform:rdled",
523 		.gpio	= EP93XX_GPIO_LINE_RDLED,
524 	},
525 };
526 
527 static const struct gpio_led_platform_data ep93xx_led_data __initconst = {
528 	.num_leds	= ARRAY_SIZE(ep93xx_led_pins),
529 	.leds		= ep93xx_led_pins,
530 };
531 
532 /*************************************************************************
533  * EP93xx pwm peripheral handling
534  *************************************************************************/
535 static struct resource ep93xx_pwm0_resource[] = {
536 	DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10),
537 };
538 
539 static struct platform_device ep93xx_pwm0_device = {
540 	.name		= "ep93xx-pwm",
541 	.id		= 0,
542 	.num_resources	= ARRAY_SIZE(ep93xx_pwm0_resource),
543 	.resource	= ep93xx_pwm0_resource,
544 };
545 
546 static struct resource ep93xx_pwm1_resource[] = {
547 	DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10),
548 };
549 
550 static struct platform_device ep93xx_pwm1_device = {
551 	.name		= "ep93xx-pwm",
552 	.id		= 1,
553 	.num_resources	= ARRAY_SIZE(ep93xx_pwm1_resource),
554 	.resource	= ep93xx_pwm1_resource,
555 };
556 
557 void __init ep93xx_register_pwm(int pwm0, int pwm1)
558 {
559 	if (pwm0)
560 		platform_device_register(&ep93xx_pwm0_device);
561 
562 	/* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
563 	if (pwm1)
564 		platform_device_register(&ep93xx_pwm1_device);
565 }
566 
567 int ep93xx_pwm_acquire_gpio(struct platform_device *pdev)
568 {
569 	int err;
570 
571 	if (pdev->id == 0) {
572 		err = 0;
573 	} else if (pdev->id == 1) {
574 		err = gpio_request(EP93XX_GPIO_LINE_EGPIO14,
575 				   dev_name(&pdev->dev));
576 		if (err)
577 			return err;
578 		err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0);
579 		if (err)
580 			goto fail;
581 
582 		/* PWM 1 output on EGPIO[14] */
583 		ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG);
584 	} else {
585 		err = -ENODEV;
586 	}
587 
588 	return err;
589 
590 fail:
591 	gpio_free(EP93XX_GPIO_LINE_EGPIO14);
592 	return err;
593 }
594 EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio);
595 
596 void ep93xx_pwm_release_gpio(struct platform_device *pdev)
597 {
598 	if (pdev->id == 1) {
599 		gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14);
600 		gpio_free(EP93XX_GPIO_LINE_EGPIO14);
601 
602 		/* EGPIO[14] used for GPIO */
603 		ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG);
604 	}
605 }
606 EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
607 
608 
609 /*************************************************************************
610  * EP93xx video peripheral handling
611  *************************************************************************/
612 static struct ep93xxfb_mach_info ep93xxfb_data;
613 
614 static struct resource ep93xx_fb_resource[] = {
615 	DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800),
616 };
617 
618 static struct platform_device ep93xx_fb_device = {
619 	.name			= "ep93xx-fb",
620 	.id			= -1,
621 	.dev			= {
622 		.platform_data		= &ep93xxfb_data,
623 		.coherent_dma_mask	= DMA_BIT_MASK(32),
624 		.dma_mask		= &ep93xx_fb_device.dev.coherent_dma_mask,
625 	},
626 	.num_resources		= ARRAY_SIZE(ep93xx_fb_resource),
627 	.resource		= ep93xx_fb_resource,
628 };
629 
630 /* The backlight use a single register in the framebuffer's register space */
631 #define EP93XX_RASTER_REG_BRIGHTNESS 0x20
632 
633 static struct resource ep93xx_bl_resources[] = {
634 	DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE +
635 		       EP93XX_RASTER_REG_BRIGHTNESS, 0x04),
636 };
637 
638 static struct platform_device ep93xx_bl_device = {
639 	.name		= "ep93xx-bl",
640 	.id		= -1,
641 	.num_resources	= ARRAY_SIZE(ep93xx_bl_resources),
642 	.resource	= ep93xx_bl_resources,
643 };
644 
645 /**
646  * ep93xx_register_fb - Register the framebuffer platform device.
647  * @data:	platform specific framebuffer configuration (__initdata)
648  */
649 void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
650 {
651 	ep93xxfb_data = *data;
652 	platform_device_register(&ep93xx_fb_device);
653 	platform_device_register(&ep93xx_bl_device);
654 }
655 
656 
657 /*************************************************************************
658  * EP93xx matrix keypad peripheral handling
659  *************************************************************************/
660 static struct ep93xx_keypad_platform_data ep93xx_keypad_data;
661 
662 static struct resource ep93xx_keypad_resource[] = {
663 	DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c),
664 	DEFINE_RES_IRQ(IRQ_EP93XX_KEY),
665 };
666 
667 static struct platform_device ep93xx_keypad_device = {
668 	.name		= "ep93xx-keypad",
669 	.id		= -1,
670 	.dev		= {
671 		.platform_data	= &ep93xx_keypad_data,
672 	},
673 	.num_resources	= ARRAY_SIZE(ep93xx_keypad_resource),
674 	.resource	= ep93xx_keypad_resource,
675 };
676 
677 /**
678  * ep93xx_register_keypad - Register the keypad platform device.
679  * @data:	platform specific keypad configuration (__initdata)
680  */
681 void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data)
682 {
683 	ep93xx_keypad_data = *data;
684 	platform_device_register(&ep93xx_keypad_device);
685 }
686 
687 int ep93xx_keypad_acquire_gpio(struct platform_device *pdev)
688 {
689 	int err;
690 	int i;
691 
692 	for (i = 0; i < 8; i++) {
693 		err = gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev));
694 		if (err)
695 			goto fail_gpio_c;
696 		err = gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev));
697 		if (err)
698 			goto fail_gpio_d;
699 	}
700 
701 	/* Enable the keypad controller; GPIO ports C and D used for keypad */
702 	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS |
703 				 EP93XX_SYSCON_DEVCFG_GONK);
704 
705 	return 0;
706 
707 fail_gpio_d:
708 	gpio_free(EP93XX_GPIO_LINE_C(i));
709 fail_gpio_c:
710 	for (--i; i >= 0; --i) {
711 		gpio_free(EP93XX_GPIO_LINE_C(i));
712 		gpio_free(EP93XX_GPIO_LINE_D(i));
713 	}
714 	return err;
715 }
716 EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio);
717 
718 void ep93xx_keypad_release_gpio(struct platform_device *pdev)
719 {
720 	int i;
721 
722 	for (i = 0; i < 8; i++) {
723 		gpio_free(EP93XX_GPIO_LINE_C(i));
724 		gpio_free(EP93XX_GPIO_LINE_D(i));
725 	}
726 
727 	/* Disable the keypad controller; GPIO ports C and D used for GPIO */
728 	ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
729 			       EP93XX_SYSCON_DEVCFG_GONK);
730 }
731 EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
732 
733 /*************************************************************************
734  * EP93xx I2S audio peripheral handling
735  *************************************************************************/
736 static struct resource ep93xx_i2s_resource[] = {
737 	DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100),
738 };
739 
740 static struct platform_device ep93xx_i2s_device = {
741 	.name		= "ep93xx-i2s",
742 	.id		= -1,
743 	.num_resources	= ARRAY_SIZE(ep93xx_i2s_resource),
744 	.resource	= ep93xx_i2s_resource,
745 };
746 
747 static struct platform_device ep93xx_pcm_device = {
748 	.name		= "ep93xx-pcm-audio",
749 	.id		= -1,
750 };
751 
752 void __init ep93xx_register_i2s(void)
753 {
754 	platform_device_register(&ep93xx_i2s_device);
755 	platform_device_register(&ep93xx_pcm_device);
756 }
757 
758 #define EP93XX_SYSCON_DEVCFG_I2S_MASK	(EP93XX_SYSCON_DEVCFG_I2SONSSP | \
759 					 EP93XX_SYSCON_DEVCFG_I2SONAC97)
760 
761 #define EP93XX_I2SCLKDIV_MASK		(EP93XX_SYSCON_I2SCLKDIV_ORIDE | \
762 					 EP93XX_SYSCON_I2SCLKDIV_SPOL)
763 
764 int ep93xx_i2s_acquire(void)
765 {
766 	unsigned val;
767 
768 	ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97,
769 			EP93XX_SYSCON_DEVCFG_I2S_MASK);
770 
771 	/*
772 	 * This is potentially racy with the clock api for i2s_mclk, sclk and
773 	 * lrclk. Since the i2s driver is the only user of those clocks we
774 	 * rely on it to prevent parallel use of this function and the
775 	 * clock api for the i2s clocks.
776 	 */
777 	val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
778 	val &= ~EP93XX_I2SCLKDIV_MASK;
779 	val |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL;
780 	ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV);
781 
782 	return 0;
783 }
784 EXPORT_SYMBOL(ep93xx_i2s_acquire);
785 
786 void ep93xx_i2s_release(void)
787 {
788 	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
789 }
790 EXPORT_SYMBOL(ep93xx_i2s_release);
791 
792 /*************************************************************************
793  * EP93xx AC97 audio peripheral handling
794  *************************************************************************/
795 static struct resource ep93xx_ac97_resources[] = {
796 	DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac),
797 	DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR),
798 };
799 
800 static struct platform_device ep93xx_ac97_device = {
801 	.name		= "ep93xx-ac97",
802 	.id		= -1,
803 	.num_resources	= ARRAY_SIZE(ep93xx_ac97_resources),
804 	.resource	= ep93xx_ac97_resources,
805 };
806 
807 void __init ep93xx_register_ac97(void)
808 {
809 	/*
810 	 * Make sure that the AC97 pins are not used by I2S.
811 	 */
812 	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97);
813 
814 	platform_device_register(&ep93xx_ac97_device);
815 	platform_device_register(&ep93xx_pcm_device);
816 }
817 
818 /*************************************************************************
819  * EP93xx Watchdog
820  *************************************************************************/
821 static struct resource ep93xx_wdt_resources[] = {
822 	DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08),
823 };
824 
825 static struct platform_device ep93xx_wdt_device = {
826 	.name		= "ep93xx-wdt",
827 	.id		= -1,
828 	.num_resources	= ARRAY_SIZE(ep93xx_wdt_resources),
829 	.resource	= ep93xx_wdt_resources,
830 };
831 
832 /*************************************************************************
833  * EP93xx IDE
834  *************************************************************************/
835 static struct resource ep93xx_ide_resources[] = {
836 	DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38),
837 	DEFINE_RES_IRQ(IRQ_EP93XX_EXT3),
838 };
839 
840 static struct platform_device ep93xx_ide_device = {
841 	.name		= "ep93xx-ide",
842 	.id		= -1,
843 	.dev		= {
844 		.dma_mask		= &ep93xx_ide_device.dev.coherent_dma_mask,
845 		.coherent_dma_mask	= DMA_BIT_MASK(32),
846 	},
847 	.num_resources	= ARRAY_SIZE(ep93xx_ide_resources),
848 	.resource	= ep93xx_ide_resources,
849 };
850 
851 void __init ep93xx_register_ide(void)
852 {
853 	platform_device_register(&ep93xx_ide_device);
854 }
855 
856 int ep93xx_ide_acquire_gpio(struct platform_device *pdev)
857 {
858 	int err;
859 	int i;
860 
861 	err = gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev));
862 	if (err)
863 		return err;
864 	err = gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev));
865 	if (err)
866 		goto fail_egpio15;
867 	for (i = 2; i < 8; i++) {
868 		err = gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev));
869 		if (err)
870 			goto fail_gpio_e;
871 	}
872 	for (i = 4; i < 8; i++) {
873 		err = gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev));
874 		if (err)
875 			goto fail_gpio_g;
876 	}
877 	for (i = 0; i < 8; i++) {
878 		err = gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev));
879 		if (err)
880 			goto fail_gpio_h;
881 	}
882 
883 	/* GPIO ports E[7:2], G[7:4] and H used by IDE */
884 	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
885 				 EP93XX_SYSCON_DEVCFG_GONIDE |
886 				 EP93XX_SYSCON_DEVCFG_HONIDE);
887 	return 0;
888 
889 fail_gpio_h:
890 	for (--i; i >= 0; --i)
891 		gpio_free(EP93XX_GPIO_LINE_H(i));
892 	i = 8;
893 fail_gpio_g:
894 	for (--i; i >= 4; --i)
895 		gpio_free(EP93XX_GPIO_LINE_G(i));
896 	i = 8;
897 fail_gpio_e:
898 	for (--i; i >= 2; --i)
899 		gpio_free(EP93XX_GPIO_LINE_E(i));
900 	gpio_free(EP93XX_GPIO_LINE_EGPIO15);
901 fail_egpio15:
902 	gpio_free(EP93XX_GPIO_LINE_EGPIO2);
903 	return err;
904 }
905 EXPORT_SYMBOL(ep93xx_ide_acquire_gpio);
906 
907 void ep93xx_ide_release_gpio(struct platform_device *pdev)
908 {
909 	int i;
910 
911 	for (i = 2; i < 8; i++)
912 		gpio_free(EP93XX_GPIO_LINE_E(i));
913 	for (i = 4; i < 8; i++)
914 		gpio_free(EP93XX_GPIO_LINE_G(i));
915 	for (i = 0; i < 8; i++)
916 		gpio_free(EP93XX_GPIO_LINE_H(i));
917 	gpio_free(EP93XX_GPIO_LINE_EGPIO15);
918 	gpio_free(EP93XX_GPIO_LINE_EGPIO2);
919 
920 
921 	/* GPIO ports E[7:2], G[7:4] and H used by GPIO */
922 	ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
923 			       EP93XX_SYSCON_DEVCFG_GONIDE |
924 			       EP93XX_SYSCON_DEVCFG_HONIDE);
925 }
926 EXPORT_SYMBOL(ep93xx_ide_release_gpio);
927 
928 void __init ep93xx_init_devices(void)
929 {
930 	/* Disallow access to MaverickCrunch initially */
931 	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
932 
933 	/* Default all ports to GPIO */
934 	ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
935 			       EP93XX_SYSCON_DEVCFG_GONK |
936 			       EP93XX_SYSCON_DEVCFG_EONIDE |
937 			       EP93XX_SYSCON_DEVCFG_GONIDE |
938 			       EP93XX_SYSCON_DEVCFG_HONIDE);
939 
940 	/* Get the GPIO working early, other devices need it */
941 	platform_device_register(&ep93xx_gpio_device);
942 
943 	amba_device_register(&uart1_device, &iomem_resource);
944 	amba_device_register(&uart2_device, &iomem_resource);
945 	amba_device_register(&uart3_device, &iomem_resource);
946 
947 	platform_device_register(&ep93xx_rtc_device);
948 	platform_device_register(&ep93xx_ohci_device);
949 	platform_device_register(&ep93xx_wdt_device);
950 
951 	gpio_led_register_device(-1, &ep93xx_led_data);
952 }
953 
954 void ep93xx_restart(enum reboot_mode mode, const char *cmd)
955 {
956 	/*
957 	 * Set then clear the SWRST bit to initiate a software reset
958 	 */
959 	ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST);
960 	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST);
961 
962 	while (1)
963 		;
964 }
965 
966 void __init ep93xx_init_late(void)
967 {
968 	crunch_init();
969 }
970