1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * arch/arm/mach-ep93xx/clock.c 4 * Clock control for Cirrus EP93xx chips. 5 * 6 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> 7 */ 8 9 #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/module.h> 15 #include <linux/string.h> 16 #include <linux/io.h> 17 #include <linux/spinlock.h> 18 #include <linux/clkdev.h> 19 #include <linux/clk-provider.h> 20 #include <linux/soc/cirrus/ep93xx.h> 21 22 #include "hardware.h" 23 24 #include <asm/div64.h> 25 26 #include "soc.h" 27 28 static DEFINE_SPINLOCK(clk_lock); 29 30 static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; 31 static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; 32 static char pclk_divisors[] = { 1, 2, 4, 8 }; 33 34 static char adc_divisors[] = { 16, 4 }; 35 static char sclk_divisors[] = { 2, 4 }; 36 static char lrclk_divisors[] = { 32, 64, 128 }; 37 38 static const char * const mux_parents[] = { 39 "xtali", 40 "pll1", 41 "pll2" 42 }; 43 44 /* 45 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS 46 */ 47 static unsigned long calc_pll_rate(unsigned long long rate, u32 config_word) 48 { 49 int i; 50 51 rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ 52 rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ 53 do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ 54 for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */ 55 rate >>= 1; 56 57 return (unsigned long)rate; 58 } 59 60 struct clk_psc { 61 struct clk_hw hw; 62 void __iomem *reg; 63 u8 bit_idx; 64 u32 mask; 65 u8 shift; 66 u8 width; 67 char *div; 68 u8 num_div; 69 spinlock_t *lock; 70 }; 71 72 #define to_clk_psc(_hw) container_of(_hw, struct clk_psc, hw) 73 74 static int ep93xx_clk_is_enabled(struct clk_hw *hw) 75 { 76 struct clk_psc *psc = to_clk_psc(hw); 77 u32 val = readl(psc->reg); 78 79 return (val & BIT(psc->bit_idx)) ? 1 : 0; 80 } 81 82 static int ep93xx_clk_enable(struct clk_hw *hw) 83 { 84 struct clk_psc *psc = to_clk_psc(hw); 85 unsigned long flags = 0; 86 u32 val; 87 88 if (psc->lock) 89 spin_lock_irqsave(psc->lock, flags); 90 91 val = __raw_readl(psc->reg); 92 val |= BIT(psc->bit_idx); 93 94 ep93xx_syscon_swlocked_write(val, psc->reg); 95 96 if (psc->lock) 97 spin_unlock_irqrestore(psc->lock, flags); 98 99 return 0; 100 } 101 102 static void ep93xx_clk_disable(struct clk_hw *hw) 103 { 104 struct clk_psc *psc = to_clk_psc(hw); 105 unsigned long flags = 0; 106 u32 val; 107 108 if (psc->lock) 109 spin_lock_irqsave(psc->lock, flags); 110 111 val = __raw_readl(psc->reg); 112 val &= ~BIT(psc->bit_idx); 113 114 ep93xx_syscon_swlocked_write(val, psc->reg); 115 116 if (psc->lock) 117 spin_unlock_irqrestore(psc->lock, flags); 118 } 119 120 static const struct clk_ops clk_ep93xx_gate_ops = { 121 .enable = ep93xx_clk_enable, 122 .disable = ep93xx_clk_disable, 123 .is_enabled = ep93xx_clk_is_enabled, 124 }; 125 126 static struct clk_hw *ep93xx_clk_register_gate(const char *name, 127 const char *parent_name, 128 void __iomem *reg, 129 u8 bit_idx) 130 { 131 struct clk_init_data init; 132 struct clk_psc *psc; 133 struct clk *clk; 134 135 psc = kzalloc(sizeof(*psc), GFP_KERNEL); 136 if (!psc) 137 return ERR_PTR(-ENOMEM); 138 139 init.name = name; 140 init.ops = &clk_ep93xx_gate_ops; 141 init.flags = CLK_SET_RATE_PARENT; 142 init.parent_names = (parent_name ? &parent_name : NULL); 143 init.num_parents = (parent_name ? 1 : 0); 144 145 psc->reg = reg; 146 psc->bit_idx = bit_idx; 147 psc->hw.init = &init; 148 psc->lock = &clk_lock; 149 150 clk = clk_register(NULL, &psc->hw); 151 if (IS_ERR(clk)) 152 kfree(psc); 153 154 return &psc->hw; 155 } 156 157 static u8 ep93xx_mux_get_parent(struct clk_hw *hw) 158 { 159 struct clk_psc *psc = to_clk_psc(hw); 160 u32 val = __raw_readl(psc->reg); 161 162 if (!(val & EP93XX_SYSCON_CLKDIV_ESEL)) 163 return 0; 164 165 if (!(val & EP93XX_SYSCON_CLKDIV_PSEL)) 166 return 1; 167 168 return 2; 169 } 170 171 static int ep93xx_mux_set_parent_lock(struct clk_hw *hw, u8 index) 172 { 173 struct clk_psc *psc = to_clk_psc(hw); 174 unsigned long flags = 0; 175 u32 val; 176 177 if (index >= ARRAY_SIZE(mux_parents)) 178 return -EINVAL; 179 180 if (psc->lock) 181 spin_lock_irqsave(psc->lock, flags); 182 183 val = __raw_readl(psc->reg); 184 val &= ~(EP93XX_SYSCON_CLKDIV_ESEL | EP93XX_SYSCON_CLKDIV_PSEL); 185 186 187 if (index != 0) { 188 val |= EP93XX_SYSCON_CLKDIV_ESEL; 189 val |= (index - 1) ? EP93XX_SYSCON_CLKDIV_PSEL : 0; 190 } 191 192 ep93xx_syscon_swlocked_write(val, psc->reg); 193 194 if (psc->lock) 195 spin_unlock_irqrestore(psc->lock, flags); 196 197 return 0; 198 } 199 200 static bool is_best(unsigned long rate, unsigned long now, 201 unsigned long best) 202 { 203 return abs(rate - now) < abs(rate - best); 204 } 205 206 static int ep93xx_mux_determine_rate(struct clk_hw *hw, 207 struct clk_rate_request *req) 208 { 209 unsigned long rate = req->rate; 210 struct clk *best_parent = 0; 211 unsigned long __parent_rate; 212 unsigned long best_rate = 0, actual_rate, mclk_rate; 213 unsigned long best_parent_rate; 214 int __div = 0, __pdiv = 0; 215 int i; 216 217 /* 218 * Try the two pll's and the external clock 219 * Because the valid predividers are 2, 2.5 and 3, we multiply 220 * all the clocks by 2 to avoid floating point math. 221 * 222 * This is based on the algorithm in the ep93xx raster guide: 223 * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf 224 * 225 */ 226 for (i = 0; i < ARRAY_SIZE(mux_parents); i++) { 227 struct clk *parent = clk_get_sys(mux_parents[i], NULL); 228 229 __parent_rate = clk_get_rate(parent); 230 mclk_rate = __parent_rate * 2; 231 232 /* Try each predivider value */ 233 for (__pdiv = 4; __pdiv <= 6; __pdiv++) { 234 __div = mclk_rate / (rate * __pdiv); 235 if (__div < 2 || __div > 127) 236 continue; 237 238 actual_rate = mclk_rate / (__pdiv * __div); 239 if (is_best(rate, actual_rate, best_rate)) { 240 best_rate = actual_rate; 241 best_parent_rate = __parent_rate; 242 best_parent = parent; 243 } 244 } 245 } 246 247 if (!best_parent) 248 return -EINVAL; 249 250 req->best_parent_rate = best_parent_rate; 251 req->best_parent_hw = __clk_get_hw(best_parent); 252 req->rate = best_rate; 253 254 return 0; 255 } 256 257 static unsigned long ep93xx_ddiv_recalc_rate(struct clk_hw *hw, 258 unsigned long parent_rate) 259 { 260 struct clk_psc *psc = to_clk_psc(hw); 261 unsigned long rate = 0; 262 u32 val = __raw_readl(psc->reg); 263 int __pdiv = ((val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & 0x03); 264 int __div = val & 0x7f; 265 266 if (__div > 0) 267 rate = (parent_rate * 2) / ((__pdiv + 3) * __div); 268 269 return rate; 270 } 271 272 static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate, 273 unsigned long parent_rate) 274 { 275 struct clk_psc *psc = to_clk_psc(hw); 276 int pdiv = 0, div = 0; 277 unsigned long best_rate = 0, actual_rate, mclk_rate; 278 int __div = 0, __pdiv = 0; 279 u32 val; 280 281 mclk_rate = parent_rate * 2; 282 283 for (__pdiv = 4; __pdiv <= 6; __pdiv++) { 284 __div = mclk_rate / (rate * __pdiv); 285 if (__div < 2 || __div > 127) 286 continue; 287 288 actual_rate = mclk_rate / (__pdiv * __div); 289 if (is_best(rate, actual_rate, best_rate)) { 290 pdiv = __pdiv - 3; 291 div = __div; 292 best_rate = actual_rate; 293 } 294 } 295 296 if (!best_rate) 297 return -EINVAL; 298 299 val = __raw_readl(psc->reg); 300 301 /* Clear old dividers */ 302 val &= ~0x37f; 303 304 /* Set the new pdiv and div bits for the new clock rate */ 305 val |= (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div; 306 ep93xx_syscon_swlocked_write(val, psc->reg); 307 308 return 0; 309 } 310 311 static const struct clk_ops clk_ddiv_ops = { 312 .enable = ep93xx_clk_enable, 313 .disable = ep93xx_clk_disable, 314 .is_enabled = ep93xx_clk_is_enabled, 315 .get_parent = ep93xx_mux_get_parent, 316 .set_parent = ep93xx_mux_set_parent_lock, 317 .determine_rate = ep93xx_mux_determine_rate, 318 .recalc_rate = ep93xx_ddiv_recalc_rate, 319 .set_rate = ep93xx_ddiv_set_rate, 320 }; 321 322 static struct clk_hw *clk_hw_register_ddiv(const char *name, 323 void __iomem *reg, 324 u8 bit_idx) 325 { 326 struct clk_init_data init; 327 struct clk_psc *psc; 328 struct clk *clk; 329 330 psc = kzalloc(sizeof(*psc), GFP_KERNEL); 331 if (!psc) 332 return ERR_PTR(-ENOMEM); 333 334 init.name = name; 335 init.ops = &clk_ddiv_ops; 336 init.flags = 0; 337 init.parent_names = mux_parents; 338 init.num_parents = ARRAY_SIZE(mux_parents); 339 340 psc->reg = reg; 341 psc->bit_idx = bit_idx; 342 psc->lock = &clk_lock; 343 psc->hw.init = &init; 344 345 clk = clk_register(NULL, &psc->hw); 346 if (IS_ERR(clk)) 347 kfree(psc); 348 349 return &psc->hw; 350 } 351 352 static unsigned long ep93xx_div_recalc_rate(struct clk_hw *hw, 353 unsigned long parent_rate) 354 { 355 struct clk_psc *psc = to_clk_psc(hw); 356 u32 val = __raw_readl(psc->reg); 357 u8 index = (val & psc->mask) >> psc->shift; 358 359 if (index > psc->num_div) 360 return 0; 361 362 return DIV_ROUND_UP_ULL(parent_rate, psc->div[index]); 363 } 364 365 static long ep93xx_div_round_rate(struct clk_hw *hw, unsigned long rate, 366 unsigned long *parent_rate) 367 { 368 struct clk_psc *psc = to_clk_psc(hw); 369 unsigned long best = 0, now, maxdiv; 370 int i; 371 372 maxdiv = psc->div[psc->num_div - 1]; 373 374 for (i = 0; i < psc->num_div; i++) { 375 if ((rate * psc->div[i]) == *parent_rate) 376 return DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]); 377 378 now = DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]); 379 380 if (is_best(rate, now, best)) 381 best = now; 382 } 383 384 if (!best) 385 best = DIV_ROUND_UP_ULL(*parent_rate, maxdiv); 386 387 return best; 388 } 389 390 static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate, 391 unsigned long parent_rate) 392 { 393 struct clk_psc *psc = to_clk_psc(hw); 394 u32 val = __raw_readl(psc->reg) & ~psc->mask; 395 int i; 396 397 for (i = 0; i < psc->num_div; i++) 398 if (rate == parent_rate / psc->div[i]) { 399 val |= i << psc->shift; 400 break; 401 } 402 403 if (i == psc->num_div) 404 return -EINVAL; 405 406 ep93xx_syscon_swlocked_write(val, psc->reg); 407 408 return 0; 409 } 410 411 static const struct clk_ops ep93xx_div_ops = { 412 .enable = ep93xx_clk_enable, 413 .disable = ep93xx_clk_disable, 414 .is_enabled = ep93xx_clk_is_enabled, 415 .recalc_rate = ep93xx_div_recalc_rate, 416 .round_rate = ep93xx_div_round_rate, 417 .set_rate = ep93xx_div_set_rate, 418 }; 419 420 static struct clk_hw *clk_hw_register_div(const char *name, 421 const char *parent_name, 422 void __iomem *reg, 423 u8 enable_bit, 424 u8 shift, 425 u8 width, 426 char *clk_divisors, 427 u8 num_div) 428 { 429 struct clk_init_data init; 430 struct clk_psc *psc; 431 struct clk *clk; 432 433 psc = kzalloc(sizeof(*psc), GFP_KERNEL); 434 if (!psc) 435 return ERR_PTR(-ENOMEM); 436 437 init.name = name; 438 init.ops = &ep93xx_div_ops; 439 init.flags = 0; 440 init.parent_names = (parent_name ? &parent_name : NULL); 441 init.num_parents = 1; 442 443 psc->reg = reg; 444 psc->bit_idx = enable_bit; 445 psc->mask = GENMASK(shift + width - 1, shift); 446 psc->shift = shift; 447 psc->div = clk_divisors; 448 psc->num_div = num_div; 449 psc->lock = &clk_lock; 450 psc->hw.init = &init; 451 452 clk = clk_register(NULL, &psc->hw); 453 if (IS_ERR(clk)) 454 kfree(psc); 455 456 return &psc->hw; 457 } 458 459 struct ep93xx_gate { 460 unsigned int bit; 461 const char *dev_id; 462 const char *con_id; 463 }; 464 465 static struct ep93xx_gate ep93xx_uarts[] = { 466 {EP93XX_SYSCON_DEVCFG_U1EN, "apb:uart1", NULL}, 467 {EP93XX_SYSCON_DEVCFG_U2EN, "apb:uart2", NULL}, 468 {EP93XX_SYSCON_DEVCFG_U3EN, "apb:uart3", NULL}, 469 }; 470 471 static void __init ep93xx_uart_clock_init(void) 472 { 473 unsigned int i; 474 struct clk_hw *hw; 475 u32 value; 476 unsigned int clk_uart_div; 477 478 value = __raw_readl(EP93XX_SYSCON_PWRCNT); 479 if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD) 480 clk_uart_div = 1; 481 else 482 clk_uart_div = 2; 483 484 hw = clk_hw_register_fixed_factor(NULL, "uart", "xtali", 0, 1, clk_uart_div); 485 486 /* parenting uart gate clocks to uart clock */ 487 for (i = 0; i < ARRAY_SIZE(ep93xx_uarts); i++) { 488 hw = ep93xx_clk_register_gate(ep93xx_uarts[i].dev_id, 489 "uart", 490 EP93XX_SYSCON_DEVCFG, 491 ep93xx_uarts[i].bit); 492 493 clk_hw_register_clkdev(hw, NULL, ep93xx_uarts[i].dev_id); 494 } 495 } 496 497 static struct ep93xx_gate ep93xx_dmas[] = { 498 {EP93XX_SYSCON_PWRCNT_DMA_M2P0, NULL, "m2p0"}, 499 {EP93XX_SYSCON_PWRCNT_DMA_M2P1, NULL, "m2p1"}, 500 {EP93XX_SYSCON_PWRCNT_DMA_M2P2, NULL, "m2p2"}, 501 {EP93XX_SYSCON_PWRCNT_DMA_M2P3, NULL, "m2p3"}, 502 {EP93XX_SYSCON_PWRCNT_DMA_M2P4, NULL, "m2p4"}, 503 {EP93XX_SYSCON_PWRCNT_DMA_M2P5, NULL, "m2p5"}, 504 {EP93XX_SYSCON_PWRCNT_DMA_M2P6, NULL, "m2p6"}, 505 {EP93XX_SYSCON_PWRCNT_DMA_M2P7, NULL, "m2p7"}, 506 {EP93XX_SYSCON_PWRCNT_DMA_M2P8, NULL, "m2p8"}, 507 {EP93XX_SYSCON_PWRCNT_DMA_M2P9, NULL, "m2p9"}, 508 {EP93XX_SYSCON_PWRCNT_DMA_M2M0, NULL, "m2m0"}, 509 {EP93XX_SYSCON_PWRCNT_DMA_M2M1, NULL, "m2m1"}, 510 }; 511 512 static void __init ep93xx_dma_clock_init(void) 513 { 514 unsigned int i; 515 struct clk_hw *hw; 516 int ret; 517 518 for (i = 0; i < ARRAY_SIZE(ep93xx_dmas); i++) { 519 hw = clk_hw_register_gate(NULL, ep93xx_dmas[i].con_id, 520 "hclk", 0, 521 EP93XX_SYSCON_PWRCNT, 522 ep93xx_dmas[i].bit, 523 0, 524 &clk_lock); 525 526 ret = clk_hw_register_clkdev(hw, ep93xx_dmas[i].con_id, NULL); 527 if (ret) 528 pr_err("%s: failed to register lookup %s\n", 529 __func__, ep93xx_dmas[i].con_id); 530 } 531 } 532 533 static int __init ep93xx_clock_init(void) 534 { 535 u32 value; 536 struct clk_hw *hw; 537 unsigned long clk_pll1_rate; 538 unsigned long clk_f_rate; 539 unsigned long clk_h_rate; 540 unsigned long clk_p_rate; 541 unsigned long clk_pll2_rate; 542 unsigned int clk_f_div; 543 unsigned int clk_h_div; 544 unsigned int clk_p_div; 545 unsigned int clk_usb_div; 546 unsigned long clk_spi_div; 547 548 hw = clk_hw_register_fixed_rate(NULL, "xtali", NULL, 0, EP93XX_EXT_CLK_RATE); 549 clk_hw_register_clkdev(hw, NULL, "xtali"); 550 551 /* Determine the bootloader configured pll1 rate */ 552 value = __raw_readl(EP93XX_SYSCON_CLKSET1); 553 if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1)) 554 clk_pll1_rate = EP93XX_EXT_CLK_RATE; 555 else 556 clk_pll1_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value); 557 558 hw = clk_hw_register_fixed_rate(NULL, "pll1", "xtali", 0, clk_pll1_rate); 559 clk_hw_register_clkdev(hw, NULL, "pll1"); 560 561 /* Initialize the pll1 derived clocks */ 562 clk_f_div = fclk_divisors[(value >> 25) & 0x7]; 563 clk_h_div = hclk_divisors[(value >> 20) & 0x7]; 564 clk_p_div = pclk_divisors[(value >> 18) & 0x3]; 565 566 hw = clk_hw_register_fixed_factor(NULL, "fclk", "pll1", 0, 1, clk_f_div); 567 clk_f_rate = clk_get_rate(hw->clk); 568 hw = clk_hw_register_fixed_factor(NULL, "hclk", "pll1", 0, 1, clk_h_div); 569 clk_h_rate = clk_get_rate(hw->clk); 570 hw = clk_hw_register_fixed_factor(NULL, "pclk", "hclk", 0, 1, clk_p_div); 571 clk_p_rate = clk_get_rate(hw->clk); 572 573 clk_hw_register_clkdev(hw, "apb_pclk", NULL); 574 575 ep93xx_dma_clock_init(); 576 577 /* Determine the bootloader configured pll2 rate */ 578 value = __raw_readl(EP93XX_SYSCON_CLKSET2); 579 if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2)) 580 clk_pll2_rate = EP93XX_EXT_CLK_RATE; 581 else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN) 582 clk_pll2_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value); 583 else 584 clk_pll2_rate = 0; 585 586 hw = clk_hw_register_fixed_rate(NULL, "pll2", "xtali", 0, clk_pll2_rate); 587 clk_hw_register_clkdev(hw, NULL, "pll2"); 588 589 /* Initialize the pll2 derived clocks */ 590 /* 591 * These four bits set the divide ratio between the PLL2 592 * output and the USB clock. 593 * 0000 - Divide by 1 594 * 0001 - Divide by 2 595 * 0010 - Divide by 3 596 * 0011 - Divide by 4 597 * 0100 - Divide by 5 598 * 0101 - Divide by 6 599 * 0110 - Divide by 7 600 * 0111 - Divide by 8 601 * 1000 - Divide by 9 602 * 1001 - Divide by 10 603 * 1010 - Divide by 11 604 * 1011 - Divide by 12 605 * 1100 - Divide by 13 606 * 1101 - Divide by 14 607 * 1110 - Divide by 15 608 * 1111 - Divide by 1 609 * On power-on-reset these bits are reset to 0000b. 610 */ 611 clk_usb_div = (((value >> 28) & 0xf) + 1); 612 hw = clk_hw_register_fixed_factor(NULL, "usb_clk", "pll2", 0, 1, clk_usb_div); 613 hw = clk_hw_register_gate(NULL, "ohci-platform", 614 "usb_clk", 0, 615 EP93XX_SYSCON_PWRCNT, 616 EP93XX_SYSCON_PWRCNT_USH_EN, 617 0, 618 &clk_lock); 619 clk_hw_register_clkdev(hw, NULL, "ohci-platform"); 620 621 /* 622 * EP93xx SSP clock rate was doubled in version E2. For more information 623 * see: 624 * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf 625 */ 626 clk_spi_div = 1; 627 if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2) 628 clk_spi_div = 2; 629 hw = clk_hw_register_fixed_factor(NULL, "ep93xx-spi.0", "xtali", 0, 1, clk_spi_div); 630 clk_hw_register_clkdev(hw, NULL, "ep93xx-spi.0"); 631 632 /* pwm clock */ 633 hw = clk_hw_register_fixed_factor(NULL, "pwm_clk", "xtali", 0, 1, 1); 634 clk_hw_register_clkdev(hw, "pwm_clk", NULL); 635 636 pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", 637 clk_pll1_rate / 1000000, clk_pll2_rate / 1000000); 638 pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", 639 clk_f_rate / 1000000, clk_h_rate / 1000000, 640 clk_p_rate / 1000000); 641 642 ep93xx_uart_clock_init(); 643 644 /* touchscreen/adc clock */ 645 hw = clk_hw_register_div("ep93xx-adc", 646 "xtali", 647 EP93XX_SYSCON_KEYTCHCLKDIV, 648 EP93XX_SYSCON_KEYTCHCLKDIV_TSEN, 649 EP93XX_SYSCON_KEYTCHCLKDIV_ADIV, 650 1, 651 adc_divisors, 652 ARRAY_SIZE(adc_divisors)); 653 654 clk_hw_register_clkdev(hw, NULL, "ep93xx-adc"); 655 656 /* keypad clock */ 657 hw = clk_hw_register_div("ep93xx-keypad", 658 "xtali", 659 EP93XX_SYSCON_KEYTCHCLKDIV, 660 EP93XX_SYSCON_KEYTCHCLKDIV_KEN, 661 EP93XX_SYSCON_KEYTCHCLKDIV_KDIV, 662 1, 663 adc_divisors, 664 ARRAY_SIZE(adc_divisors)); 665 666 clk_hw_register_clkdev(hw, NULL, "ep93xx-keypad"); 667 668 /* On reset PDIV and VDIV is set to zero, while PDIV zero 669 * means clock disable, VDIV shouldn't be zero. 670 * So i set both dividers to minimum. 671 */ 672 /* ENA - Enable CLK divider. */ 673 /* PDIV - 00 - Disable clock */ 674 /* VDIV - at least 2 */ 675 /* Check and enable video clk registers */ 676 value = __raw_readl(EP93XX_SYSCON_VIDCLKDIV); 677 value |= (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; 678 ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_VIDCLKDIV); 679 680 /* check and enable i2s clk registers */ 681 value = __raw_readl(EP93XX_SYSCON_I2SCLKDIV); 682 value |= (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; 683 ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_I2SCLKDIV); 684 685 /* video clk */ 686 hw = clk_hw_register_ddiv("ep93xx-fb", 687 EP93XX_SYSCON_VIDCLKDIV, 688 EP93XX_SYSCON_CLKDIV_ENABLE); 689 690 clk_hw_register_clkdev(hw, NULL, "ep93xx-fb"); 691 692 /* i2s clk */ 693 hw = clk_hw_register_ddiv("mclk", 694 EP93XX_SYSCON_I2SCLKDIV, 695 EP93XX_SYSCON_CLKDIV_ENABLE); 696 697 clk_hw_register_clkdev(hw, "mclk", "ep93xx-i2s"); 698 699 /* i2s sclk */ 700 #define EP93XX_I2SCLKDIV_SDIV_SHIFT 16 701 #define EP93XX_I2SCLKDIV_SDIV_WIDTH 1 702 hw = clk_hw_register_div("sclk", 703 "mclk", 704 EP93XX_SYSCON_I2SCLKDIV, 705 EP93XX_SYSCON_I2SCLKDIV_SENA, 706 EP93XX_I2SCLKDIV_SDIV_SHIFT, 707 EP93XX_I2SCLKDIV_SDIV_WIDTH, 708 sclk_divisors, 709 ARRAY_SIZE(sclk_divisors)); 710 711 clk_hw_register_clkdev(hw, "sclk", "ep93xx-i2s"); 712 713 /* i2s lrclk */ 714 #define EP93XX_I2SCLKDIV_LRDIV32_SHIFT 17 715 #define EP93XX_I2SCLKDIV_LRDIV32_WIDTH 3 716 hw = clk_hw_register_div("lrclk", 717 "sclk", 718 EP93XX_SYSCON_I2SCLKDIV, 719 EP93XX_SYSCON_I2SCLKDIV_SENA, 720 EP93XX_I2SCLKDIV_LRDIV32_SHIFT, 721 EP93XX_I2SCLKDIV_LRDIV32_WIDTH, 722 lrclk_divisors, 723 ARRAY_SIZE(lrclk_divisors)); 724 725 clk_hw_register_clkdev(hw, "lrclk", "ep93xx-i2s"); 726 727 return 0; 728 } 729 postcore_initcall(ep93xx_clock_init); 730