1 /* 2 * arch/arm/mach-ep93xx/clock.c 3 * Clock control for Cirrus EP93xx chips. 4 * 5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or (at 10 * your option) any later version. 11 */ 12 13 #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt 14 15 #include <linux/kernel.h> 16 #include <linux/clk.h> 17 #include <linux/err.h> 18 #include <linux/module.h> 19 #include <linux/string.h> 20 #include <linux/io.h> 21 #include <linux/spinlock.h> 22 #include <linux/clkdev.h> 23 #include <linux/soc/cirrus/ep93xx.h> 24 25 #include "hardware.h" 26 27 #include <asm/div64.h> 28 29 #include "soc.h" 30 31 struct clk { 32 struct clk *parent; 33 unsigned long rate; 34 int users; 35 int sw_locked; 36 void __iomem *enable_reg; 37 u32 enable_mask; 38 39 unsigned long (*get_rate)(struct clk *clk); 40 int (*set_rate)(struct clk *clk, unsigned long rate); 41 }; 42 43 44 static unsigned long get_uart_rate(struct clk *clk); 45 46 static int set_keytchclk_rate(struct clk *clk, unsigned long rate); 47 static int set_div_rate(struct clk *clk, unsigned long rate); 48 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate); 49 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate); 50 51 static struct clk clk_xtali = { 52 .rate = EP93XX_EXT_CLK_RATE, 53 }; 54 static struct clk clk_uart1 = { 55 .parent = &clk_xtali, 56 .sw_locked = 1, 57 .enable_reg = EP93XX_SYSCON_DEVCFG, 58 .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN, 59 .get_rate = get_uart_rate, 60 }; 61 static struct clk clk_uart2 = { 62 .parent = &clk_xtali, 63 .sw_locked = 1, 64 .enable_reg = EP93XX_SYSCON_DEVCFG, 65 .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN, 66 .get_rate = get_uart_rate, 67 }; 68 static struct clk clk_uart3 = { 69 .parent = &clk_xtali, 70 .sw_locked = 1, 71 .enable_reg = EP93XX_SYSCON_DEVCFG, 72 .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN, 73 .get_rate = get_uart_rate, 74 }; 75 static struct clk clk_pll1 = { 76 .parent = &clk_xtali, 77 }; 78 static struct clk clk_f = { 79 .parent = &clk_pll1, 80 }; 81 static struct clk clk_h = { 82 .parent = &clk_pll1, 83 }; 84 static struct clk clk_p = { 85 .parent = &clk_pll1, 86 }; 87 static struct clk clk_pll2 = { 88 .parent = &clk_xtali, 89 }; 90 static struct clk clk_usb_host = { 91 .parent = &clk_pll2, 92 .enable_reg = EP93XX_SYSCON_PWRCNT, 93 .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN, 94 }; 95 static struct clk clk_keypad = { 96 .parent = &clk_xtali, 97 .sw_locked = 1, 98 .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV, 99 .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN, 100 .set_rate = set_keytchclk_rate, 101 }; 102 static struct clk clk_adc = { 103 .parent = &clk_xtali, 104 .sw_locked = 1, 105 .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV, 106 .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_TSEN, 107 .set_rate = set_keytchclk_rate, 108 }; 109 static struct clk clk_spi = { 110 .parent = &clk_xtali, 111 .rate = EP93XX_EXT_CLK_RATE, 112 }; 113 static struct clk clk_pwm = { 114 .parent = &clk_xtali, 115 .rate = EP93XX_EXT_CLK_RATE, 116 }; 117 118 static struct clk clk_video = { 119 .sw_locked = 1, 120 .enable_reg = EP93XX_SYSCON_VIDCLKDIV, 121 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE, 122 .set_rate = set_div_rate, 123 }; 124 125 static struct clk clk_i2s_mclk = { 126 .sw_locked = 1, 127 .enable_reg = EP93XX_SYSCON_I2SCLKDIV, 128 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE, 129 .set_rate = set_div_rate, 130 }; 131 132 static struct clk clk_i2s_sclk = { 133 .sw_locked = 1, 134 .parent = &clk_i2s_mclk, 135 .enable_reg = EP93XX_SYSCON_I2SCLKDIV, 136 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA, 137 .set_rate = set_i2s_sclk_rate, 138 }; 139 140 static struct clk clk_i2s_lrclk = { 141 .sw_locked = 1, 142 .parent = &clk_i2s_sclk, 143 .enable_reg = EP93XX_SYSCON_I2SCLKDIV, 144 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA, 145 .set_rate = set_i2s_lrclk_rate, 146 }; 147 148 /* DMA Clocks */ 149 static struct clk clk_m2p0 = { 150 .parent = &clk_h, 151 .enable_reg = EP93XX_SYSCON_PWRCNT, 152 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0, 153 }; 154 static struct clk clk_m2p1 = { 155 .parent = &clk_h, 156 .enable_reg = EP93XX_SYSCON_PWRCNT, 157 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1, 158 }; 159 static struct clk clk_m2p2 = { 160 .parent = &clk_h, 161 .enable_reg = EP93XX_SYSCON_PWRCNT, 162 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2, 163 }; 164 static struct clk clk_m2p3 = { 165 .parent = &clk_h, 166 .enable_reg = EP93XX_SYSCON_PWRCNT, 167 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3, 168 }; 169 static struct clk clk_m2p4 = { 170 .parent = &clk_h, 171 .enable_reg = EP93XX_SYSCON_PWRCNT, 172 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4, 173 }; 174 static struct clk clk_m2p5 = { 175 .parent = &clk_h, 176 .enable_reg = EP93XX_SYSCON_PWRCNT, 177 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5, 178 }; 179 static struct clk clk_m2p6 = { 180 .parent = &clk_h, 181 .enable_reg = EP93XX_SYSCON_PWRCNT, 182 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6, 183 }; 184 static struct clk clk_m2p7 = { 185 .parent = &clk_h, 186 .enable_reg = EP93XX_SYSCON_PWRCNT, 187 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7, 188 }; 189 static struct clk clk_m2p8 = { 190 .parent = &clk_h, 191 .enable_reg = EP93XX_SYSCON_PWRCNT, 192 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8, 193 }; 194 static struct clk clk_m2p9 = { 195 .parent = &clk_h, 196 .enable_reg = EP93XX_SYSCON_PWRCNT, 197 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9, 198 }; 199 static struct clk clk_m2m0 = { 200 .parent = &clk_h, 201 .enable_reg = EP93XX_SYSCON_PWRCNT, 202 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0, 203 }; 204 static struct clk clk_m2m1 = { 205 .parent = &clk_h, 206 .enable_reg = EP93XX_SYSCON_PWRCNT, 207 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1, 208 }; 209 210 #define INIT_CK(dev,con,ck) \ 211 { .dev_id = dev, .con_id = con, .clk = ck } 212 213 static struct clk_lookup clocks[] = { 214 INIT_CK(NULL, "xtali", &clk_xtali), 215 INIT_CK("apb:uart1", NULL, &clk_uart1), 216 INIT_CK("apb:uart2", NULL, &clk_uart2), 217 INIT_CK("apb:uart3", NULL, &clk_uart3), 218 INIT_CK(NULL, "pll1", &clk_pll1), 219 INIT_CK(NULL, "fclk", &clk_f), 220 INIT_CK(NULL, "hclk", &clk_h), 221 INIT_CK(NULL, "apb_pclk", &clk_p), 222 INIT_CK(NULL, "pll2", &clk_pll2), 223 INIT_CK("ohci-platform", NULL, &clk_usb_host), 224 INIT_CK("ep93xx-keypad", NULL, &clk_keypad), 225 INIT_CK("ep93xx-adc", NULL, &clk_adc), 226 INIT_CK("ep93xx-fb", NULL, &clk_video), 227 INIT_CK("ep93xx-spi.0", NULL, &clk_spi), 228 INIT_CK("ep93xx-i2s", "mclk", &clk_i2s_mclk), 229 INIT_CK("ep93xx-i2s", "sclk", &clk_i2s_sclk), 230 INIT_CK("ep93xx-i2s", "lrclk", &clk_i2s_lrclk), 231 INIT_CK(NULL, "pwm_clk", &clk_pwm), 232 INIT_CK(NULL, "m2p0", &clk_m2p0), 233 INIT_CK(NULL, "m2p1", &clk_m2p1), 234 INIT_CK(NULL, "m2p2", &clk_m2p2), 235 INIT_CK(NULL, "m2p3", &clk_m2p3), 236 INIT_CK(NULL, "m2p4", &clk_m2p4), 237 INIT_CK(NULL, "m2p5", &clk_m2p5), 238 INIT_CK(NULL, "m2p6", &clk_m2p6), 239 INIT_CK(NULL, "m2p7", &clk_m2p7), 240 INIT_CK(NULL, "m2p8", &clk_m2p8), 241 INIT_CK(NULL, "m2p9", &clk_m2p9), 242 INIT_CK(NULL, "m2m0", &clk_m2m0), 243 INIT_CK(NULL, "m2m1", &clk_m2m1), 244 }; 245 246 static DEFINE_SPINLOCK(clk_lock); 247 248 static void __clk_enable(struct clk *clk) 249 { 250 if (!clk->users++) { 251 if (clk->parent) 252 __clk_enable(clk->parent); 253 254 if (clk->enable_reg) { 255 u32 v; 256 257 v = __raw_readl(clk->enable_reg); 258 v |= clk->enable_mask; 259 if (clk->sw_locked) 260 ep93xx_syscon_swlocked_write(v, clk->enable_reg); 261 else 262 __raw_writel(v, clk->enable_reg); 263 } 264 } 265 } 266 267 int clk_enable(struct clk *clk) 268 { 269 unsigned long flags; 270 271 if (!clk) 272 return -EINVAL; 273 274 spin_lock_irqsave(&clk_lock, flags); 275 __clk_enable(clk); 276 spin_unlock_irqrestore(&clk_lock, flags); 277 278 return 0; 279 } 280 EXPORT_SYMBOL(clk_enable); 281 282 static void __clk_disable(struct clk *clk) 283 { 284 if (!--clk->users) { 285 if (clk->enable_reg) { 286 u32 v; 287 288 v = __raw_readl(clk->enable_reg); 289 v &= ~clk->enable_mask; 290 if (clk->sw_locked) 291 ep93xx_syscon_swlocked_write(v, clk->enable_reg); 292 else 293 __raw_writel(v, clk->enable_reg); 294 } 295 296 if (clk->parent) 297 __clk_disable(clk->parent); 298 } 299 } 300 301 void clk_disable(struct clk *clk) 302 { 303 unsigned long flags; 304 305 if (!clk) 306 return; 307 308 spin_lock_irqsave(&clk_lock, flags); 309 __clk_disable(clk); 310 spin_unlock_irqrestore(&clk_lock, flags); 311 } 312 EXPORT_SYMBOL(clk_disable); 313 314 static unsigned long get_uart_rate(struct clk *clk) 315 { 316 unsigned long rate = clk_get_rate(clk->parent); 317 u32 value; 318 319 value = __raw_readl(EP93XX_SYSCON_PWRCNT); 320 if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD) 321 return rate; 322 else 323 return rate / 2; 324 } 325 326 unsigned long clk_get_rate(struct clk *clk) 327 { 328 if (clk->get_rate) 329 return clk->get_rate(clk); 330 331 return clk->rate; 332 } 333 EXPORT_SYMBOL(clk_get_rate); 334 335 static int set_keytchclk_rate(struct clk *clk, unsigned long rate) 336 { 337 u32 val; 338 u32 div_bit; 339 340 val = __raw_readl(clk->enable_reg); 341 342 /* 343 * The Key Matrix and ADC clocks are configured using the same 344 * System Controller register. The clock used will be either 345 * 1/4 or 1/16 the external clock rate depending on the 346 * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 347 * bit being set or cleared. 348 */ 349 div_bit = clk->enable_mask >> 15; 350 351 if (rate == EP93XX_KEYTCHCLK_DIV4) 352 val |= div_bit; 353 else if (rate == EP93XX_KEYTCHCLK_DIV16) 354 val &= ~div_bit; 355 else 356 return -EINVAL; 357 358 ep93xx_syscon_swlocked_write(val, clk->enable_reg); 359 clk->rate = rate; 360 return 0; 361 } 362 363 static int calc_clk_div(struct clk *clk, unsigned long rate, 364 int *psel, int *esel, int *pdiv, int *div) 365 { 366 struct clk *mclk; 367 unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1; 368 int i, found = 0, __div = 0, __pdiv = 0; 369 370 /* Don't exceed the maximum rate */ 371 max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4); 372 rate = min(rate, max_rate); 373 374 /* 375 * Try the two pll's and the external clock 376 * Because the valid predividers are 2, 2.5 and 3, we multiply 377 * all the clocks by 2 to avoid floating point math. 378 * 379 * This is based on the algorithm in the ep93xx raster guide: 380 * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf 381 * 382 */ 383 for (i = 0; i < 3; i++) { 384 if (i == 0) 385 mclk = &clk_xtali; 386 else if (i == 1) 387 mclk = &clk_pll1; 388 else 389 mclk = &clk_pll2; 390 mclk_rate = mclk->rate * 2; 391 392 /* Try each predivider value */ 393 for (__pdiv = 4; __pdiv <= 6; __pdiv++) { 394 __div = mclk_rate / (rate * __pdiv); 395 if (__div < 2 || __div > 127) 396 continue; 397 398 actual_rate = mclk_rate / (__pdiv * __div); 399 400 if (!found || abs(actual_rate - rate) < rate_err) { 401 *pdiv = __pdiv - 3; 402 *div = __div; 403 *psel = (i == 2); 404 *esel = (i != 0); 405 clk->parent = mclk; 406 clk->rate = actual_rate; 407 rate_err = abs(actual_rate - rate); 408 found = 1; 409 } 410 } 411 } 412 413 if (!found) 414 return -EINVAL; 415 416 return 0; 417 } 418 419 static int set_div_rate(struct clk *clk, unsigned long rate) 420 { 421 int err, psel = 0, esel = 0, pdiv = 0, div = 0; 422 u32 val; 423 424 err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div); 425 if (err) 426 return err; 427 428 /* Clear the esel, psel, pdiv and div bits */ 429 val = __raw_readl(clk->enable_reg); 430 val &= ~0x7fff; 431 432 /* Set the new esel, psel, pdiv and div bits for the new clock rate */ 433 val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) | 434 (psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) | 435 (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div; 436 ep93xx_syscon_swlocked_write(val, clk->enable_reg); 437 return 0; 438 } 439 440 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate) 441 { 442 unsigned val = __raw_readl(clk->enable_reg); 443 444 if (rate == clk_i2s_mclk.rate / 2) 445 ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV, 446 clk->enable_reg); 447 else if (rate == clk_i2s_mclk.rate / 4) 448 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_SDIV, 449 clk->enable_reg); 450 else 451 return -EINVAL; 452 453 clk_i2s_sclk.rate = rate; 454 return 0; 455 } 456 457 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate) 458 { 459 unsigned val = __raw_readl(clk->enable_reg) & 460 ~EP93XX_I2SCLKDIV_LRDIV_MASK; 461 462 if (rate == clk_i2s_sclk.rate / 32) 463 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV32, 464 clk->enable_reg); 465 else if (rate == clk_i2s_sclk.rate / 64) 466 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV64, 467 clk->enable_reg); 468 else if (rate == clk_i2s_sclk.rate / 128) 469 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV128, 470 clk->enable_reg); 471 else 472 return -EINVAL; 473 474 clk_i2s_lrclk.rate = rate; 475 return 0; 476 } 477 478 int clk_set_rate(struct clk *clk, unsigned long rate) 479 { 480 if (clk->set_rate) 481 return clk->set_rate(clk, rate); 482 483 return -EINVAL; 484 } 485 EXPORT_SYMBOL(clk_set_rate); 486 487 long clk_round_rate(struct clk *clk, unsigned long rate) 488 { 489 WARN_ON(clk); 490 return 0; 491 } 492 EXPORT_SYMBOL(clk_round_rate); 493 494 int clk_set_parent(struct clk *clk, struct clk *parent) 495 { 496 WARN_ON(clk); 497 return 0; 498 } 499 EXPORT_SYMBOL(clk_set_parent); 500 501 struct clk *clk_get_parent(struct clk *clk) 502 { 503 return clk->parent; 504 } 505 EXPORT_SYMBOL(clk_get_parent); 506 507 508 static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; 509 static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; 510 static char pclk_divisors[] = { 1, 2, 4, 8 }; 511 512 /* 513 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS 514 */ 515 static unsigned long calc_pll_rate(u32 config_word) 516 { 517 unsigned long long rate; 518 int i; 519 520 rate = clk_xtali.rate; 521 rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ 522 rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ 523 do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ 524 for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */ 525 rate >>= 1; 526 527 return (unsigned long)rate; 528 } 529 530 static void __init ep93xx_dma_clock_init(void) 531 { 532 clk_m2p0.rate = clk_h.rate; 533 clk_m2p1.rate = clk_h.rate; 534 clk_m2p2.rate = clk_h.rate; 535 clk_m2p3.rate = clk_h.rate; 536 clk_m2p4.rate = clk_h.rate; 537 clk_m2p5.rate = clk_h.rate; 538 clk_m2p6.rate = clk_h.rate; 539 clk_m2p7.rate = clk_h.rate; 540 clk_m2p8.rate = clk_h.rate; 541 clk_m2p9.rate = clk_h.rate; 542 clk_m2m0.rate = clk_h.rate; 543 clk_m2m1.rate = clk_h.rate; 544 } 545 546 static int __init ep93xx_clock_init(void) 547 { 548 u32 value; 549 550 /* Determine the bootloader configured pll1 rate */ 551 value = __raw_readl(EP93XX_SYSCON_CLKSET1); 552 if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1)) 553 clk_pll1.rate = clk_xtali.rate; 554 else 555 clk_pll1.rate = calc_pll_rate(value); 556 557 /* Initialize the pll1 derived clocks */ 558 clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; 559 clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7]; 560 clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3]; 561 ep93xx_dma_clock_init(); 562 563 /* Determine the bootloader configured pll2 rate */ 564 value = __raw_readl(EP93XX_SYSCON_CLKSET2); 565 if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2)) 566 clk_pll2.rate = clk_xtali.rate; 567 else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN) 568 clk_pll2.rate = calc_pll_rate(value); 569 else 570 clk_pll2.rate = 0; 571 572 /* Initialize the pll2 derived clocks */ 573 clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1); 574 575 /* 576 * EP93xx SSP clock rate was doubled in version E2. For more information 577 * see: 578 * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf 579 */ 580 if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2) 581 clk_spi.rate /= 2; 582 583 pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", 584 clk_pll1.rate / 1000000, clk_pll2.rate / 1000000); 585 pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", 586 clk_f.rate / 1000000, clk_h.rate / 1000000, 587 clk_p.rate / 1000000); 588 589 clkdev_add_table(clocks, ARRAY_SIZE(clocks)); 590 return 0; 591 } 592 postcore_initcall(ep93xx_clock_init); 593