xref: /openbmc/linux/arch/arm/mach-ep93xx/clock.c (revision 22246614)
1 /*
2  * arch/arm/mach-ep93xx/clock.c
3  * Clock control for Cirrus EP93xx chips.
4  *
5  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or (at
10  * your option) any later version.
11  */
12 
13 #include <linux/kernel.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/module.h>
17 #include <linux/string.h>
18 #include <asm/div64.h>
19 #include <asm/hardware.h>
20 #include <asm/io.h>
21 
22 struct clk {
23 	char		*name;
24 	unsigned long	rate;
25 	int		users;
26 	u32		enable_reg;
27 	u32		enable_mask;
28 };
29 
30 static struct clk clk_uart = {
31 	.name		= "UARTCLK",
32 	.rate		= 14745600,
33 };
34 static struct clk clk_pll1 = {
35 	.name		= "pll1",
36 };
37 static struct clk clk_f = {
38 	.name		= "fclk",
39 };
40 static struct clk clk_h = {
41 	.name		= "hclk",
42 };
43 static struct clk clk_p = {
44 	.name		= "pclk",
45 };
46 static struct clk clk_pll2 = {
47 	.name		= "pll2",
48 };
49 static struct clk clk_usb_host = {
50 	.name		= "usb_host",
51 	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
52 	.enable_mask	= EP93XX_SYSCON_CLOCK_USH_EN,
53 };
54 
55 
56 static struct clk *clocks[] = {
57 	&clk_uart,
58 	&clk_pll1,
59 	&clk_f,
60 	&clk_h,
61 	&clk_p,
62 	&clk_pll2,
63 	&clk_usb_host,
64 };
65 
66 struct clk *clk_get(struct device *dev, const char *id)
67 {
68 	int i;
69 
70 	for (i = 0; i < ARRAY_SIZE(clocks); i++) {
71 		if (!strcmp(clocks[i]->name, id))
72 			return clocks[i];
73 	}
74 
75 	return ERR_PTR(-ENOENT);
76 }
77 
78 int clk_enable(struct clk *clk)
79 {
80 	if (!clk->users++ && clk->enable_reg) {
81 		u32 value;
82 
83 		value = __raw_readl(clk->enable_reg);
84 		__raw_writel(value | clk->enable_mask, clk->enable_reg);
85 	}
86 
87 	return 0;
88 }
89 
90 void clk_disable(struct clk *clk)
91 {
92 	if (!--clk->users && clk->enable_reg) {
93 		u32 value;
94 
95 		value = __raw_readl(clk->enable_reg);
96 		__raw_writel(value & ~clk->enable_mask, clk->enable_reg);
97 	}
98 }
99 
100 unsigned long clk_get_rate(struct clk *clk)
101 {
102 	return clk->rate;
103 }
104 
105 void clk_put(struct clk *clk)
106 {
107 }
108 
109 
110 
111 static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
112 static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
113 static char pclk_divisors[] = { 1, 2, 4, 8 };
114 
115 /*
116  * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
117  */
118 static unsigned long calc_pll_rate(u32 config_word)
119 {
120 	unsigned long long rate;
121 	int i;
122 
123 	rate = 14745600;
124 	rate *= ((config_word >> 11) & 0x1f) + 1;		/* X1FBD */
125 	rate *= ((config_word >> 5) & 0x3f) + 1;		/* X2FBD */
126 	do_div(rate, (config_word & 0x1f) + 1);			/* X2IPD */
127 	for (i = 0; i < ((config_word >> 16) & 3); i++)		/* PS */
128 		rate >>= 1;
129 
130 	return (unsigned long)rate;
131 }
132 
133 static int __init ep93xx_clock_init(void)
134 {
135 	u32 value;
136 
137 	value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
138 	if (!(value & 0x00800000)) {			/* PLL1 bypassed?  */
139 		clk_pll1.rate = 14745600;
140 	} else {
141 		clk_pll1.rate = calc_pll_rate(value);
142 	}
143 	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
144 	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
145 	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
146 
147 	value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
148 	if (!(value & 0x00080000)) {			/* PLL2 bypassed?  */
149 		clk_pll2.rate = 14745600;
150 	} else if (value & 0x00040000) {		/* PLL2 enabled?  */
151 		clk_pll2.rate = calc_pll_rate(value);
152 	} else {
153 		clk_pll2.rate = 0;
154 	}
155 	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
156 
157 	printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
158 		clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
159 	printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
160 		clk_f.rate / 1000000, clk_h.rate / 1000000,
161 		clk_p.rate / 1000000);
162 
163 	return 0;
164 }
165 arch_initcall(ep93xx_clock_init);
166