1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * arch/arm/mach-dove/pcie.c 4 * 5 * PCIe functions for Marvell Dove 88AP510 SoC 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/pci.h> 10 #include <linux/clk.h> 11 #include <video/vga.h> 12 #include <asm/mach/pci.h> 13 #include <asm/mach/arch.h> 14 #include <asm/setup.h> 15 #include <asm/delay.h> 16 #include <plat/pcie.h> 17 #include <plat/addr-map.h> 18 #include "irqs.h" 19 #include "bridge-regs.h" 20 #include "common.h" 21 22 struct pcie_port { 23 u8 index; 24 u8 root_bus_nr; 25 void __iomem *base; 26 spinlock_t conf_lock; 27 char mem_space_name[16]; 28 struct resource res; 29 }; 30 31 static struct pcie_port pcie_port[2]; 32 static int num_pcie_ports; 33 34 35 static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) 36 { 37 struct pcie_port *pp; 38 struct resource realio; 39 40 if (nr >= num_pcie_ports) 41 return 0; 42 43 pp = &pcie_port[nr]; 44 sys->private_data = pp; 45 pp->root_bus_nr = sys->busnr; 46 47 /* 48 * Generic PCIe unit setup. 49 */ 50 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); 51 52 orion_pcie_setup(pp->base); 53 54 realio.start = sys->busnr * SZ_64K; 55 realio.end = realio.start + SZ_64K - 1; 56 pci_remap_iospace(&realio, pp->index == 0 ? DOVE_PCIE0_IO_PHYS_BASE : 57 DOVE_PCIE1_IO_PHYS_BASE); 58 59 /* 60 * IORESOURCE_MEM 61 */ 62 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), 63 "PCIe %d MEM", pp->index); 64 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; 65 pp->res.name = pp->mem_space_name; 66 if (pp->index == 0) { 67 pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE; 68 pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1; 69 } else { 70 pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE; 71 pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1; 72 } 73 pp->res.flags = IORESOURCE_MEM; 74 if (request_resource(&iomem_resource, &pp->res)) 75 panic("Request PCIe Memory resource failed\n"); 76 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); 77 78 return 1; 79 } 80 81 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) 82 { 83 /* 84 * Don't go out when trying to access nonexisting devices 85 * on the local bus. 86 */ 87 if (bus == pp->root_bus_nr && dev > 1) 88 return 0; 89 90 return 1; 91 } 92 93 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 94 int size, u32 *val) 95 { 96 struct pci_sys_data *sys = bus->sysdata; 97 struct pcie_port *pp = sys->private_data; 98 unsigned long flags; 99 int ret; 100 101 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) { 102 *val = 0xffffffff; 103 return PCIBIOS_DEVICE_NOT_FOUND; 104 } 105 106 spin_lock_irqsave(&pp->conf_lock, flags); 107 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); 108 spin_unlock_irqrestore(&pp->conf_lock, flags); 109 110 return ret; 111 } 112 113 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, 114 int where, int size, u32 val) 115 { 116 struct pci_sys_data *sys = bus->sysdata; 117 struct pcie_port *pp = sys->private_data; 118 unsigned long flags; 119 int ret; 120 121 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) 122 return PCIBIOS_DEVICE_NOT_FOUND; 123 124 spin_lock_irqsave(&pp->conf_lock, flags); 125 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); 126 spin_unlock_irqrestore(&pp->conf_lock, flags); 127 128 return ret; 129 } 130 131 static struct pci_ops pcie_ops = { 132 .read = pcie_rd_conf, 133 .write = pcie_wr_conf, 134 }; 135 136 /* 137 * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it 138 * is operating as a root complex this needs to be switched to 139 * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on 140 * the device. Decoding setup is handled by the orion code. 141 */ 142 static void rc_pci_fixup(struct pci_dev *dev) 143 { 144 if (dev->bus->parent == NULL && dev->devfn == 0) { 145 int i; 146 147 dev->class &= 0xff; 148 dev->class |= PCI_CLASS_BRIDGE_HOST << 8; 149 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 150 dev->resource[i].start = 0; 151 dev->resource[i].end = 0; 152 dev->resource[i].flags = 0; 153 } 154 } 155 } 156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); 157 158 static int __init 159 dove_pcie_scan_bus(int nr, struct pci_host_bridge *bridge) 160 { 161 struct pci_sys_data *sys = pci_host_bridge_priv(bridge); 162 163 if (nr >= num_pcie_ports) { 164 BUG(); 165 return -EINVAL; 166 } 167 168 list_splice_init(&sys->resources, &bridge->windows); 169 bridge->dev.parent = NULL; 170 bridge->sysdata = sys; 171 bridge->busnr = sys->busnr; 172 bridge->ops = &pcie_ops; 173 174 return pci_scan_root_bus_bridge(bridge); 175 } 176 177 static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 178 { 179 struct pci_sys_data *sys = dev->sysdata; 180 struct pcie_port *pp = sys->private_data; 181 182 return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0; 183 } 184 185 static struct hw_pci dove_pci __initdata = { 186 .nr_controllers = 2, 187 .setup = dove_pcie_setup, 188 .scan = dove_pcie_scan_bus, 189 .map_irq = dove_pcie_map_irq, 190 }; 191 192 static void __init add_pcie_port(int index, void __iomem *base) 193 { 194 printk(KERN_INFO "Dove PCIe port %d: ", index); 195 196 if (orion_pcie_link_up(base)) { 197 struct pcie_port *pp = &pcie_port[num_pcie_ports++]; 198 struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0")); 199 200 if (!IS_ERR(clk)) 201 clk_prepare_enable(clk); 202 203 printk(KERN_INFO "link up\n"); 204 205 pp->index = index; 206 pp->root_bus_nr = -1; 207 pp->base = base; 208 spin_lock_init(&pp->conf_lock); 209 memset(&pp->res, 0, sizeof(pp->res)); 210 } else { 211 printk(KERN_INFO "link down, ignoring\n"); 212 } 213 } 214 215 void __init dove_pcie_init(int init_port0, int init_port1) 216 { 217 vga_base = DOVE_PCIE0_MEM_PHYS_BASE; 218 219 if (init_port0) 220 add_pcie_port(0, DOVE_PCIE0_VIRT_BASE); 221 222 if (init_port1) 223 add_pcie_port(1, DOVE_PCIE1_VIRT_BASE); 224 225 pci_common_init(&dove_pci); 226 } 227