xref: /openbmc/linux/arch/arm/mach-dove/irqs.h (revision 3dc4b6fb)
1 /*
2  * IRQ definitions for Marvell Dove 88AP510 SoC
3  *
4  * This file is licensed under the terms of the GNU General Public
5  * License version 2.  This program is licensed "as is" without any
6  * warranty of any kind, whether express or implied.
7  */
8 
9 #ifndef __ASM_ARCH_IRQS_H
10 #define __ASM_ARCH_IRQS_H
11 
12 /*
13  * Dove Low Interrupt Controller
14  */
15 #define IRQ_DOVE_BRIDGE		(1 + 0)
16 #define IRQ_DOVE_H2C		(1 + 1)
17 #define IRQ_DOVE_C2H		(1 + 2)
18 #define IRQ_DOVE_NAND		(1 + 3)
19 #define IRQ_DOVE_PDMA		(1 + 4)
20 #define IRQ_DOVE_SPI1		(1 + 5)
21 #define IRQ_DOVE_SPI0		(1 + 6)
22 #define IRQ_DOVE_UART_0		(1 + 7)
23 #define IRQ_DOVE_UART_1		(1 + 8)
24 #define IRQ_DOVE_UART_2		(1 + 9)
25 #define IRQ_DOVE_UART_3		(1 + 10)
26 #define IRQ_DOVE_I2C		(1 + 11)
27 #define IRQ_DOVE_GPIO_0_7	(1 + 12)
28 #define IRQ_DOVE_GPIO_8_15	(1 + 13)
29 #define IRQ_DOVE_GPIO_16_23	(1 + 14)
30 #define IRQ_DOVE_PCIE0_ERR	(1 + 15)
31 #define IRQ_DOVE_PCIE0		(1 + 16)
32 #define IRQ_DOVE_PCIE1_ERR	(1 + 17)
33 #define IRQ_DOVE_PCIE1		(1 + 18)
34 #define IRQ_DOVE_I2S0		(1 + 19)
35 #define IRQ_DOVE_I2S0_ERR	(1 + 20)
36 #define IRQ_DOVE_I2S1		(1 + 21)
37 #define IRQ_DOVE_I2S1_ERR	(1 + 22)
38 #define IRQ_DOVE_USB_ERR	(1 + 23)
39 #define IRQ_DOVE_USB0		(1 + 24)
40 #define IRQ_DOVE_USB1		(1 + 25)
41 #define IRQ_DOVE_GE00_RX	(1 + 26)
42 #define IRQ_DOVE_GE00_TX	(1 + 27)
43 #define IRQ_DOVE_GE00_MISC	(1 + 28)
44 #define IRQ_DOVE_GE00_SUM	(1 + 29)
45 #define IRQ_DOVE_GE00_ERR	(1 + 30)
46 #define IRQ_DOVE_CRYPTO		(1 + 31)
47 
48 /*
49  * Dove High Interrupt Controller
50  */
51 #define IRQ_DOVE_AC97		(1 + 32)
52 #define IRQ_DOVE_PMU		(1 + 33)
53 #define IRQ_DOVE_CAM		(1 + 34)
54 #define IRQ_DOVE_SDIO0		(1 + 35)
55 #define IRQ_DOVE_SDIO1		(1 + 36)
56 #define IRQ_DOVE_SDIO0_WAKEUP	(1 + 37)
57 #define IRQ_DOVE_SDIO1_WAKEUP	(1 + 38)
58 #define IRQ_DOVE_XOR_00		(1 + 39)
59 #define IRQ_DOVE_XOR_01		(1 + 40)
60 #define IRQ_DOVE_XOR0_ERR	(1 + 41)
61 #define IRQ_DOVE_XOR_10		(1 + 42)
62 #define IRQ_DOVE_XOR_11		(1 + 43)
63 #define IRQ_DOVE_XOR1_ERR	(1 + 44)
64 #define IRQ_DOVE_LCD_DCON	(1 + 45)
65 #define IRQ_DOVE_LCD1		(1 + 46)
66 #define IRQ_DOVE_LCD0		(1 + 47)
67 #define IRQ_DOVE_GPU		(1 + 48)
68 #define IRQ_DOVE_PERFORM_MNTR	(1 + 49)
69 #define IRQ_DOVE_VPRO_DMA1	(1 + 51)
70 #define IRQ_DOVE_SSP_TIMER	(1 + 54)
71 #define IRQ_DOVE_SSP		(1 + 55)
72 #define IRQ_DOVE_MC_L2_ERR	(1 + 56)
73 #define IRQ_DOVE_CRYPTO_ERR	(1 + 59)
74 #define IRQ_DOVE_GPIO_24_31	(1 + 60)
75 #define IRQ_DOVE_HIGH_GPIO	(1 + 61)
76 #define IRQ_DOVE_SATA		(1 + 62)
77 
78 /*
79  * DOVE General Purpose Pins
80  */
81 #define IRQ_DOVE_GPIO_START	65
82 #define NR_GPIO_IRQS		64
83 
84 /*
85  * PMU interrupts
86  */
87 #define IRQ_DOVE_PMU_START	(IRQ_DOVE_GPIO_START + NR_GPIO_IRQS)
88 #define NR_PMU_IRQS		7
89 #define IRQ_DOVE_RTC		(IRQ_DOVE_PMU_START + 5)
90 
91 #define DOVE_NR_IRQS		(IRQ_DOVE_PMU_START + NR_PMU_IRQS)
92 
93 
94 #endif
95