1 /* 2 * arch/arm/mach-dove/irq.c 3 * 4 * Dove IRQ handling. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/irq.h> 14 #include <linux/gpio.h> 15 #include <linux/io.h> 16 #include <asm/mach/arch.h> 17 #include <plat/irq.h> 18 #include <asm/mach/irq.h> 19 #include <mach/pm.h> 20 #include <mach/bridge-regs.h> 21 #include "common.h" 22 23 static void pmu_irq_mask(struct irq_data *d) 24 { 25 int pin = irq_to_pmu(d->irq); 26 u32 u; 27 28 u = readl(PMU_INTERRUPT_MASK); 29 u &= ~(1 << (pin & 31)); 30 writel(u, PMU_INTERRUPT_MASK); 31 } 32 33 static void pmu_irq_unmask(struct irq_data *d) 34 { 35 int pin = irq_to_pmu(d->irq); 36 u32 u; 37 38 u = readl(PMU_INTERRUPT_MASK); 39 u |= 1 << (pin & 31); 40 writel(u, PMU_INTERRUPT_MASK); 41 } 42 43 static void pmu_irq_ack(struct irq_data *d) 44 { 45 int pin = irq_to_pmu(d->irq); 46 u32 u; 47 48 u = ~(1 << (pin & 31)); 49 writel(u, PMU_INTERRUPT_CAUSE); 50 } 51 52 static struct irq_chip pmu_irq_chip = { 53 .name = "pmu_irq", 54 .irq_mask = pmu_irq_mask, 55 .irq_unmask = pmu_irq_unmask, 56 .irq_ack = pmu_irq_ack, 57 }; 58 59 static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc) 60 { 61 unsigned long cause = readl(PMU_INTERRUPT_CAUSE); 62 63 cause &= readl(PMU_INTERRUPT_MASK); 64 if (cause == 0) { 65 do_bad_IRQ(irq, desc); 66 return; 67 } 68 69 for (irq = 0; irq < NR_PMU_IRQS; irq++) { 70 if (!(cause & (1 << irq))) 71 continue; 72 irq = pmu_to_irq(irq); 73 generic_handle_irq(irq); 74 } 75 } 76 77 static int __initdata gpio0_irqs[4] = { 78 IRQ_DOVE_GPIO_0_7, 79 IRQ_DOVE_GPIO_8_15, 80 IRQ_DOVE_GPIO_16_23, 81 IRQ_DOVE_GPIO_24_31, 82 }; 83 84 static int __initdata gpio1_irqs[4] = { 85 IRQ_DOVE_HIGH_GPIO, 86 0, 87 0, 88 0, 89 }; 90 91 static int __initdata gpio2_irqs[4] = { 92 0, 93 0, 94 0, 95 0, 96 }; 97 98 void __init dove_init_irq(void) 99 { 100 int i; 101 102 orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); 103 orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); 104 105 /* 106 * Initialize gpiolib for GPIOs 0-71. 107 */ 108 orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, 109 IRQ_DOVE_GPIO_START, gpio0_irqs); 110 111 orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, 112 IRQ_DOVE_GPIO_START + 32, gpio1_irqs); 113 114 orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0, 115 IRQ_DOVE_GPIO_START + 64, gpio2_irqs); 116 117 /* 118 * Mask and clear PMU interrupts 119 */ 120 writel(0, PMU_INTERRUPT_MASK); 121 writel(0, PMU_INTERRUPT_CAUSE); 122 123 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { 124 irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq); 125 irq_set_status_flags(i, IRQ_LEVEL); 126 set_irq_flags(i, IRQF_VALID); 127 } 128 irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); 129 } 130