1 /* 2 * arch/arm/mach-dove/common.c 3 * 4 * Core functions for Marvell Dove 88AP510 System On Chip 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/delay.h> 13 #include <linux/init.h> 14 #include <linux/platform_device.h> 15 #include <linux/pci.h> 16 #include <linux/clk-provider.h> 17 #include <linux/clk/mvebu.h> 18 #include <linux/ata_platform.h> 19 #include <linux/gpio.h> 20 #include <linux/of.h> 21 #include <linux/of_platform.h> 22 #include <asm/page.h> 23 #include <asm/setup.h> 24 #include <asm/timex.h> 25 #include <asm/hardware/cache-tauros2.h> 26 #include <asm/mach/map.h> 27 #include <asm/mach/time.h> 28 #include <asm/mach/pci.h> 29 #include <mach/dove.h> 30 #include <mach/pm.h> 31 #include <mach/bridge-regs.h> 32 #include <asm/mach/arch.h> 33 #include <linux/irq.h> 34 #include <plat/time.h> 35 #include <linux/platform_data/usb-ehci-orion.h> 36 #include <linux/platform_data/dma-mv_xor.h> 37 #include <plat/irq.h> 38 #include <plat/common.h> 39 #include <plat/addr-map.h> 40 #include "common.h" 41 42 /***************************************************************************** 43 * I/O Address Mapping 44 ****************************************************************************/ 45 static struct map_desc dove_io_desc[] __initdata = { 46 { 47 .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE, 48 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), 49 .length = DOVE_SB_REGS_SIZE, 50 .type = MT_DEVICE, 51 }, { 52 .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE, 53 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), 54 .length = DOVE_NB_REGS_SIZE, 55 .type = MT_DEVICE, 56 }, 57 }; 58 59 void __init dove_map_io(void) 60 { 61 iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc)); 62 } 63 64 /***************************************************************************** 65 * CLK tree 66 ****************************************************************************/ 67 static int dove_tclk; 68 69 static DEFINE_SPINLOCK(gating_lock); 70 static struct clk *tclk; 71 72 static struct clk __init *dove_register_gate(const char *name, 73 const char *parent, u8 bit_idx) 74 { 75 return clk_register_gate(NULL, name, parent, 0, 76 (void __iomem *)CLOCK_GATING_CONTROL, 77 bit_idx, 0, &gating_lock); 78 } 79 80 static void __init dove_clk_init(void) 81 { 82 struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; 83 struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; 84 struct clk *xor0, *xor1, *ge, *gephy; 85 86 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, 87 dove_tclk); 88 89 usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0); 90 usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1); 91 sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA); 92 pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0); 93 pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1); 94 sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0); 95 sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1); 96 nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND); 97 camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA); 98 i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0); 99 i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1); 100 crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO); 101 ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97); 102 pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA); 103 xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0); 104 xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1); 105 gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY); 106 ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE); 107 108 orion_clkdev_add(NULL, "orion_spi.0", tclk); 109 orion_clkdev_add(NULL, "orion_spi.1", tclk); 110 orion_clkdev_add(NULL, "orion_wdt", tclk); 111 orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk); 112 113 orion_clkdev_add(NULL, "orion-ehci.0", usb0); 114 orion_clkdev_add(NULL, "orion-ehci.1", usb1); 115 orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge); 116 orion_clkdev_add(NULL, "sata_mv.0", sata); 117 orion_clkdev_add("0", "pcie", pex0); 118 orion_clkdev_add("1", "pcie", pex1); 119 orion_clkdev_add(NULL, "sdhci-dove.0", sdio0); 120 orion_clkdev_add(NULL, "sdhci-dove.1", sdio1); 121 orion_clkdev_add(NULL, "orion_nand", nand); 122 orion_clkdev_add(NULL, "cafe1000-ccic.0", camera); 123 orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0); 124 orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1); 125 orion_clkdev_add(NULL, "mv_crypto", crypto); 126 orion_clkdev_add(NULL, "dove-ac97", ac97); 127 orion_clkdev_add(NULL, "dove-pdma", pdma); 128 orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0); 129 orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1); 130 } 131 132 /***************************************************************************** 133 * EHCI0 134 ****************************************************************************/ 135 void __init dove_ehci0_init(void) 136 { 137 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); 138 } 139 140 /***************************************************************************** 141 * EHCI1 142 ****************************************************************************/ 143 void __init dove_ehci1_init(void) 144 { 145 orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); 146 } 147 148 /***************************************************************************** 149 * GE00 150 ****************************************************************************/ 151 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) 152 { 153 orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, 154 IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR, 155 1600); 156 } 157 158 /***************************************************************************** 159 * SoC RTC 160 ****************************************************************************/ 161 void __init dove_rtc_init(void) 162 { 163 orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); 164 } 165 166 /***************************************************************************** 167 * SATA 168 ****************************************************************************/ 169 void __init dove_sata_init(struct mv_sata_platform_data *sata_data) 170 { 171 orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); 172 173 } 174 175 /***************************************************************************** 176 * UART0 177 ****************************************************************************/ 178 void __init dove_uart0_init(void) 179 { 180 orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, 181 IRQ_DOVE_UART_0, tclk); 182 } 183 184 /***************************************************************************** 185 * UART1 186 ****************************************************************************/ 187 void __init dove_uart1_init(void) 188 { 189 orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, 190 IRQ_DOVE_UART_1, tclk); 191 } 192 193 /***************************************************************************** 194 * UART2 195 ****************************************************************************/ 196 void __init dove_uart2_init(void) 197 { 198 orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, 199 IRQ_DOVE_UART_2, tclk); 200 } 201 202 /***************************************************************************** 203 * UART3 204 ****************************************************************************/ 205 void __init dove_uart3_init(void) 206 { 207 orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, 208 IRQ_DOVE_UART_3, tclk); 209 } 210 211 /***************************************************************************** 212 * SPI 213 ****************************************************************************/ 214 void __init dove_spi0_init(void) 215 { 216 orion_spi_init(DOVE_SPI0_PHYS_BASE); 217 } 218 219 void __init dove_spi1_init(void) 220 { 221 orion_spi_1_init(DOVE_SPI1_PHYS_BASE); 222 } 223 224 /***************************************************************************** 225 * I2C 226 ****************************************************************************/ 227 void __init dove_i2c_init(void) 228 { 229 orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10); 230 } 231 232 /***************************************************************************** 233 * Time handling 234 ****************************************************************************/ 235 void __init dove_init_early(void) 236 { 237 orion_time_set_base(TIMER_VIRT_BASE); 238 } 239 240 static int __init dove_find_tclk(void) 241 { 242 return 166666667; 243 } 244 245 static void __init dove_timer_init(void) 246 { 247 dove_tclk = dove_find_tclk(); 248 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, 249 IRQ_DOVE_BRIDGE, dove_tclk); 250 } 251 252 struct sys_timer dove_timer = { 253 .init = dove_timer_init, 254 }; 255 256 /***************************************************************************** 257 * Cryptographic Engines and Security Accelerator (CESA) 258 ****************************************************************************/ 259 void __init dove_crypto_init(void) 260 { 261 orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE, 262 DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO); 263 } 264 265 /***************************************************************************** 266 * XOR 0 267 ****************************************************************************/ 268 void __init dove_xor0_init(void) 269 { 270 orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, 271 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); 272 } 273 274 /***************************************************************************** 275 * XOR 1 276 ****************************************************************************/ 277 void __init dove_xor1_init(void) 278 { 279 orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, 280 IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); 281 } 282 283 /***************************************************************************** 284 * SDIO 285 ****************************************************************************/ 286 static u64 sdio_dmamask = DMA_BIT_MASK(32); 287 288 static struct resource dove_sdio0_resources[] = { 289 { 290 .start = DOVE_SDIO0_PHYS_BASE, 291 .end = DOVE_SDIO0_PHYS_BASE + 0xff, 292 .flags = IORESOURCE_MEM, 293 }, { 294 .start = IRQ_DOVE_SDIO0, 295 .end = IRQ_DOVE_SDIO0, 296 .flags = IORESOURCE_IRQ, 297 }, 298 }; 299 300 static struct platform_device dove_sdio0 = { 301 .name = "sdhci-dove", 302 .id = 0, 303 .dev = { 304 .dma_mask = &sdio_dmamask, 305 .coherent_dma_mask = DMA_BIT_MASK(32), 306 }, 307 .resource = dove_sdio0_resources, 308 .num_resources = ARRAY_SIZE(dove_sdio0_resources), 309 }; 310 311 void __init dove_sdio0_init(void) 312 { 313 platform_device_register(&dove_sdio0); 314 } 315 316 static struct resource dove_sdio1_resources[] = { 317 { 318 .start = DOVE_SDIO1_PHYS_BASE, 319 .end = DOVE_SDIO1_PHYS_BASE + 0xff, 320 .flags = IORESOURCE_MEM, 321 }, { 322 .start = IRQ_DOVE_SDIO1, 323 .end = IRQ_DOVE_SDIO1, 324 .flags = IORESOURCE_IRQ, 325 }, 326 }; 327 328 static struct platform_device dove_sdio1 = { 329 .name = "sdhci-dove", 330 .id = 1, 331 .dev = { 332 .dma_mask = &sdio_dmamask, 333 .coherent_dma_mask = DMA_BIT_MASK(32), 334 }, 335 .resource = dove_sdio1_resources, 336 .num_resources = ARRAY_SIZE(dove_sdio1_resources), 337 }; 338 339 void __init dove_sdio1_init(void) 340 { 341 platform_device_register(&dove_sdio1); 342 } 343 344 void __init dove_init(void) 345 { 346 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", 347 (dove_tclk + 499999) / 1000000); 348 349 #ifdef CONFIG_CACHE_TAUROS2 350 tauros2_init(0); 351 #endif 352 dove_setup_cpu_mbus(); 353 354 /* Setup root of clk tree */ 355 dove_clk_init(); 356 357 /* internal devices that every board has */ 358 dove_rtc_init(); 359 dove_xor0_init(); 360 dove_xor1_init(); 361 } 362 363 void dove_restart(char mode, const char *cmd) 364 { 365 /* 366 * Enable soft reset to assert RSTOUTn. 367 */ 368 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); 369 370 /* 371 * Assert soft reset. 372 */ 373 writel(SOFT_RESET, SYSTEM_SOFT_RESET); 374 375 while (1) 376 ; 377 } 378 379 #if defined(CONFIG_MACH_DOVE_DT) 380 /* 381 * There are still devices that doesn't even know about DT, 382 * get clock gates here and add a clock lookup. 383 */ 384 static void __init dove_legacy_clk_init(void) 385 { 386 struct device_node *np = of_find_compatible_node(NULL, NULL, 387 "marvell,dove-gating-clock"); 388 struct of_phandle_args clkspec; 389 390 clkspec.np = np; 391 clkspec.args_count = 1; 392 393 clkspec.args[0] = CLOCK_GATING_BIT_USB0; 394 orion_clkdev_add(NULL, "orion-ehci.0", 395 of_clk_get_from_provider(&clkspec)); 396 397 clkspec.args[0] = CLOCK_GATING_BIT_USB1; 398 orion_clkdev_add(NULL, "orion-ehci.1", 399 of_clk_get_from_provider(&clkspec)); 400 401 clkspec.args[0] = CLOCK_GATING_BIT_GBE; 402 orion_clkdev_add(NULL, "mv643xx_eth_port.0", 403 of_clk_get_from_provider(&clkspec)); 404 405 clkspec.args[0] = CLOCK_GATING_BIT_PCIE0; 406 orion_clkdev_add("0", "pcie", 407 of_clk_get_from_provider(&clkspec)); 408 409 clkspec.args[0] = CLOCK_GATING_BIT_PCIE1; 410 orion_clkdev_add("1", "pcie", 411 of_clk_get_from_provider(&clkspec)); 412 } 413 414 static void __init dove_of_clk_init(void) 415 { 416 mvebu_clocks_init(); 417 dove_legacy_clk_init(); 418 } 419 420 static struct mv643xx_eth_platform_data dove_dt_ge00_data = { 421 .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, 422 }; 423 424 static void __init dove_dt_init(void) 425 { 426 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", 427 (dove_tclk + 499999) / 1000000); 428 429 #ifdef CONFIG_CACHE_TAUROS2 430 tauros2_init(0); 431 #endif 432 dove_setup_cpu_mbus(); 433 434 /* Setup root of clk tree */ 435 dove_of_clk_init(); 436 437 /* Internal devices not ported to DT yet */ 438 dove_rtc_init(); 439 440 dove_ge00_init(&dove_dt_ge00_data); 441 dove_ehci0_init(); 442 dove_ehci1_init(); 443 dove_pcie_init(1, 1); 444 445 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 446 } 447 448 static const char * const dove_dt_board_compat[] = { 449 "marvell,dove", 450 NULL 451 }; 452 453 DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)") 454 .map_io = dove_map_io, 455 .init_early = dove_init_early, 456 .init_irq = orion_dt_init_irq, 457 .timer = &dove_timer, 458 .init_machine = dove_dt_init, 459 .restart = dove_restart, 460 .dt_compat = dove_dt_board_compat, 461 MACHINE_END 462 #endif 463