1 /* 2 * arch/arm/mach-dove/common.c 3 * 4 * Core functions for Marvell Dove 88AP510 System On Chip 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/init.h> 14 #include <linux/of.h> 15 #include <linux/of_platform.h> 16 #include <linux/platform_data/dma-mv_xor.h> 17 #include <linux/platform_data/usb-ehci-orion.h> 18 #include <linux/platform_device.h> 19 #include <asm/hardware/cache-tauros2.h> 20 #include <asm/mach/arch.h> 21 #include <asm/mach/map.h> 22 #include <asm/mach/time.h> 23 #include <mach/bridge-regs.h> 24 #include <mach/pm.h> 25 #include <plat/common.h> 26 #include <plat/irq.h> 27 #include <plat/time.h> 28 #include "common.h" 29 30 /***************************************************************************** 31 * I/O Address Mapping 32 ****************************************************************************/ 33 static struct map_desc dove_io_desc[] __initdata = { 34 { 35 .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE, 36 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), 37 .length = DOVE_SB_REGS_SIZE, 38 .type = MT_DEVICE, 39 }, { 40 .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE, 41 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), 42 .length = DOVE_NB_REGS_SIZE, 43 .type = MT_DEVICE, 44 }, 45 }; 46 47 void __init dove_map_io(void) 48 { 49 iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc)); 50 } 51 52 /***************************************************************************** 53 * CLK tree 54 ****************************************************************************/ 55 static int dove_tclk; 56 57 static DEFINE_SPINLOCK(gating_lock); 58 static struct clk *tclk; 59 60 static struct clk __init *dove_register_gate(const char *name, 61 const char *parent, u8 bit_idx) 62 { 63 return clk_register_gate(NULL, name, parent, 0, 64 (void __iomem *)CLOCK_GATING_CONTROL, 65 bit_idx, 0, &gating_lock); 66 } 67 68 static void __init dove_clk_init(void) 69 { 70 struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; 71 struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; 72 struct clk *xor0, *xor1, *ge, *gephy; 73 74 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, 75 dove_tclk); 76 77 usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0); 78 usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1); 79 sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA); 80 pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0); 81 pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1); 82 sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0); 83 sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1); 84 nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND); 85 camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA); 86 i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0); 87 i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1); 88 crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO); 89 ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97); 90 pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA); 91 xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0); 92 xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1); 93 gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY); 94 ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE); 95 96 orion_clkdev_add(NULL, "orion_spi.0", tclk); 97 orion_clkdev_add(NULL, "orion_spi.1", tclk); 98 orion_clkdev_add(NULL, "orion_wdt", tclk); 99 orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk); 100 101 orion_clkdev_add(NULL, "orion-ehci.0", usb0); 102 orion_clkdev_add(NULL, "orion-ehci.1", usb1); 103 orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge); 104 orion_clkdev_add(NULL, "sata_mv.0", sata); 105 orion_clkdev_add("0", "pcie", pex0); 106 orion_clkdev_add("1", "pcie", pex1); 107 orion_clkdev_add(NULL, "sdhci-dove.0", sdio0); 108 orion_clkdev_add(NULL, "sdhci-dove.1", sdio1); 109 orion_clkdev_add(NULL, "orion_nand", nand); 110 orion_clkdev_add(NULL, "cafe1000-ccic.0", camera); 111 orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0); 112 orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1); 113 orion_clkdev_add(NULL, "mv_crypto", crypto); 114 orion_clkdev_add(NULL, "dove-ac97", ac97); 115 orion_clkdev_add(NULL, "dove-pdma", pdma); 116 orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0); 117 orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1); 118 } 119 120 /***************************************************************************** 121 * EHCI0 122 ****************************************************************************/ 123 void __init dove_ehci0_init(void) 124 { 125 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); 126 } 127 128 /***************************************************************************** 129 * EHCI1 130 ****************************************************************************/ 131 void __init dove_ehci1_init(void) 132 { 133 orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); 134 } 135 136 /***************************************************************************** 137 * GE00 138 ****************************************************************************/ 139 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) 140 { 141 orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, 142 IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR, 143 1600); 144 } 145 146 /***************************************************************************** 147 * SoC RTC 148 ****************************************************************************/ 149 void __init dove_rtc_init(void) 150 { 151 orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); 152 } 153 154 /***************************************************************************** 155 * SATA 156 ****************************************************************************/ 157 void __init dove_sata_init(struct mv_sata_platform_data *sata_data) 158 { 159 orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); 160 161 } 162 163 /***************************************************************************** 164 * UART0 165 ****************************************************************************/ 166 void __init dove_uart0_init(void) 167 { 168 orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, 169 IRQ_DOVE_UART_0, tclk); 170 } 171 172 /***************************************************************************** 173 * UART1 174 ****************************************************************************/ 175 void __init dove_uart1_init(void) 176 { 177 orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, 178 IRQ_DOVE_UART_1, tclk); 179 } 180 181 /***************************************************************************** 182 * UART2 183 ****************************************************************************/ 184 void __init dove_uart2_init(void) 185 { 186 orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, 187 IRQ_DOVE_UART_2, tclk); 188 } 189 190 /***************************************************************************** 191 * UART3 192 ****************************************************************************/ 193 void __init dove_uart3_init(void) 194 { 195 orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, 196 IRQ_DOVE_UART_3, tclk); 197 } 198 199 /***************************************************************************** 200 * SPI 201 ****************************************************************************/ 202 void __init dove_spi0_init(void) 203 { 204 orion_spi_init(DOVE_SPI0_PHYS_BASE); 205 } 206 207 void __init dove_spi1_init(void) 208 { 209 orion_spi_1_init(DOVE_SPI1_PHYS_BASE); 210 } 211 212 /***************************************************************************** 213 * I2C 214 ****************************************************************************/ 215 void __init dove_i2c_init(void) 216 { 217 orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10); 218 } 219 220 /***************************************************************************** 221 * Time handling 222 ****************************************************************************/ 223 void __init dove_init_early(void) 224 { 225 orion_time_set_base(TIMER_VIRT_BASE); 226 mvebu_mbus_init("marvell,dove-mbus", 227 BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, 228 DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ); 229 } 230 231 static int __init dove_find_tclk(void) 232 { 233 return 166666667; 234 } 235 236 void __init dove_timer_init(void) 237 { 238 dove_tclk = dove_find_tclk(); 239 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, 240 IRQ_DOVE_BRIDGE, dove_tclk); 241 } 242 243 /***************************************************************************** 244 * Cryptographic Engines and Security Accelerator (CESA) 245 ****************************************************************************/ 246 void __init dove_crypto_init(void) 247 { 248 orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE, 249 DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO); 250 } 251 252 /***************************************************************************** 253 * XOR 0 254 ****************************************************************************/ 255 void __init dove_xor0_init(void) 256 { 257 orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, 258 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); 259 } 260 261 /***************************************************************************** 262 * XOR 1 263 ****************************************************************************/ 264 void __init dove_xor1_init(void) 265 { 266 orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, 267 IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); 268 } 269 270 /***************************************************************************** 271 * SDIO 272 ****************************************************************************/ 273 static u64 sdio_dmamask = DMA_BIT_MASK(32); 274 275 static struct resource dove_sdio0_resources[] = { 276 { 277 .start = DOVE_SDIO0_PHYS_BASE, 278 .end = DOVE_SDIO0_PHYS_BASE + 0xff, 279 .flags = IORESOURCE_MEM, 280 }, { 281 .start = IRQ_DOVE_SDIO0, 282 .end = IRQ_DOVE_SDIO0, 283 .flags = IORESOURCE_IRQ, 284 }, 285 }; 286 287 static struct platform_device dove_sdio0 = { 288 .name = "sdhci-dove", 289 .id = 0, 290 .dev = { 291 .dma_mask = &sdio_dmamask, 292 .coherent_dma_mask = DMA_BIT_MASK(32), 293 }, 294 .resource = dove_sdio0_resources, 295 .num_resources = ARRAY_SIZE(dove_sdio0_resources), 296 }; 297 298 void __init dove_sdio0_init(void) 299 { 300 platform_device_register(&dove_sdio0); 301 } 302 303 static struct resource dove_sdio1_resources[] = { 304 { 305 .start = DOVE_SDIO1_PHYS_BASE, 306 .end = DOVE_SDIO1_PHYS_BASE + 0xff, 307 .flags = IORESOURCE_MEM, 308 }, { 309 .start = IRQ_DOVE_SDIO1, 310 .end = IRQ_DOVE_SDIO1, 311 .flags = IORESOURCE_IRQ, 312 }, 313 }; 314 315 static struct platform_device dove_sdio1 = { 316 .name = "sdhci-dove", 317 .id = 1, 318 .dev = { 319 .dma_mask = &sdio_dmamask, 320 .coherent_dma_mask = DMA_BIT_MASK(32), 321 }, 322 .resource = dove_sdio1_resources, 323 .num_resources = ARRAY_SIZE(dove_sdio1_resources), 324 }; 325 326 void __init dove_sdio1_init(void) 327 { 328 platform_device_register(&dove_sdio1); 329 } 330 331 void __init dove_setup_cpu_wins(void) 332 { 333 /* 334 * The PCIe windows will no longer be statically allocated 335 * here once Dove is migrated to the pci-mvebu driver. 336 */ 337 mvebu_mbus_add_window_remap_flags("pcie0.0", 338 DOVE_PCIE0_IO_PHYS_BASE, 339 DOVE_PCIE0_IO_SIZE, 340 DOVE_PCIE0_IO_BUS_BASE, 341 MVEBU_MBUS_PCI_IO); 342 mvebu_mbus_add_window_remap_flags("pcie1.0", 343 DOVE_PCIE1_IO_PHYS_BASE, 344 DOVE_PCIE1_IO_SIZE, 345 DOVE_PCIE1_IO_BUS_BASE, 346 MVEBU_MBUS_PCI_IO); 347 mvebu_mbus_add_window_remap_flags("pcie0.0", 348 DOVE_PCIE0_MEM_PHYS_BASE, 349 DOVE_PCIE0_MEM_SIZE, 350 MVEBU_MBUS_NO_REMAP, 351 MVEBU_MBUS_PCI_MEM); 352 mvebu_mbus_add_window_remap_flags("pcie1.0", 353 DOVE_PCIE1_MEM_PHYS_BASE, 354 DOVE_PCIE1_MEM_SIZE, 355 MVEBU_MBUS_NO_REMAP, 356 MVEBU_MBUS_PCI_MEM); 357 mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE, 358 DOVE_CESA_SIZE); 359 mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE, 360 DOVE_BOOTROM_SIZE); 361 mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE, 362 DOVE_SCRATCHPAD_SIZE); 363 } 364 365 void __init dove_init(void) 366 { 367 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", 368 (dove_tclk + 499999) / 1000000); 369 370 #ifdef CONFIG_CACHE_TAUROS2 371 tauros2_init(0); 372 #endif 373 dove_setup_cpu_wins(); 374 375 /* Setup root of clk tree */ 376 dove_clk_init(); 377 378 /* internal devices that every board has */ 379 dove_rtc_init(); 380 dove_xor0_init(); 381 dove_xor1_init(); 382 } 383 384 void dove_restart(enum reboot_mode mode, const char *cmd) 385 { 386 /* 387 * Enable soft reset to assert RSTOUTn. 388 */ 389 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); 390 391 /* 392 * Assert soft reset. 393 */ 394 writel(SOFT_RESET, SYSTEM_SOFT_RESET); 395 396 while (1) 397 ; 398 } 399