1 /* 2 * arch/arm/mach-dove/common.c 3 * 4 * Core functions for Marvell Dove 88AP510 System On Chip 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/init.h> 14 #include <linux/of.h> 15 #include <linux/of_platform.h> 16 #include <linux/platform_data/dma-mv_xor.h> 17 #include <linux/platform_data/usb-ehci-orion.h> 18 #include <linux/platform_device.h> 19 #include <asm/hardware/cache-tauros2.h> 20 #include <asm/mach/arch.h> 21 #include <asm/mach/map.h> 22 #include <asm/mach/time.h> 23 #include <mach/bridge-regs.h> 24 #include <mach/pm.h> 25 #include <plat/common.h> 26 #include <plat/irq.h> 27 #include <plat/time.h> 28 #include "common.h" 29 30 /* These can go away once Dove uses the mvebu-mbus DT binding */ 31 #define DOVE_MBUS_PCIE0_MEM_TARGET 0x4 32 #define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8 33 #define DOVE_MBUS_PCIE0_IO_TARGET 0x4 34 #define DOVE_MBUS_PCIE0_IO_ATTR 0xe0 35 #define DOVE_MBUS_PCIE1_MEM_TARGET 0x8 36 #define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8 37 #define DOVE_MBUS_PCIE1_IO_TARGET 0x8 38 #define DOVE_MBUS_PCIE1_IO_ATTR 0xe0 39 #define DOVE_MBUS_CESA_TARGET 0x3 40 #define DOVE_MBUS_CESA_ATTR 0x1 41 #define DOVE_MBUS_BOOTROM_TARGET 0x1 42 #define DOVE_MBUS_BOOTROM_ATTR 0xfd 43 #define DOVE_MBUS_SCRATCHPAD_TARGET 0xd 44 #define DOVE_MBUS_SCRATCHPAD_ATTR 0x0 45 46 /***************************************************************************** 47 * I/O Address Mapping 48 ****************************************************************************/ 49 static struct map_desc dove_io_desc[] __initdata = { 50 { 51 .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE, 52 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), 53 .length = DOVE_SB_REGS_SIZE, 54 .type = MT_DEVICE, 55 }, { 56 .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE, 57 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), 58 .length = DOVE_NB_REGS_SIZE, 59 .type = MT_DEVICE, 60 }, 61 }; 62 63 void __init dove_map_io(void) 64 { 65 iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc)); 66 } 67 68 /***************************************************************************** 69 * CLK tree 70 ****************************************************************************/ 71 static int dove_tclk; 72 73 static DEFINE_SPINLOCK(gating_lock); 74 static struct clk *tclk; 75 76 static struct clk __init *dove_register_gate(const char *name, 77 const char *parent, u8 bit_idx) 78 { 79 return clk_register_gate(NULL, name, parent, 0, 80 (void __iomem *)CLOCK_GATING_CONTROL, 81 bit_idx, 0, &gating_lock); 82 } 83 84 static void __init dove_clk_init(void) 85 { 86 struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; 87 struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; 88 struct clk *xor0, *xor1, *ge, *gephy; 89 90 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, 91 dove_tclk); 92 93 usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0); 94 usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1); 95 sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA); 96 pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0); 97 pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1); 98 sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0); 99 sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1); 100 nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND); 101 camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA); 102 i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0); 103 i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1); 104 crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO); 105 ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97); 106 pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA); 107 xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0); 108 xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1); 109 gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY); 110 ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE); 111 112 orion_clkdev_add(NULL, "orion_spi.0", tclk); 113 orion_clkdev_add(NULL, "orion_spi.1", tclk); 114 orion_clkdev_add(NULL, "orion_wdt", tclk); 115 orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk); 116 117 orion_clkdev_add(NULL, "orion-ehci.0", usb0); 118 orion_clkdev_add(NULL, "orion-ehci.1", usb1); 119 orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge); 120 orion_clkdev_add(NULL, "sata_mv.0", sata); 121 orion_clkdev_add("0", "pcie", pex0); 122 orion_clkdev_add("1", "pcie", pex1); 123 orion_clkdev_add(NULL, "sdhci-dove.0", sdio0); 124 orion_clkdev_add(NULL, "sdhci-dove.1", sdio1); 125 orion_clkdev_add(NULL, "orion_nand", nand); 126 orion_clkdev_add(NULL, "cafe1000-ccic.0", camera); 127 orion_clkdev_add(NULL, "mvebu-audio.0", i2s0); 128 orion_clkdev_add(NULL, "mvebu-audio.1", i2s1); 129 orion_clkdev_add(NULL, "mv_crypto", crypto); 130 orion_clkdev_add(NULL, "dove-ac97", ac97); 131 orion_clkdev_add(NULL, "dove-pdma", pdma); 132 orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0); 133 orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1); 134 } 135 136 /***************************************************************************** 137 * EHCI0 138 ****************************************************************************/ 139 void __init dove_ehci0_init(void) 140 { 141 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); 142 } 143 144 /***************************************************************************** 145 * EHCI1 146 ****************************************************************************/ 147 void __init dove_ehci1_init(void) 148 { 149 orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); 150 } 151 152 /***************************************************************************** 153 * GE00 154 ****************************************************************************/ 155 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) 156 { 157 orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, 158 IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR, 159 1600); 160 } 161 162 /***************************************************************************** 163 * SoC RTC 164 ****************************************************************************/ 165 void __init dove_rtc_init(void) 166 { 167 orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); 168 } 169 170 /***************************************************************************** 171 * SATA 172 ****************************************************************************/ 173 void __init dove_sata_init(struct mv_sata_platform_data *sata_data) 174 { 175 orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); 176 177 } 178 179 /***************************************************************************** 180 * UART0 181 ****************************************************************************/ 182 void __init dove_uart0_init(void) 183 { 184 orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, 185 IRQ_DOVE_UART_0, tclk); 186 } 187 188 /***************************************************************************** 189 * UART1 190 ****************************************************************************/ 191 void __init dove_uart1_init(void) 192 { 193 orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, 194 IRQ_DOVE_UART_1, tclk); 195 } 196 197 /***************************************************************************** 198 * UART2 199 ****************************************************************************/ 200 void __init dove_uart2_init(void) 201 { 202 orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, 203 IRQ_DOVE_UART_2, tclk); 204 } 205 206 /***************************************************************************** 207 * UART3 208 ****************************************************************************/ 209 void __init dove_uart3_init(void) 210 { 211 orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, 212 IRQ_DOVE_UART_3, tclk); 213 } 214 215 /***************************************************************************** 216 * SPI 217 ****************************************************************************/ 218 void __init dove_spi0_init(void) 219 { 220 orion_spi_init(DOVE_SPI0_PHYS_BASE); 221 } 222 223 void __init dove_spi1_init(void) 224 { 225 orion_spi_1_init(DOVE_SPI1_PHYS_BASE); 226 } 227 228 /***************************************************************************** 229 * I2C 230 ****************************************************************************/ 231 void __init dove_i2c_init(void) 232 { 233 orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10); 234 } 235 236 /***************************************************************************** 237 * Time handling 238 ****************************************************************************/ 239 void __init dove_init_early(void) 240 { 241 orion_time_set_base(TIMER_VIRT_BASE); 242 mvebu_mbus_init("marvell,dove-mbus", 243 BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, 244 DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ); 245 } 246 247 static int __init dove_find_tclk(void) 248 { 249 return 166666667; 250 } 251 252 void __init dove_timer_init(void) 253 { 254 dove_tclk = dove_find_tclk(); 255 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, 256 IRQ_DOVE_BRIDGE, dove_tclk); 257 } 258 259 /***************************************************************************** 260 * Cryptographic Engines and Security Accelerator (CESA) 261 ****************************************************************************/ 262 void __init dove_crypto_init(void) 263 { 264 orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE, 265 DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO); 266 } 267 268 /***************************************************************************** 269 * XOR 0 270 ****************************************************************************/ 271 void __init dove_xor0_init(void) 272 { 273 orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, 274 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); 275 } 276 277 /***************************************************************************** 278 * XOR 1 279 ****************************************************************************/ 280 void __init dove_xor1_init(void) 281 { 282 orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, 283 IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); 284 } 285 286 /***************************************************************************** 287 * SDIO 288 ****************************************************************************/ 289 static u64 sdio_dmamask = DMA_BIT_MASK(32); 290 291 static struct resource dove_sdio0_resources[] = { 292 { 293 .start = DOVE_SDIO0_PHYS_BASE, 294 .end = DOVE_SDIO0_PHYS_BASE + 0xff, 295 .flags = IORESOURCE_MEM, 296 }, { 297 .start = IRQ_DOVE_SDIO0, 298 .end = IRQ_DOVE_SDIO0, 299 .flags = IORESOURCE_IRQ, 300 }, 301 }; 302 303 static struct platform_device dove_sdio0 = { 304 .name = "sdhci-dove", 305 .id = 0, 306 .dev = { 307 .dma_mask = &sdio_dmamask, 308 .coherent_dma_mask = DMA_BIT_MASK(32), 309 }, 310 .resource = dove_sdio0_resources, 311 .num_resources = ARRAY_SIZE(dove_sdio0_resources), 312 }; 313 314 void __init dove_sdio0_init(void) 315 { 316 platform_device_register(&dove_sdio0); 317 } 318 319 static struct resource dove_sdio1_resources[] = { 320 { 321 .start = DOVE_SDIO1_PHYS_BASE, 322 .end = DOVE_SDIO1_PHYS_BASE + 0xff, 323 .flags = IORESOURCE_MEM, 324 }, { 325 .start = IRQ_DOVE_SDIO1, 326 .end = IRQ_DOVE_SDIO1, 327 .flags = IORESOURCE_IRQ, 328 }, 329 }; 330 331 static struct platform_device dove_sdio1 = { 332 .name = "sdhci-dove", 333 .id = 1, 334 .dev = { 335 .dma_mask = &sdio_dmamask, 336 .coherent_dma_mask = DMA_BIT_MASK(32), 337 }, 338 .resource = dove_sdio1_resources, 339 .num_resources = ARRAY_SIZE(dove_sdio1_resources), 340 }; 341 342 void __init dove_sdio1_init(void) 343 { 344 platform_device_register(&dove_sdio1); 345 } 346 347 void __init dove_setup_cpu_wins(void) 348 { 349 /* 350 * The PCIe windows will no longer be statically allocated 351 * here once Dove is migrated to the pci-mvebu driver. The 352 * non-PCIe windows will no longer be created here once Dove 353 * fully moves to DT. 354 */ 355 mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET, 356 DOVE_MBUS_PCIE0_IO_ATTR, 357 DOVE_PCIE0_IO_PHYS_BASE, 358 DOVE_PCIE0_IO_SIZE, 359 DOVE_PCIE0_IO_BUS_BASE); 360 mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET, 361 DOVE_MBUS_PCIE1_IO_ATTR, 362 DOVE_PCIE1_IO_PHYS_BASE, 363 DOVE_PCIE1_IO_SIZE, 364 DOVE_PCIE1_IO_BUS_BASE); 365 mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET, 366 DOVE_MBUS_PCIE0_MEM_ATTR, 367 DOVE_PCIE0_MEM_PHYS_BASE, 368 DOVE_PCIE0_MEM_SIZE); 369 mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET, 370 DOVE_MBUS_PCIE1_MEM_ATTR, 371 DOVE_PCIE1_MEM_PHYS_BASE, 372 DOVE_PCIE1_MEM_SIZE); 373 mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET, 374 DOVE_MBUS_CESA_ATTR, 375 DOVE_CESA_PHYS_BASE, 376 DOVE_CESA_SIZE); 377 mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET, 378 DOVE_MBUS_BOOTROM_ATTR, 379 DOVE_BOOTROM_PHYS_BASE, 380 DOVE_BOOTROM_SIZE); 381 mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET, 382 DOVE_MBUS_SCRATCHPAD_ATTR, 383 DOVE_SCRATCHPAD_PHYS_BASE, 384 DOVE_SCRATCHPAD_SIZE); 385 } 386 387 void __init dove_init(void) 388 { 389 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", 390 (dove_tclk + 499999) / 1000000); 391 392 #ifdef CONFIG_CACHE_TAUROS2 393 tauros2_init(0); 394 #endif 395 dove_setup_cpu_wins(); 396 397 /* Setup root of clk tree */ 398 dove_clk_init(); 399 400 /* internal devices that every board has */ 401 dove_rtc_init(); 402 dove_xor0_init(); 403 dove_xor1_init(); 404 } 405 406 void dove_restart(enum reboot_mode mode, const char *cmd) 407 { 408 /* 409 * Enable soft reset to assert RSTOUTn. 410 */ 411 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); 412 413 /* 414 * Assert soft reset. 415 */ 416 writel(SOFT_RESET, SYSTEM_SOFT_RESET); 417 418 while (1) 419 ; 420 } 421