xref: /openbmc/linux/arch/arm/mach-davinci/mux.c (revision 7dd65feb)
1 /*
2  * Utility to set the DAVINCI MUX register from a table in mux.h
3  *
4  * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5  *
6  * Based on linux/arch/arm/plat-omap/mux.c:
7  * Copyright (C) 2003 - 2005 Nokia Corporation
8  *
9  * Written by Tony Lindgren
10  *
11  * 2007 (c) MontaVista Software, Inc. This file is licensed under
12  * the terms of the GNU General Public License version 2. This program
13  * is licensed "as is" without any warranty of any kind, whether express
14  * or implied.
15  *
16  * Copyright (C) 2008 Texas Instruments.
17  */
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/spinlock.h>
21 
22 #include <mach/mux.h>
23 #include <mach/common.h>
24 
25 /*
26  * Sets the DAVINCI MUX register based on the table
27  */
28 int __init_or_module davinci_cfg_reg(const unsigned long index)
29 {
30 	static DEFINE_SPINLOCK(mux_spin_lock);
31 	struct davinci_soc_info *soc_info = &davinci_soc_info;
32 	void __iomem *base = soc_info->pinmux_base;
33 	unsigned long flags;
34 	const struct mux_config *cfg;
35 	unsigned int reg_orig = 0, reg = 0;
36 	unsigned int mask, warn = 0;
37 
38 	if (!soc_info->pinmux_pins)
39 		BUG();
40 
41 	if (index >= soc_info->pinmux_pins_num) {
42 		printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
43 		       index, soc_info->pinmux_pins_num);
44 		dump_stack();
45 		return -ENODEV;
46 	}
47 
48 	cfg = &soc_info->pinmux_pins[index];
49 
50 	if (cfg->name == NULL) {
51 		printk(KERN_ERR "No entry for the specified index\n");
52 		return -ENODEV;
53 	}
54 
55 	/* Update the mux register in question */
56 	if (cfg->mask) {
57 		unsigned	tmp1, tmp2;
58 
59 		spin_lock_irqsave(&mux_spin_lock, flags);
60 		reg_orig = __raw_readl(base + cfg->mux_reg);
61 
62 		mask = (cfg->mask << cfg->mask_offset);
63 		tmp1 = reg_orig & mask;
64 		reg = reg_orig & ~mask;
65 
66 		tmp2 = (cfg->mode << cfg->mask_offset);
67 		reg |= tmp2;
68 
69 		if (tmp1 != tmp2)
70 			warn = 1;
71 
72 		__raw_writel(reg, base + cfg->mux_reg);
73 		spin_unlock_irqrestore(&mux_spin_lock, flags);
74 	}
75 
76 	if (warn) {
77 #ifdef CONFIG_DAVINCI_MUX_WARNINGS
78 		printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
79 #endif
80 	}
81 
82 #ifdef CONFIG_DAVINCI_MUX_DEBUG
83 	if (cfg->debug || warn) {
84 		printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name);
85 		printk(KERN_WARNING "	   %s (0x%08x) = 0x%08x -> 0x%08x\n",
86 		       cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
87 	}
88 #endif
89 
90 	return 0;
91 }
92 EXPORT_SYMBOL(davinci_cfg_reg);
93 
94 int da8xx_pinmux_setup(const short pins[])
95 {
96 	int i, error = -EINVAL;
97 
98 	if (pins)
99 		for (i = 0; pins[i] >= 0; i++) {
100 			error = davinci_cfg_reg(pins[i]);
101 			if (error)
102 				break;
103 		}
104 
105 	return error;
106 }
107