1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * DA8XX/OMAP L1XX platform device data
4  *
5  * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
6  * Derived from code that was:
7  *	Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
8  */
9 #include <linux/ahci_platform.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk.h>
12 #include <linux/clkdev.h>
13 #include <linux/dma-contiguous.h>
14 #include <linux/dmaengine.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/platform_device.h>
18 #include <linux/reboot.h>
19 #include <linux/serial_8250.h>
20 
21 #include <mach/common.h>
22 #include <mach/cputype.h>
23 #include <mach/da8xx.h>
24 
25 #include "asp.h"
26 #include "cpuidle.h"
27 #include "irqs.h"
28 #include "sram.h"
29 
30 #define DA8XX_TPCC_BASE			0x01c00000
31 #define DA8XX_TPTC0_BASE		0x01c08000
32 #define DA8XX_TPTC1_BASE		0x01c08400
33 #define DA8XX_WDOG_BASE			0x01c21000 /* DA8XX_TIMER64P1_BASE */
34 #define DA8XX_I2C0_BASE			0x01c22000
35 #define DA8XX_RTC_BASE			0x01c23000
36 #define DA8XX_PRUSS_MEM_BASE		0x01c30000
37 #define DA8XX_MMCSD0_BASE		0x01c40000
38 #define DA8XX_SPI0_BASE			0x01c41000
39 #define DA830_SPI1_BASE			0x01e12000
40 #define DA8XX_LCD_CNTRL_BASE		0x01e13000
41 #define DA850_SATA_BASE			0x01e18000
42 #define DA850_MMCSD1_BASE		0x01e1b000
43 #define DA8XX_EMAC_CPPI_PORT_BASE	0x01e20000
44 #define DA8XX_EMAC_CPGMACSS_BASE	0x01e22000
45 #define DA8XX_EMAC_CPGMAC_BASE		0x01e23000
46 #define DA8XX_EMAC_MDIO_BASE		0x01e24000
47 #define DA8XX_I2C1_BASE			0x01e28000
48 #define DA850_TPCC1_BASE		0x01e30000
49 #define DA850_TPTC2_BASE		0x01e38000
50 #define DA850_SPI1_BASE			0x01f0e000
51 #define DA8XX_DDR2_CTL_BASE		0xb0000000
52 
53 #define DA8XX_EMAC_CTRL_REG_OFFSET	0x3000
54 #define DA8XX_EMAC_MOD_REG_OFFSET	0x2000
55 #define DA8XX_EMAC_RAM_OFFSET		0x0000
56 #define DA8XX_EMAC_CTRL_RAM_SIZE	SZ_8K
57 
58 void __iomem *da8xx_syscfg0_base;
59 void __iomem *da8xx_syscfg1_base;
60 
61 static struct plat_serial8250_port da8xx_serial0_pdata[] = {
62 	{
63 		.mapbase	= DA8XX_UART0_BASE,
64 		.irq		= DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0),
65 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
66 					UPF_IOREMAP,
67 		.iotype		= UPIO_MEM,
68 		.regshift	= 2,
69 	},
70 	{
71 		.flags	= 0,
72 	}
73 };
74 static struct plat_serial8250_port da8xx_serial1_pdata[] = {
75 	{
76 		.mapbase	= DA8XX_UART1_BASE,
77 		.irq		= DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1),
78 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
79 					UPF_IOREMAP,
80 		.iotype		= UPIO_MEM,
81 		.regshift	= 2,
82 	},
83 	{
84 		.flags	= 0,
85 	}
86 };
87 static struct plat_serial8250_port da8xx_serial2_pdata[] = {
88 	{
89 		.mapbase	= DA8XX_UART2_BASE,
90 		.irq		= DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2),
91 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
92 					UPF_IOREMAP,
93 		.iotype		= UPIO_MEM,
94 		.regshift	= 2,
95 	},
96 	{
97 		.flags	= 0,
98 	}
99 };
100 
101 struct platform_device da8xx_serial_device[] = {
102 	{
103 		.name	= "serial8250",
104 		.id	= PLAT8250_DEV_PLATFORM,
105 		.dev	= {
106 			.platform_data	= da8xx_serial0_pdata,
107 		}
108 	},
109 	{
110 		.name	= "serial8250",
111 		.id	= PLAT8250_DEV_PLATFORM1,
112 		.dev	= {
113 			.platform_data	= da8xx_serial1_pdata,
114 		}
115 	},
116 	{
117 		.name	= "serial8250",
118 		.id	= PLAT8250_DEV_PLATFORM2,
119 		.dev	= {
120 			.platform_data	= da8xx_serial2_pdata,
121 		}
122 	},
123 	{
124 	}
125 };
126 
127 static s8 da8xx_queue_priority_mapping[][2] = {
128 	/* {event queue no, Priority} */
129 	{0, 3},
130 	{1, 7},
131 	{-1, -1}
132 };
133 
134 static s8 da850_queue_priority_mapping[][2] = {
135 	/* {event queue no, Priority} */
136 	{0, 3},
137 	{-1, -1}
138 };
139 
140 static struct edma_soc_info da8xx_edma0_pdata = {
141 	.queue_priority_mapping	= da8xx_queue_priority_mapping,
142 	.default_queue		= EVENTQ_1,
143 };
144 
145 static struct edma_soc_info da850_edma1_pdata = {
146 	.queue_priority_mapping	= da850_queue_priority_mapping,
147 	.default_queue		= EVENTQ_0,
148 };
149 
150 static struct resource da8xx_edma0_resources[] = {
151 	{
152 		.name	= "edma3_cc",
153 		.start	= DA8XX_TPCC_BASE,
154 		.end	= DA8XX_TPCC_BASE + SZ_32K - 1,
155 		.flags	= IORESOURCE_MEM,
156 	},
157 	{
158 		.name	= "edma3_tc0",
159 		.start	= DA8XX_TPTC0_BASE,
160 		.end	= DA8XX_TPTC0_BASE + SZ_1K - 1,
161 		.flags	= IORESOURCE_MEM,
162 	},
163 	{
164 		.name	= "edma3_tc1",
165 		.start	= DA8XX_TPTC1_BASE,
166 		.end	= DA8XX_TPTC1_BASE + SZ_1K - 1,
167 		.flags	= IORESOURCE_MEM,
168 	},
169 	{
170 		.name	= "edma3_ccint",
171 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0),
172 		.flags	= IORESOURCE_IRQ,
173 	},
174 	{
175 		.name	= "edma3_ccerrint",
176 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT),
177 		.flags	= IORESOURCE_IRQ,
178 	},
179 };
180 
181 static struct resource da850_edma1_resources[] = {
182 	{
183 		.name	= "edma3_cc",
184 		.start	= DA850_TPCC1_BASE,
185 		.end	= DA850_TPCC1_BASE + SZ_32K - 1,
186 		.flags	= IORESOURCE_MEM,
187 	},
188 	{
189 		.name	= "edma3_tc0",
190 		.start	= DA850_TPTC2_BASE,
191 		.end	= DA850_TPTC2_BASE + SZ_1K - 1,
192 		.flags	= IORESOURCE_MEM,
193 	},
194 	{
195 		.name	= "edma3_ccint",
196 		.start	= DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1),
197 		.flags	= IORESOURCE_IRQ,
198 	},
199 	{
200 		.name	= "edma3_ccerrint",
201 		.start	= DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1),
202 		.flags	= IORESOURCE_IRQ,
203 	},
204 };
205 
206 static const struct platform_device_info da8xx_edma0_device __initconst = {
207 	.name		= "edma",
208 	.id		= 0,
209 	.dma_mask	= DMA_BIT_MASK(32),
210 	.res		= da8xx_edma0_resources,
211 	.num_res	= ARRAY_SIZE(da8xx_edma0_resources),
212 	.data		= &da8xx_edma0_pdata,
213 	.size_data	= sizeof(da8xx_edma0_pdata),
214 };
215 
216 static const struct platform_device_info da850_edma1_device __initconst = {
217 	.name		= "edma",
218 	.id		= 1,
219 	.dma_mask	= DMA_BIT_MASK(32),
220 	.res		= da850_edma1_resources,
221 	.num_res	= ARRAY_SIZE(da850_edma1_resources),
222 	.data		= &da850_edma1_pdata,
223 	.size_data	= sizeof(da850_edma1_pdata),
224 };
225 
226 static const struct dma_slave_map da830_edma_map[] = {
227 	{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
228 	{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
229 	{ "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
230 	{ "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
231 	{ "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
232 	{ "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
233 	{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
234 	{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
235 	{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
236 	{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
237 	{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
238 	{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
239 };
240 
241 int __init da830_register_edma(struct edma_rsv_info *rsv)
242 {
243 	struct platform_device *edma_pdev;
244 
245 	da8xx_edma0_pdata.rsv = rsv;
246 
247 	da8xx_edma0_pdata.slave_map = da830_edma_map;
248 	da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
249 
250 	edma_pdev = platform_device_register_full(&da8xx_edma0_device);
251 	return PTR_ERR_OR_ZERO(edma_pdev);
252 }
253 
254 static const struct dma_slave_map da850_edma0_map[] = {
255 	{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
256 	{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
257 	{ "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
258 	{ "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
259 	{ "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
260 	{ "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
261 	{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
262 	{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
263 	{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
264 	{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
265 	{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
266 	{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
267 };
268 
269 static const struct dma_slave_map da850_edma1_map[] = {
270 	{ "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
271 	{ "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
272 };
273 
274 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
275 {
276 	struct platform_device *edma_pdev;
277 
278 	if (rsv) {
279 		da8xx_edma0_pdata.rsv = rsv[0];
280 		da850_edma1_pdata.rsv = rsv[1];
281 	}
282 
283 	da8xx_edma0_pdata.slave_map = da850_edma0_map;
284 	da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
285 
286 	edma_pdev = platform_device_register_full(&da8xx_edma0_device);
287 	if (IS_ERR(edma_pdev)) {
288 		pr_warn("%s: Failed to register eDMA0\n", __func__);
289 		return PTR_ERR(edma_pdev);
290 	}
291 
292 	da850_edma1_pdata.slave_map = da850_edma1_map;
293 	da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
294 
295 	edma_pdev = platform_device_register_full(&da850_edma1_device);
296 	return PTR_ERR_OR_ZERO(edma_pdev);
297 }
298 
299 static struct resource da8xx_i2c_resources0[] = {
300 	{
301 		.start	= DA8XX_I2C0_BASE,
302 		.end	= DA8XX_I2C0_BASE + SZ_4K - 1,
303 		.flags	= IORESOURCE_MEM,
304 	},
305 	{
306 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
307 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
308 		.flags	= IORESOURCE_IRQ,
309 	},
310 };
311 
312 static struct platform_device da8xx_i2c_device0 = {
313 	.name		= "i2c_davinci",
314 	.id		= 1,
315 	.num_resources	= ARRAY_SIZE(da8xx_i2c_resources0),
316 	.resource	= da8xx_i2c_resources0,
317 };
318 
319 static struct resource da8xx_i2c_resources1[] = {
320 	{
321 		.start	= DA8XX_I2C1_BASE,
322 		.end	= DA8XX_I2C1_BASE + SZ_4K - 1,
323 		.flags	= IORESOURCE_MEM,
324 	},
325 	{
326 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
327 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
328 		.flags	= IORESOURCE_IRQ,
329 	},
330 };
331 
332 static struct platform_device da8xx_i2c_device1 = {
333 	.name		= "i2c_davinci",
334 	.id		= 2,
335 	.num_resources	= ARRAY_SIZE(da8xx_i2c_resources1),
336 	.resource	= da8xx_i2c_resources1,
337 };
338 
339 int __init da8xx_register_i2c(int instance,
340 		struct davinci_i2c_platform_data *pdata)
341 {
342 	struct platform_device *pdev;
343 
344 	if (instance == 0)
345 		pdev = &da8xx_i2c_device0;
346 	else if (instance == 1)
347 		pdev = &da8xx_i2c_device1;
348 	else
349 		return -EINVAL;
350 
351 	pdev->dev.platform_data = pdata;
352 	return platform_device_register(pdev);
353 }
354 
355 static struct resource da8xx_watchdog_resources[] = {
356 	{
357 		.start	= DA8XX_WDOG_BASE,
358 		.end	= DA8XX_WDOG_BASE + SZ_4K - 1,
359 		.flags	= IORESOURCE_MEM,
360 	},
361 };
362 
363 static struct platform_device da8xx_wdt_device = {
364 	.name		= "davinci-wdt",
365 	.id		= -1,
366 	.num_resources	= ARRAY_SIZE(da8xx_watchdog_resources),
367 	.resource	= da8xx_watchdog_resources,
368 };
369 
370 int __init da8xx_register_watchdog(void)
371 {
372 	return platform_device_register(&da8xx_wdt_device);
373 }
374 
375 static struct resource da8xx_emac_resources[] = {
376 	{
377 		.start	= DA8XX_EMAC_CPPI_PORT_BASE,
378 		.end	= DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
379 		.flags	= IORESOURCE_MEM,
380 	},
381 	{
382 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
383 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
384 		.flags	= IORESOURCE_IRQ,
385 	},
386 	{
387 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
388 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
389 		.flags	= IORESOURCE_IRQ,
390 	},
391 	{
392 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
393 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
394 		.flags	= IORESOURCE_IRQ,
395 	},
396 	{
397 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
398 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
399 		.flags	= IORESOURCE_IRQ,
400 	},
401 };
402 
403 struct emac_platform_data da8xx_emac_pdata = {
404 	.ctrl_reg_offset	= DA8XX_EMAC_CTRL_REG_OFFSET,
405 	.ctrl_mod_reg_offset	= DA8XX_EMAC_MOD_REG_OFFSET,
406 	.ctrl_ram_offset	= DA8XX_EMAC_RAM_OFFSET,
407 	.ctrl_ram_size		= DA8XX_EMAC_CTRL_RAM_SIZE,
408 	.version		= EMAC_VERSION_2,
409 };
410 
411 static struct platform_device da8xx_emac_device = {
412 	.name		= "davinci_emac",
413 	.id		= 1,
414 	.dev = {
415 		.platform_data	= &da8xx_emac_pdata,
416 	},
417 	.num_resources	= ARRAY_SIZE(da8xx_emac_resources),
418 	.resource	= da8xx_emac_resources,
419 };
420 
421 static struct resource da8xx_mdio_resources[] = {
422 	{
423 		.start	= DA8XX_EMAC_MDIO_BASE,
424 		.end	= DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
425 		.flags	= IORESOURCE_MEM,
426 	},
427 };
428 
429 static struct platform_device da8xx_mdio_device = {
430 	.name		= "davinci_mdio",
431 	.id		= 0,
432 	.num_resources	= ARRAY_SIZE(da8xx_mdio_resources),
433 	.resource	= da8xx_mdio_resources,
434 };
435 
436 int __init da8xx_register_emac(void)
437 {
438 	int ret;
439 
440 	ret = platform_device_register(&da8xx_mdio_device);
441 	if (ret < 0)
442 		return ret;
443 
444 	return platform_device_register(&da8xx_emac_device);
445 }
446 
447 static struct resource da830_mcasp1_resources[] = {
448 	{
449 		.name	= "mpu",
450 		.start	= DAVINCI_DA830_MCASP1_REG_BASE,
451 		.end	= DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
452 		.flags	= IORESOURCE_MEM,
453 	},
454 	/* TX event */
455 	{
456 		.name	= "tx",
457 		.start	= DAVINCI_DA830_DMA_MCASP1_AXEVT,
458 		.end	= DAVINCI_DA830_DMA_MCASP1_AXEVT,
459 		.flags	= IORESOURCE_DMA,
460 	},
461 	/* RX event */
462 	{
463 		.name	= "rx",
464 		.start	= DAVINCI_DA830_DMA_MCASP1_AREVT,
465 		.end	= DAVINCI_DA830_DMA_MCASP1_AREVT,
466 		.flags	= IORESOURCE_DMA,
467 	},
468 	{
469 		.name	= "common",
470 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
471 		.flags	= IORESOURCE_IRQ,
472 	},
473 };
474 
475 static struct platform_device da830_mcasp1_device = {
476 	.name		= "davinci-mcasp",
477 	.id		= 1,
478 	.num_resources	= ARRAY_SIZE(da830_mcasp1_resources),
479 	.resource	= da830_mcasp1_resources,
480 };
481 
482 static struct resource da830_mcasp2_resources[] = {
483 	{
484 		.name	= "mpu",
485 		.start	= DAVINCI_DA830_MCASP2_REG_BASE,
486 		.end	= DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
487 		.flags	= IORESOURCE_MEM,
488 	},
489 	/* TX event */
490 	{
491 		.name	= "tx",
492 		.start	= DAVINCI_DA830_DMA_MCASP2_AXEVT,
493 		.end	= DAVINCI_DA830_DMA_MCASP2_AXEVT,
494 		.flags	= IORESOURCE_DMA,
495 	},
496 	/* RX event */
497 	{
498 		.name	= "rx",
499 		.start	= DAVINCI_DA830_DMA_MCASP2_AREVT,
500 		.end	= DAVINCI_DA830_DMA_MCASP2_AREVT,
501 		.flags	= IORESOURCE_DMA,
502 	},
503 	{
504 		.name	= "common",
505 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
506 		.flags	= IORESOURCE_IRQ,
507 	},
508 };
509 
510 static struct platform_device da830_mcasp2_device = {
511 	.name		= "davinci-mcasp",
512 	.id		= 2,
513 	.num_resources	= ARRAY_SIZE(da830_mcasp2_resources),
514 	.resource	= da830_mcasp2_resources,
515 };
516 
517 static struct resource da850_mcasp_resources[] = {
518 	{
519 		.name	= "mpu",
520 		.start	= DAVINCI_DA8XX_MCASP0_REG_BASE,
521 		.end	= DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
522 		.flags	= IORESOURCE_MEM,
523 	},
524 	/* TX event */
525 	{
526 		.name	= "tx",
527 		.start	= DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
528 		.end	= DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
529 		.flags	= IORESOURCE_DMA,
530 	},
531 	/* RX event */
532 	{
533 		.name	= "rx",
534 		.start	= DAVINCI_DA8XX_DMA_MCASP0_AREVT,
535 		.end	= DAVINCI_DA8XX_DMA_MCASP0_AREVT,
536 		.flags	= IORESOURCE_DMA,
537 	},
538 	{
539 		.name	= "common",
540 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
541 		.flags	= IORESOURCE_IRQ,
542 	},
543 };
544 
545 static struct platform_device da850_mcasp_device = {
546 	.name		= "davinci-mcasp",
547 	.id		= 0,
548 	.num_resources	= ARRAY_SIZE(da850_mcasp_resources),
549 	.resource	= da850_mcasp_resources,
550 };
551 
552 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
553 {
554 	struct platform_device *pdev;
555 
556 	switch (id) {
557 	case 0:
558 		/* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
559 		pdev = &da850_mcasp_device;
560 		break;
561 	case 1:
562 		/* Valid for DA830/OMAP-L137 only */
563 		if (!cpu_is_davinci_da830())
564 			return;
565 		pdev = &da830_mcasp1_device;
566 		break;
567 	case 2:
568 		/* Valid for DA830/OMAP-L137 only */
569 		if (!cpu_is_davinci_da830())
570 			return;
571 		pdev = &da830_mcasp2_device;
572 		break;
573 	default:
574 		return;
575 	}
576 
577 	pdev->dev.platform_data = pdata;
578 	platform_device_register(pdev);
579 }
580 
581 static struct resource da8xx_pruss_resources[] = {
582 	{
583 		.start	= DA8XX_PRUSS_MEM_BASE,
584 		.end	= DA8XX_PRUSS_MEM_BASE + 0xFFFF,
585 		.flags	= IORESOURCE_MEM,
586 	},
587 	{
588 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
589 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
590 		.flags	= IORESOURCE_IRQ,
591 	},
592 	{
593 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
594 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
595 		.flags	= IORESOURCE_IRQ,
596 	},
597 	{
598 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
599 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
600 		.flags	= IORESOURCE_IRQ,
601 	},
602 	{
603 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
604 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
605 		.flags	= IORESOURCE_IRQ,
606 	},
607 	{
608 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
609 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
610 		.flags	= IORESOURCE_IRQ,
611 	},
612 	{
613 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
614 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
615 		.flags	= IORESOURCE_IRQ,
616 	},
617 	{
618 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
619 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
620 		.flags	= IORESOURCE_IRQ,
621 	},
622 	{
623 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
624 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
625 		.flags	= IORESOURCE_IRQ,
626 	},
627 };
628 
629 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
630 	.pintc_base	= 0x4000,
631 };
632 
633 static struct platform_device da8xx_uio_pruss_dev = {
634 	.name		= "pruss_uio",
635 	.id		= -1,
636 	.num_resources	= ARRAY_SIZE(da8xx_pruss_resources),
637 	.resource	= da8xx_pruss_resources,
638 	.dev		= {
639 		.coherent_dma_mask	= DMA_BIT_MASK(32),
640 		.platform_data		= &da8xx_uio_pruss_pdata,
641 	}
642 };
643 
644 int __init da8xx_register_uio_pruss(void)
645 {
646 	da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
647 	return platform_device_register(&da8xx_uio_pruss_dev);
648 }
649 
650 static struct lcd_ctrl_config lcd_cfg = {
651 	.panel_shade		= COLOR_ACTIVE,
652 	.bpp			= 16,
653 };
654 
655 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
656 	.manu_name		= "sharp",
657 	.controller_data	= &lcd_cfg,
658 	.type			= "Sharp_LCD035Q3DG01",
659 };
660 
661 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
662 	.manu_name		= "sharp",
663 	.controller_data	= &lcd_cfg,
664 	.type			= "Sharp_LK043T1DG01",
665 };
666 
667 static struct resource da8xx_lcdc_resources[] = {
668 	[0] = { /* registers */
669 		.start  = DA8XX_LCD_CNTRL_BASE,
670 		.end    = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
671 		.flags  = IORESOURCE_MEM,
672 	},
673 	[1] = { /* interrupt */
674 		.start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
675 		.end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
676 		.flags  = IORESOURCE_IRQ,
677 	},
678 };
679 
680 static struct platform_device da8xx_lcdc_device = {
681 	.name		= "da8xx_lcdc",
682 	.id		= 0,
683 	.num_resources	= ARRAY_SIZE(da8xx_lcdc_resources),
684 	.resource	= da8xx_lcdc_resources,
685 	.dev		= {
686 		.coherent_dma_mask	= DMA_BIT_MASK(32),
687 	}
688 };
689 
690 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
691 {
692 	da8xx_lcdc_device.dev.platform_data = pdata;
693 	return platform_device_register(&da8xx_lcdc_device);
694 }
695 
696 static struct resource da8xx_gpio_resources[] = {
697 	{ /* registers */
698 		.start	= DA8XX_GPIO_BASE,
699 		.end	= DA8XX_GPIO_BASE + SZ_4K - 1,
700 		.flags	= IORESOURCE_MEM,
701 	},
702 	{ /* interrupt */
703 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
704 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
705 		.flags	= IORESOURCE_IRQ,
706 	},
707 	{
708 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
709 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
710 		.flags	= IORESOURCE_IRQ,
711 	},
712 	{
713 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
714 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
715 		.flags	= IORESOURCE_IRQ,
716 	},
717 	{
718 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
719 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
720 		.flags	= IORESOURCE_IRQ,
721 	},
722 	{
723 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
724 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
725 		.flags	= IORESOURCE_IRQ,
726 	},
727 	{
728 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
729 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
730 		.flags	= IORESOURCE_IRQ,
731 	},
732 	{
733 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
734 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
735 		.flags	= IORESOURCE_IRQ,
736 	},
737 	{
738 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
739 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
740 		.flags	= IORESOURCE_IRQ,
741 	},
742 	{
743 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
744 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
745 		.flags	= IORESOURCE_IRQ,
746 	},
747 };
748 
749 static struct platform_device da8xx_gpio_device = {
750 	.name		= "davinci_gpio",
751 	.id		= -1,
752 	.num_resources	= ARRAY_SIZE(da8xx_gpio_resources),
753 	.resource	= da8xx_gpio_resources,
754 };
755 
756 int __init da8xx_register_gpio(void *pdata)
757 {
758 	da8xx_gpio_device.dev.platform_data = pdata;
759 	return platform_device_register(&da8xx_gpio_device);
760 }
761 
762 static struct resource da8xx_mmcsd0_resources[] = {
763 	{		/* registers */
764 		.start	= DA8XX_MMCSD0_BASE,
765 		.end	= DA8XX_MMCSD0_BASE + SZ_4K - 1,
766 		.flags	= IORESOURCE_MEM,
767 	},
768 	{		/* interrupt */
769 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
770 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
771 		.flags	= IORESOURCE_IRQ,
772 	},
773 };
774 
775 static struct platform_device da8xx_mmcsd0_device = {
776 	.name		= "da830-mmc",
777 	.id		= 0,
778 	.num_resources	= ARRAY_SIZE(da8xx_mmcsd0_resources),
779 	.resource	= da8xx_mmcsd0_resources,
780 };
781 
782 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
783 {
784 	da8xx_mmcsd0_device.dev.platform_data = config;
785 	return platform_device_register(&da8xx_mmcsd0_device);
786 }
787 
788 #ifdef CONFIG_ARCH_DAVINCI_DA850
789 static struct resource da850_mmcsd1_resources[] = {
790 	{		/* registers */
791 		.start	= DA850_MMCSD1_BASE,
792 		.end	= DA850_MMCSD1_BASE + SZ_4K - 1,
793 		.flags	= IORESOURCE_MEM,
794 	},
795 	{		/* interrupt */
796 		.start	= DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
797 		.end	= DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
798 		.flags	= IORESOURCE_IRQ,
799 	},
800 };
801 
802 static struct platform_device da850_mmcsd1_device = {
803 	.name		= "da830-mmc",
804 	.id		= 1,
805 	.num_resources	= ARRAY_SIZE(da850_mmcsd1_resources),
806 	.resource	= da850_mmcsd1_resources,
807 };
808 
809 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
810 {
811 	da850_mmcsd1_device.dev.platform_data = config;
812 	return platform_device_register(&da850_mmcsd1_device);
813 }
814 #endif
815 
816 static struct resource da8xx_rproc_resources[] = {
817 	{ /* DSP boot address */
818 		.name		= "host1cfg",
819 		.start		= DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
820 		.end		= DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
821 		.flags		= IORESOURCE_MEM,
822 	},
823 	{ /* DSP interrupt registers */
824 		.name		= "chipsig",
825 		.start		= DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
826 		.end		= DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
827 		.flags		= IORESOURCE_MEM,
828 	},
829 	{ /* DSP L2 RAM */
830 		.name		= "l2sram",
831 		.start		= DA8XX_DSP_L2_RAM_BASE,
832 		.end		= DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
833 		.flags		= IORESOURCE_MEM,
834 	},
835 	{ /* DSP L1P RAM */
836 		.name		= "l1pram",
837 		.start		= DA8XX_DSP_L1P_RAM_BASE,
838 		.end		= DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
839 		.flags		= IORESOURCE_MEM,
840 	},
841 	{ /* DSP L1D RAM */
842 		.name		= "l1dram",
843 		.start		= DA8XX_DSP_L1D_RAM_BASE,
844 		.end		= DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
845 		.flags		= IORESOURCE_MEM,
846 	},
847 	{ /* dsp irq */
848 		.start		= DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
849 		.end		= DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
850 		.flags		= IORESOURCE_IRQ,
851 	},
852 };
853 
854 static struct platform_device da8xx_dsp = {
855 	.name	= "davinci-rproc",
856 	.dev	= {
857 		.coherent_dma_mask	= DMA_BIT_MASK(32),
858 	},
859 	.num_resources	= ARRAY_SIZE(da8xx_rproc_resources),
860 	.resource	= da8xx_rproc_resources,
861 };
862 
863 static bool rproc_mem_inited __initdata;
864 
865 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
866 
867 static phys_addr_t rproc_base __initdata;
868 static unsigned long rproc_size __initdata;
869 
870 static int __init early_rproc_mem(char *p)
871 {
872 	char *endp;
873 
874 	if (p == NULL)
875 		return 0;
876 
877 	rproc_size = memparse(p, &endp);
878 	if (*endp == '@')
879 		rproc_base = memparse(endp + 1, NULL);
880 
881 	return 0;
882 }
883 early_param("rproc_mem", early_rproc_mem);
884 
885 void __init da8xx_rproc_reserve_cma(void)
886 {
887 	int ret;
888 
889 	if (!rproc_base || !rproc_size) {
890 		pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
891 		       "    'nn' and 'address' must both be non-zero\n",
892 		       __func__);
893 
894 		return;
895 	}
896 
897 	pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
898 		__func__, rproc_size, (unsigned long)rproc_base);
899 
900 	ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
901 	if (ret)
902 		pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
903 	else
904 		rproc_mem_inited = true;
905 }
906 
907 #else
908 
909 void __init da8xx_rproc_reserve_cma(void)
910 {
911 }
912 
913 #endif
914 
915 int __init da8xx_register_rproc(void)
916 {
917 	int ret;
918 
919 	if (!rproc_mem_inited) {
920 		pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
921 			__func__);
922 		return -ENOMEM;
923 	}
924 
925 	ret = platform_device_register(&da8xx_dsp);
926 	if (ret)
927 		pr_err("%s: can't register DSP device: %d\n", __func__, ret);
928 
929 	return ret;
930 };
931 
932 static struct resource da8xx_rtc_resources[] = {
933 	{
934 		.start		= DA8XX_RTC_BASE,
935 		.end		= DA8XX_RTC_BASE + SZ_4K - 1,
936 		.flags		= IORESOURCE_MEM,
937 	},
938 	{ /* timer irq */
939 		.start		= DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
940 		.end		= DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
941 		.flags		= IORESOURCE_IRQ,
942 	},
943 	{ /* alarm irq */
944 		.start		= DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
945 		.end		= DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
946 		.flags		= IORESOURCE_IRQ,
947 	},
948 };
949 
950 static struct platform_device da8xx_rtc_device = {
951 	.name           = "da830-rtc",
952 	.id             = -1,
953 	.num_resources	= ARRAY_SIZE(da8xx_rtc_resources),
954 	.resource	= da8xx_rtc_resources,
955 };
956 
957 int da8xx_register_rtc(void)
958 {
959 	return platform_device_register(&da8xx_rtc_device);
960 }
961 
962 static void __iomem *da8xx_ddr2_ctlr_base;
963 void __iomem * __init da8xx_get_mem_ctlr(void)
964 {
965 	if (da8xx_ddr2_ctlr_base)
966 		return da8xx_ddr2_ctlr_base;
967 
968 	da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
969 	if (!da8xx_ddr2_ctlr_base)
970 		pr_warn("%s: Unable to map DDR2 controller", __func__);
971 
972 	return da8xx_ddr2_ctlr_base;
973 }
974 
975 static struct resource da8xx_cpuidle_resources[] = {
976 	{
977 		.start		= DA8XX_DDR2_CTL_BASE,
978 		.end		= DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
979 		.flags		= IORESOURCE_MEM,
980 	},
981 };
982 
983 /* DA8XX devices support DDR2 power down */
984 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
985 	.ddr2_pdown	= 1,
986 };
987 
988 
989 static struct platform_device da8xx_cpuidle_device = {
990 	.name			= "cpuidle-davinci",
991 	.num_resources		= ARRAY_SIZE(da8xx_cpuidle_resources),
992 	.resource		= da8xx_cpuidle_resources,
993 	.dev = {
994 		.platform_data	= &da8xx_cpuidle_pdata,
995 	},
996 };
997 
998 int __init da8xx_register_cpuidle(void)
999 {
1000 	da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
1001 
1002 	return platform_device_register(&da8xx_cpuidle_device);
1003 }
1004 
1005 static struct resource da8xx_spi0_resources[] = {
1006 	[0] = {
1007 		.start	= DA8XX_SPI0_BASE,
1008 		.end	= DA8XX_SPI0_BASE + SZ_4K - 1,
1009 		.flags	= IORESOURCE_MEM,
1010 	},
1011 	[1] = {
1012 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
1013 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
1014 		.flags	= IORESOURCE_IRQ,
1015 	},
1016 };
1017 
1018 static struct resource da8xx_spi1_resources[] = {
1019 	[0] = {
1020 		.start	= DA830_SPI1_BASE,
1021 		.end	= DA830_SPI1_BASE + SZ_4K - 1,
1022 		.flags	= IORESOURCE_MEM,
1023 	},
1024 	[1] = {
1025 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
1026 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
1027 		.flags	= IORESOURCE_IRQ,
1028 	},
1029 };
1030 
1031 static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
1032 	[0] = {
1033 		.version	= SPI_VERSION_2,
1034 		.intr_line	= 1,
1035 		.dma_event_q	= EVENTQ_0,
1036 		.prescaler_limit = 2,
1037 	},
1038 	[1] = {
1039 		.version	= SPI_VERSION_2,
1040 		.intr_line	= 1,
1041 		.dma_event_q	= EVENTQ_0,
1042 		.prescaler_limit = 2,
1043 	},
1044 };
1045 
1046 static struct platform_device da8xx_spi_device[] = {
1047 	[0] = {
1048 		.name		= "spi_davinci",
1049 		.id		= 0,
1050 		.num_resources	= ARRAY_SIZE(da8xx_spi0_resources),
1051 		.resource	= da8xx_spi0_resources,
1052 		.dev		= {
1053 			.platform_data = &da8xx_spi_pdata[0],
1054 		},
1055 	},
1056 	[1] = {
1057 		.name		= "spi_davinci",
1058 		.id		= 1,
1059 		.num_resources	= ARRAY_SIZE(da8xx_spi1_resources),
1060 		.resource	= da8xx_spi1_resources,
1061 		.dev		= {
1062 			.platform_data = &da8xx_spi_pdata[1],
1063 		},
1064 	},
1065 };
1066 
1067 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
1068 {
1069 	if (instance < 0 || instance > 1)
1070 		return -EINVAL;
1071 
1072 	da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
1073 
1074 	if (instance == 1 && cpu_is_davinci_da850()) {
1075 		da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
1076 		da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
1077 	}
1078 
1079 	return platform_device_register(&da8xx_spi_device[instance]);
1080 }
1081 
1082 #ifdef CONFIG_ARCH_DAVINCI_DA850
1083 int __init da850_register_sata_refclk(int rate)
1084 {
1085 	struct clk *clk;
1086 
1087 	clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate);
1088 	if (IS_ERR(clk))
1089 		return PTR_ERR(clk);
1090 
1091 	return clk_register_clkdev(clk, "refclk", "ahci_da850");
1092 }
1093 
1094 static struct resource da850_sata_resources[] = {
1095 	{
1096 		.start	= DA850_SATA_BASE,
1097 		.end	= DA850_SATA_BASE + 0x1fff,
1098 		.flags	= IORESOURCE_MEM,
1099 	},
1100 	{
1101 		.start	= DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
1102 		.end	= DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
1103 		.flags	= IORESOURCE_MEM,
1104 	},
1105 	{
1106 		.start	= DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT),
1107 		.flags	= IORESOURCE_IRQ,
1108 	},
1109 };
1110 
1111 static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1112 
1113 static struct platform_device da850_sata_device = {
1114 	.name	= "ahci_da850",
1115 	.id	= -1,
1116 	.dev	= {
1117 		.dma_mask		= &da850_sata_dmamask,
1118 		.coherent_dma_mask	= DMA_BIT_MASK(32),
1119 	},
1120 	.num_resources	= ARRAY_SIZE(da850_sata_resources),
1121 	.resource	= da850_sata_resources,
1122 };
1123 
1124 int __init da850_register_sata(unsigned long refclkpn)
1125 {
1126 	int ret;
1127 
1128 	ret = da850_register_sata_refclk(refclkpn);
1129 	if (ret)
1130 		return ret;
1131 
1132 	return platform_device_register(&da850_sata_device);
1133 }
1134 #endif
1135 
1136 static struct regmap *da8xx_cfgchip;
1137 
1138 static const struct regmap_config da8xx_cfgchip_config __initconst = {
1139 	.name		= "cfgchip",
1140 	.reg_bits	= 32,
1141 	.val_bits	= 32,
1142 	.reg_stride	= 4,
1143 	.max_register	= DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG,
1144 };
1145 
1146 /**
1147  * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap
1148  *
1149  * This is for use on non-DT boards only. For DT boards, use
1150  * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip")
1151  *
1152  * Returns: Pointer to the CFGCHIP regmap or negative error code.
1153  */
1154 struct regmap * __init da8xx_get_cfgchip(void)
1155 {
1156 	if (IS_ERR_OR_NULL(da8xx_cfgchip))
1157 		da8xx_cfgchip = regmap_init_mmio(NULL,
1158 					DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG),
1159 					&da8xx_cfgchip_config);
1160 
1161 	return da8xx_cfgchip;
1162 }
1163