1 /* 2 * DA8XX/OMAP L1XX platform device data 3 * 4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> 5 * Derived from code that was: 6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 #include <linux/init.h> 14 #include <linux/platform_device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/serial_8250.h> 17 #include <linux/ahci_platform.h> 18 #include <linux/clk.h> 19 20 #include <mach/cputype.h> 21 #include <mach/common.h> 22 #include <mach/time.h> 23 #include <mach/da8xx.h> 24 #include <mach/cpuidle.h> 25 #include <mach/sram.h> 26 27 #include "clock.h" 28 #include "asp.h" 29 30 #define DA8XX_TPCC_BASE 0x01c00000 31 #define DA8XX_TPTC0_BASE 0x01c08000 32 #define DA8XX_TPTC1_BASE 0x01c08400 33 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ 34 #define DA8XX_I2C0_BASE 0x01c22000 35 #define DA8XX_RTC_BASE 0x01c23000 36 #define DA8XX_PRUSS_MEM_BASE 0x01c30000 37 #define DA8XX_MMCSD0_BASE 0x01c40000 38 #define DA8XX_SPI0_BASE 0x01c41000 39 #define DA830_SPI1_BASE 0x01e12000 40 #define DA8XX_LCD_CNTRL_BASE 0x01e13000 41 #define DA850_SATA_BASE 0x01e18000 42 #define DA850_MMCSD1_BASE 0x01e1b000 43 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 44 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 45 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 46 #define DA8XX_EMAC_MDIO_BASE 0x01e24000 47 #define DA8XX_I2C1_BASE 0x01e28000 48 #define DA850_TPCC1_BASE 0x01e30000 49 #define DA850_TPTC2_BASE 0x01e38000 50 #define DA850_SPI1_BASE 0x01f0e000 51 #define DA8XX_DDR2_CTL_BASE 0xb0000000 52 53 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 54 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 55 #define DA8XX_EMAC_RAM_OFFSET 0x0000 56 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K 57 58 #define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14) 59 #define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15) 60 #define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16) 61 #define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17) 62 #define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18) 63 #define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19) 64 #define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28) 65 #define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29) 66 67 void __iomem *da8xx_syscfg0_base; 68 void __iomem *da8xx_syscfg1_base; 69 70 static struct plat_serial8250_port da8xx_serial_pdata[] = { 71 { 72 .mapbase = DA8XX_UART0_BASE, 73 .irq = IRQ_DA8XX_UARTINT0, 74 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 75 UPF_IOREMAP, 76 .iotype = UPIO_MEM, 77 .regshift = 2, 78 }, 79 { 80 .mapbase = DA8XX_UART1_BASE, 81 .irq = IRQ_DA8XX_UARTINT1, 82 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 83 UPF_IOREMAP, 84 .iotype = UPIO_MEM, 85 .regshift = 2, 86 }, 87 { 88 .mapbase = DA8XX_UART2_BASE, 89 .irq = IRQ_DA8XX_UARTINT2, 90 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 91 UPF_IOREMAP, 92 .iotype = UPIO_MEM, 93 .regshift = 2, 94 }, 95 { 96 .flags = 0, 97 }, 98 }; 99 100 struct platform_device da8xx_serial_device = { 101 .name = "serial8250", 102 .id = PLAT8250_DEV_PLATFORM, 103 .dev = { 104 .platform_data = da8xx_serial_pdata, 105 }, 106 }; 107 108 static const s8 da8xx_queue_tc_mapping[][2] = { 109 /* {event queue no, TC no} */ 110 {0, 0}, 111 {1, 1}, 112 {-1, -1} 113 }; 114 115 static const s8 da8xx_queue_priority_mapping[][2] = { 116 /* {event queue no, Priority} */ 117 {0, 3}, 118 {1, 7}, 119 {-1, -1} 120 }; 121 122 static const s8 da850_queue_tc_mapping[][2] = { 123 /* {event queue no, TC no} */ 124 {0, 0}, 125 {-1, -1} 126 }; 127 128 static const s8 da850_queue_priority_mapping[][2] = { 129 /* {event queue no, Priority} */ 130 {0, 3}, 131 {-1, -1} 132 }; 133 134 static struct edma_soc_info da830_edma_cc0_info = { 135 .n_channel = 32, 136 .n_region = 4, 137 .n_slot = 128, 138 .n_tc = 2, 139 .n_cc = 1, 140 .queue_tc_mapping = da8xx_queue_tc_mapping, 141 .queue_priority_mapping = da8xx_queue_priority_mapping, 142 .default_queue = EVENTQ_1, 143 }; 144 145 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = { 146 &da830_edma_cc0_info, 147 }; 148 149 static struct edma_soc_info da850_edma_cc_info[] = { 150 { 151 .n_channel = 32, 152 .n_region = 4, 153 .n_slot = 128, 154 .n_tc = 2, 155 .n_cc = 1, 156 .queue_tc_mapping = da8xx_queue_tc_mapping, 157 .queue_priority_mapping = da8xx_queue_priority_mapping, 158 .default_queue = EVENTQ_1, 159 }, 160 { 161 .n_channel = 32, 162 .n_region = 4, 163 .n_slot = 128, 164 .n_tc = 1, 165 .n_cc = 1, 166 .queue_tc_mapping = da850_queue_tc_mapping, 167 .queue_priority_mapping = da850_queue_priority_mapping, 168 .default_queue = EVENTQ_0, 169 }, 170 }; 171 172 static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = { 173 &da850_edma_cc_info[0], 174 &da850_edma_cc_info[1], 175 }; 176 177 static struct resource da830_edma_resources[] = { 178 { 179 .name = "edma_cc0", 180 .start = DA8XX_TPCC_BASE, 181 .end = DA8XX_TPCC_BASE + SZ_32K - 1, 182 .flags = IORESOURCE_MEM, 183 }, 184 { 185 .name = "edma_tc0", 186 .start = DA8XX_TPTC0_BASE, 187 .end = DA8XX_TPTC0_BASE + SZ_1K - 1, 188 .flags = IORESOURCE_MEM, 189 }, 190 { 191 .name = "edma_tc1", 192 .start = DA8XX_TPTC1_BASE, 193 .end = DA8XX_TPTC1_BASE + SZ_1K - 1, 194 .flags = IORESOURCE_MEM, 195 }, 196 { 197 .name = "edma0", 198 .start = IRQ_DA8XX_CCINT0, 199 .flags = IORESOURCE_IRQ, 200 }, 201 { 202 .name = "edma0_err", 203 .start = IRQ_DA8XX_CCERRINT, 204 .flags = IORESOURCE_IRQ, 205 }, 206 }; 207 208 static struct resource da850_edma_resources[] = { 209 { 210 .name = "edma_cc0", 211 .start = DA8XX_TPCC_BASE, 212 .end = DA8XX_TPCC_BASE + SZ_32K - 1, 213 .flags = IORESOURCE_MEM, 214 }, 215 { 216 .name = "edma_tc0", 217 .start = DA8XX_TPTC0_BASE, 218 .end = DA8XX_TPTC0_BASE + SZ_1K - 1, 219 .flags = IORESOURCE_MEM, 220 }, 221 { 222 .name = "edma_tc1", 223 .start = DA8XX_TPTC1_BASE, 224 .end = DA8XX_TPTC1_BASE + SZ_1K - 1, 225 .flags = IORESOURCE_MEM, 226 }, 227 { 228 .name = "edma_cc1", 229 .start = DA850_TPCC1_BASE, 230 .end = DA850_TPCC1_BASE + SZ_32K - 1, 231 .flags = IORESOURCE_MEM, 232 }, 233 { 234 .name = "edma_tc2", 235 .start = DA850_TPTC2_BASE, 236 .end = DA850_TPTC2_BASE + SZ_1K - 1, 237 .flags = IORESOURCE_MEM, 238 }, 239 { 240 .name = "edma0", 241 .start = IRQ_DA8XX_CCINT0, 242 .flags = IORESOURCE_IRQ, 243 }, 244 { 245 .name = "edma0_err", 246 .start = IRQ_DA8XX_CCERRINT, 247 .flags = IORESOURCE_IRQ, 248 }, 249 { 250 .name = "edma1", 251 .start = IRQ_DA850_CCINT1, 252 .flags = IORESOURCE_IRQ, 253 }, 254 { 255 .name = "edma1_err", 256 .start = IRQ_DA850_CCERRINT1, 257 .flags = IORESOURCE_IRQ, 258 }, 259 }; 260 261 static struct platform_device da830_edma_device = { 262 .name = "edma", 263 .id = -1, 264 .dev = { 265 .platform_data = da830_edma_info, 266 }, 267 .num_resources = ARRAY_SIZE(da830_edma_resources), 268 .resource = da830_edma_resources, 269 }; 270 271 static struct platform_device da850_edma_device = { 272 .name = "edma", 273 .id = -1, 274 .dev = { 275 .platform_data = da850_edma_info, 276 }, 277 .num_resources = ARRAY_SIZE(da850_edma_resources), 278 .resource = da850_edma_resources, 279 }; 280 281 int __init da830_register_edma(struct edma_rsv_info *rsv) 282 { 283 da830_edma_cc0_info.rsv = rsv; 284 285 return platform_device_register(&da830_edma_device); 286 } 287 288 int __init da850_register_edma(struct edma_rsv_info *rsv[2]) 289 { 290 if (rsv) { 291 da850_edma_cc_info[0].rsv = rsv[0]; 292 da850_edma_cc_info[1].rsv = rsv[1]; 293 } 294 295 return platform_device_register(&da850_edma_device); 296 } 297 298 static struct resource da8xx_i2c_resources0[] = { 299 { 300 .start = DA8XX_I2C0_BASE, 301 .end = DA8XX_I2C0_BASE + SZ_4K - 1, 302 .flags = IORESOURCE_MEM, 303 }, 304 { 305 .start = IRQ_DA8XX_I2CINT0, 306 .end = IRQ_DA8XX_I2CINT0, 307 .flags = IORESOURCE_IRQ, 308 }, 309 }; 310 311 static struct platform_device da8xx_i2c_device0 = { 312 .name = "i2c_davinci", 313 .id = 1, 314 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), 315 .resource = da8xx_i2c_resources0, 316 }; 317 318 static struct resource da8xx_i2c_resources1[] = { 319 { 320 .start = DA8XX_I2C1_BASE, 321 .end = DA8XX_I2C1_BASE + SZ_4K - 1, 322 .flags = IORESOURCE_MEM, 323 }, 324 { 325 .start = IRQ_DA8XX_I2CINT1, 326 .end = IRQ_DA8XX_I2CINT1, 327 .flags = IORESOURCE_IRQ, 328 }, 329 }; 330 331 static struct platform_device da8xx_i2c_device1 = { 332 .name = "i2c_davinci", 333 .id = 2, 334 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), 335 .resource = da8xx_i2c_resources1, 336 }; 337 338 int __init da8xx_register_i2c(int instance, 339 struct davinci_i2c_platform_data *pdata) 340 { 341 struct platform_device *pdev; 342 343 if (instance == 0) 344 pdev = &da8xx_i2c_device0; 345 else if (instance == 1) 346 pdev = &da8xx_i2c_device1; 347 else 348 return -EINVAL; 349 350 pdev->dev.platform_data = pdata; 351 return platform_device_register(pdev); 352 } 353 354 static struct resource da8xx_watchdog_resources[] = { 355 { 356 .start = DA8XX_WDOG_BASE, 357 .end = DA8XX_WDOG_BASE + SZ_4K - 1, 358 .flags = IORESOURCE_MEM, 359 }, 360 }; 361 362 static struct platform_device da8xx_wdt_device = { 363 .name = "watchdog", 364 .id = -1, 365 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), 366 .resource = da8xx_watchdog_resources, 367 }; 368 369 void da8xx_restart(char mode, const char *cmd) 370 { 371 struct device *dev; 372 373 dev = bus_find_device_by_name(&platform_bus_type, NULL, "watchdog"); 374 if (!dev) { 375 pr_err("%s: failed to find watchdog device\n", __func__); 376 return; 377 } 378 379 davinci_watchdog_reset(to_platform_device(dev)); 380 } 381 382 int __init da8xx_register_watchdog(void) 383 { 384 return platform_device_register(&da8xx_wdt_device); 385 } 386 387 static struct resource da8xx_emac_resources[] = { 388 { 389 .start = DA8XX_EMAC_CPPI_PORT_BASE, 390 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1, 391 .flags = IORESOURCE_MEM, 392 }, 393 { 394 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE, 395 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE, 396 .flags = IORESOURCE_IRQ, 397 }, 398 { 399 .start = IRQ_DA8XX_C0_RX_PULSE, 400 .end = IRQ_DA8XX_C0_RX_PULSE, 401 .flags = IORESOURCE_IRQ, 402 }, 403 { 404 .start = IRQ_DA8XX_C0_TX_PULSE, 405 .end = IRQ_DA8XX_C0_TX_PULSE, 406 .flags = IORESOURCE_IRQ, 407 }, 408 { 409 .start = IRQ_DA8XX_C0_MISC_PULSE, 410 .end = IRQ_DA8XX_C0_MISC_PULSE, 411 .flags = IORESOURCE_IRQ, 412 }, 413 }; 414 415 struct emac_platform_data da8xx_emac_pdata = { 416 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, 417 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, 418 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, 419 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, 420 .version = EMAC_VERSION_2, 421 }; 422 423 static struct platform_device da8xx_emac_device = { 424 .name = "davinci_emac", 425 .id = 1, 426 .dev = { 427 .platform_data = &da8xx_emac_pdata, 428 }, 429 .num_resources = ARRAY_SIZE(da8xx_emac_resources), 430 .resource = da8xx_emac_resources, 431 }; 432 433 static struct resource da8xx_mdio_resources[] = { 434 { 435 .start = DA8XX_EMAC_MDIO_BASE, 436 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1, 437 .flags = IORESOURCE_MEM, 438 }, 439 }; 440 441 static struct platform_device da8xx_mdio_device = { 442 .name = "davinci_mdio", 443 .id = 0, 444 .num_resources = ARRAY_SIZE(da8xx_mdio_resources), 445 .resource = da8xx_mdio_resources, 446 }; 447 448 int __init da8xx_register_emac(void) 449 { 450 int ret; 451 452 ret = platform_device_register(&da8xx_mdio_device); 453 if (ret < 0) 454 return ret; 455 ret = platform_device_register(&da8xx_emac_device); 456 if (ret < 0) 457 return ret; 458 ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev), 459 NULL, &da8xx_emac_device.dev); 460 return ret; 461 } 462 463 static struct resource da830_mcasp1_resources[] = { 464 { 465 .name = "mcasp1", 466 .start = DAVINCI_DA830_MCASP1_REG_BASE, 467 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, 468 .flags = IORESOURCE_MEM, 469 }, 470 /* TX event */ 471 { 472 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, 473 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, 474 .flags = IORESOURCE_DMA, 475 }, 476 /* RX event */ 477 { 478 .start = DAVINCI_DA830_DMA_MCASP1_AREVT, 479 .end = DAVINCI_DA830_DMA_MCASP1_AREVT, 480 .flags = IORESOURCE_DMA, 481 }, 482 }; 483 484 static struct platform_device da830_mcasp1_device = { 485 .name = "davinci-mcasp", 486 .id = 1, 487 .num_resources = ARRAY_SIZE(da830_mcasp1_resources), 488 .resource = da830_mcasp1_resources, 489 }; 490 491 static struct resource da850_mcasp_resources[] = { 492 { 493 .name = "mcasp", 494 .start = DAVINCI_DA8XX_MCASP0_REG_BASE, 495 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, 496 .flags = IORESOURCE_MEM, 497 }, 498 /* TX event */ 499 { 500 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 501 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 502 .flags = IORESOURCE_DMA, 503 }, 504 /* RX event */ 505 { 506 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 507 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 508 .flags = IORESOURCE_DMA, 509 }, 510 }; 511 512 static struct platform_device da850_mcasp_device = { 513 .name = "davinci-mcasp", 514 .id = 0, 515 .num_resources = ARRAY_SIZE(da850_mcasp_resources), 516 .resource = da850_mcasp_resources, 517 }; 518 519 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) 520 { 521 /* DA830/OMAP-L137 has 3 instances of McASP */ 522 if (cpu_is_davinci_da830() && id == 1) { 523 da830_mcasp1_device.dev.platform_data = pdata; 524 platform_device_register(&da830_mcasp1_device); 525 } else if (cpu_is_davinci_da850()) { 526 da850_mcasp_device.dev.platform_data = pdata; 527 platform_device_register(&da850_mcasp_device); 528 } 529 } 530 531 static struct resource da8xx_pruss_resources[] = { 532 { 533 .start = DA8XX_PRUSS_MEM_BASE, 534 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF, 535 .flags = IORESOURCE_MEM, 536 }, 537 { 538 .start = IRQ_DA8XX_EVTOUT0, 539 .end = IRQ_DA8XX_EVTOUT0, 540 .flags = IORESOURCE_IRQ, 541 }, 542 { 543 .start = IRQ_DA8XX_EVTOUT1, 544 .end = IRQ_DA8XX_EVTOUT1, 545 .flags = IORESOURCE_IRQ, 546 }, 547 { 548 .start = IRQ_DA8XX_EVTOUT2, 549 .end = IRQ_DA8XX_EVTOUT2, 550 .flags = IORESOURCE_IRQ, 551 }, 552 { 553 .start = IRQ_DA8XX_EVTOUT3, 554 .end = IRQ_DA8XX_EVTOUT3, 555 .flags = IORESOURCE_IRQ, 556 }, 557 { 558 .start = IRQ_DA8XX_EVTOUT4, 559 .end = IRQ_DA8XX_EVTOUT4, 560 .flags = IORESOURCE_IRQ, 561 }, 562 { 563 .start = IRQ_DA8XX_EVTOUT5, 564 .end = IRQ_DA8XX_EVTOUT5, 565 .flags = IORESOURCE_IRQ, 566 }, 567 { 568 .start = IRQ_DA8XX_EVTOUT6, 569 .end = IRQ_DA8XX_EVTOUT6, 570 .flags = IORESOURCE_IRQ, 571 }, 572 { 573 .start = IRQ_DA8XX_EVTOUT7, 574 .end = IRQ_DA8XX_EVTOUT7, 575 .flags = IORESOURCE_IRQ, 576 }, 577 }; 578 579 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = { 580 .pintc_base = 0x4000, 581 }; 582 583 static struct platform_device da8xx_uio_pruss_dev = { 584 .name = "pruss_uio", 585 .id = -1, 586 .num_resources = ARRAY_SIZE(da8xx_pruss_resources), 587 .resource = da8xx_pruss_resources, 588 .dev = { 589 .coherent_dma_mask = DMA_BIT_MASK(32), 590 .platform_data = &da8xx_uio_pruss_pdata, 591 } 592 }; 593 594 int __init da8xx_register_uio_pruss(void) 595 { 596 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool(); 597 return platform_device_register(&da8xx_uio_pruss_dev); 598 } 599 600 static struct lcd_ctrl_config lcd_cfg = { 601 .panel_shade = COLOR_ACTIVE, 602 .bpp = 16, 603 }; 604 605 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = { 606 .manu_name = "sharp", 607 .controller_data = &lcd_cfg, 608 .type = "Sharp_LCD035Q3DG01", 609 }; 610 611 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = { 612 .manu_name = "sharp", 613 .controller_data = &lcd_cfg, 614 .type = "Sharp_LK043T1DG01", 615 }; 616 617 static struct resource da8xx_lcdc_resources[] = { 618 [0] = { /* registers */ 619 .start = DA8XX_LCD_CNTRL_BASE, 620 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, 621 .flags = IORESOURCE_MEM, 622 }, 623 [1] = { /* interrupt */ 624 .start = IRQ_DA8XX_LCDINT, 625 .end = IRQ_DA8XX_LCDINT, 626 .flags = IORESOURCE_IRQ, 627 }, 628 }; 629 630 static struct platform_device da8xx_lcdc_device = { 631 .name = "da8xx_lcdc", 632 .id = 0, 633 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), 634 .resource = da8xx_lcdc_resources, 635 }; 636 637 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) 638 { 639 da8xx_lcdc_device.dev.platform_data = pdata; 640 return platform_device_register(&da8xx_lcdc_device); 641 } 642 643 static struct resource da8xx_mmcsd0_resources[] = { 644 { /* registers */ 645 .start = DA8XX_MMCSD0_BASE, 646 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, 647 .flags = IORESOURCE_MEM, 648 }, 649 { /* interrupt */ 650 .start = IRQ_DA8XX_MMCSDINT0, 651 .end = IRQ_DA8XX_MMCSDINT0, 652 .flags = IORESOURCE_IRQ, 653 }, 654 { /* DMA RX */ 655 .start = DA8XX_DMA_MMCSD0_RX, 656 .end = DA8XX_DMA_MMCSD0_RX, 657 .flags = IORESOURCE_DMA, 658 }, 659 { /* DMA TX */ 660 .start = DA8XX_DMA_MMCSD0_TX, 661 .end = DA8XX_DMA_MMCSD0_TX, 662 .flags = IORESOURCE_DMA, 663 }, 664 }; 665 666 static struct platform_device da8xx_mmcsd0_device = { 667 .name = "davinci_mmc", 668 .id = 0, 669 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), 670 .resource = da8xx_mmcsd0_resources, 671 }; 672 673 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) 674 { 675 da8xx_mmcsd0_device.dev.platform_data = config; 676 return platform_device_register(&da8xx_mmcsd0_device); 677 } 678 679 #ifdef CONFIG_ARCH_DAVINCI_DA850 680 static struct resource da850_mmcsd1_resources[] = { 681 { /* registers */ 682 .start = DA850_MMCSD1_BASE, 683 .end = DA850_MMCSD1_BASE + SZ_4K - 1, 684 .flags = IORESOURCE_MEM, 685 }, 686 { /* interrupt */ 687 .start = IRQ_DA850_MMCSDINT0_1, 688 .end = IRQ_DA850_MMCSDINT0_1, 689 .flags = IORESOURCE_IRQ, 690 }, 691 { /* DMA RX */ 692 .start = DA850_DMA_MMCSD1_RX, 693 .end = DA850_DMA_MMCSD1_RX, 694 .flags = IORESOURCE_DMA, 695 }, 696 { /* DMA TX */ 697 .start = DA850_DMA_MMCSD1_TX, 698 .end = DA850_DMA_MMCSD1_TX, 699 .flags = IORESOURCE_DMA, 700 }, 701 }; 702 703 static struct platform_device da850_mmcsd1_device = { 704 .name = "davinci_mmc", 705 .id = 1, 706 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), 707 .resource = da850_mmcsd1_resources, 708 }; 709 710 int __init da850_register_mmcsd1(struct davinci_mmc_config *config) 711 { 712 da850_mmcsd1_device.dev.platform_data = config; 713 return platform_device_register(&da850_mmcsd1_device); 714 } 715 #endif 716 717 static struct resource da8xx_rtc_resources[] = { 718 { 719 .start = DA8XX_RTC_BASE, 720 .end = DA8XX_RTC_BASE + SZ_4K - 1, 721 .flags = IORESOURCE_MEM, 722 }, 723 { /* timer irq */ 724 .start = IRQ_DA8XX_RTC, 725 .end = IRQ_DA8XX_RTC, 726 .flags = IORESOURCE_IRQ, 727 }, 728 { /* alarm irq */ 729 .start = IRQ_DA8XX_RTC, 730 .end = IRQ_DA8XX_RTC, 731 .flags = IORESOURCE_IRQ, 732 }, 733 }; 734 735 static struct platform_device da8xx_rtc_device = { 736 .name = "da830-rtc", 737 .id = -1, 738 .num_resources = ARRAY_SIZE(da8xx_rtc_resources), 739 .resource = da8xx_rtc_resources, 740 }; 741 742 int da8xx_register_rtc(void) 743 { 744 int ret; 745 746 ret = platform_device_register(&da8xx_rtc_device); 747 if (!ret) 748 /* Atleast on DA850, RTC is a wakeup source */ 749 device_init_wakeup(&da8xx_rtc_device.dev, true); 750 751 return ret; 752 } 753 754 static void __iomem *da8xx_ddr2_ctlr_base; 755 void __iomem * __init da8xx_get_mem_ctlr(void) 756 { 757 if (da8xx_ddr2_ctlr_base) 758 return da8xx_ddr2_ctlr_base; 759 760 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K); 761 if (!da8xx_ddr2_ctlr_base) 762 pr_warn("%s: Unable to map DDR2 controller", __func__); 763 764 return da8xx_ddr2_ctlr_base; 765 } 766 767 static struct resource da8xx_cpuidle_resources[] = { 768 { 769 .start = DA8XX_DDR2_CTL_BASE, 770 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1, 771 .flags = IORESOURCE_MEM, 772 }, 773 }; 774 775 /* DA8XX devices support DDR2 power down */ 776 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = { 777 .ddr2_pdown = 1, 778 }; 779 780 781 static struct platform_device da8xx_cpuidle_device = { 782 .name = "cpuidle-davinci", 783 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources), 784 .resource = da8xx_cpuidle_resources, 785 .dev = { 786 .platform_data = &da8xx_cpuidle_pdata, 787 }, 788 }; 789 790 int __init da8xx_register_cpuidle(void) 791 { 792 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr(); 793 794 return platform_device_register(&da8xx_cpuidle_device); 795 } 796 797 static struct resource da8xx_spi0_resources[] = { 798 [0] = { 799 .start = DA8XX_SPI0_BASE, 800 .end = DA8XX_SPI0_BASE + SZ_4K - 1, 801 .flags = IORESOURCE_MEM, 802 }, 803 [1] = { 804 .start = IRQ_DA8XX_SPINT0, 805 .end = IRQ_DA8XX_SPINT0, 806 .flags = IORESOURCE_IRQ, 807 }, 808 [2] = { 809 .start = DA8XX_DMA_SPI0_RX, 810 .end = DA8XX_DMA_SPI0_RX, 811 .flags = IORESOURCE_DMA, 812 }, 813 [3] = { 814 .start = DA8XX_DMA_SPI0_TX, 815 .end = DA8XX_DMA_SPI0_TX, 816 .flags = IORESOURCE_DMA, 817 }, 818 }; 819 820 static struct resource da8xx_spi1_resources[] = { 821 [0] = { 822 .start = DA830_SPI1_BASE, 823 .end = DA830_SPI1_BASE + SZ_4K - 1, 824 .flags = IORESOURCE_MEM, 825 }, 826 [1] = { 827 .start = IRQ_DA8XX_SPINT1, 828 .end = IRQ_DA8XX_SPINT1, 829 .flags = IORESOURCE_IRQ, 830 }, 831 [2] = { 832 .start = DA8XX_DMA_SPI1_RX, 833 .end = DA8XX_DMA_SPI1_RX, 834 .flags = IORESOURCE_DMA, 835 }, 836 [3] = { 837 .start = DA8XX_DMA_SPI1_TX, 838 .end = DA8XX_DMA_SPI1_TX, 839 .flags = IORESOURCE_DMA, 840 }, 841 }; 842 843 static struct davinci_spi_platform_data da8xx_spi_pdata[] = { 844 [0] = { 845 .version = SPI_VERSION_2, 846 .intr_line = 1, 847 .dma_event_q = EVENTQ_0, 848 }, 849 [1] = { 850 .version = SPI_VERSION_2, 851 .intr_line = 1, 852 .dma_event_q = EVENTQ_0, 853 }, 854 }; 855 856 static struct platform_device da8xx_spi_device[] = { 857 [0] = { 858 .name = "spi_davinci", 859 .id = 0, 860 .num_resources = ARRAY_SIZE(da8xx_spi0_resources), 861 .resource = da8xx_spi0_resources, 862 .dev = { 863 .platform_data = &da8xx_spi_pdata[0], 864 }, 865 }, 866 [1] = { 867 .name = "spi_davinci", 868 .id = 1, 869 .num_resources = ARRAY_SIZE(da8xx_spi1_resources), 870 .resource = da8xx_spi1_resources, 871 .dev = { 872 .platform_data = &da8xx_spi_pdata[1], 873 }, 874 }, 875 }; 876 877 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect) 878 { 879 if (instance < 0 || instance > 1) 880 return -EINVAL; 881 882 da8xx_spi_pdata[instance].num_chipselect = num_chipselect; 883 884 if (instance == 1 && cpu_is_davinci_da850()) { 885 da8xx_spi1_resources[0].start = DA850_SPI1_BASE; 886 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; 887 } 888 889 return platform_device_register(&da8xx_spi_device[instance]); 890 } 891 892 #ifdef CONFIG_ARCH_DAVINCI_DA850 893 894 static struct resource da850_sata_resources[] = { 895 { 896 .start = DA850_SATA_BASE, 897 .end = DA850_SATA_BASE + 0x1fff, 898 .flags = IORESOURCE_MEM, 899 }, 900 { 901 .start = IRQ_DA850_SATAINT, 902 .flags = IORESOURCE_IRQ, 903 }, 904 }; 905 906 /* SATA PHY Control Register offset from AHCI base */ 907 #define SATA_P0PHYCR_REG 0x178 908 909 #define SATA_PHY_MPY(x) ((x) << 0) 910 #define SATA_PHY_LOS(x) ((x) << 6) 911 #define SATA_PHY_RXCDR(x) ((x) << 10) 912 #define SATA_PHY_RXEQ(x) ((x) << 13) 913 #define SATA_PHY_TXSWING(x) ((x) << 19) 914 #define SATA_PHY_ENPLL(x) ((x) << 31) 915 916 static struct clk *da850_sata_clk; 917 static unsigned long da850_sata_refclkpn; 918 919 /* Supported DA850 SATA crystal frequencies */ 920 #define KHZ_TO_HZ(freq) ((freq) * 1000) 921 static unsigned long da850_sata_xtal[] = { 922 KHZ_TO_HZ(300000), 923 KHZ_TO_HZ(250000), 924 0, /* Reserved */ 925 KHZ_TO_HZ(187500), 926 KHZ_TO_HZ(150000), 927 KHZ_TO_HZ(125000), 928 KHZ_TO_HZ(120000), 929 KHZ_TO_HZ(100000), 930 KHZ_TO_HZ(75000), 931 KHZ_TO_HZ(60000), 932 }; 933 934 static int da850_sata_init(struct device *dev, void __iomem *addr) 935 { 936 int i, ret; 937 unsigned int val; 938 939 da850_sata_clk = clk_get(dev, NULL); 940 if (IS_ERR(da850_sata_clk)) 941 return PTR_ERR(da850_sata_clk); 942 943 ret = clk_prepare_enable(da850_sata_clk); 944 if (ret) 945 goto err0; 946 947 /* Enable SATA clock receiver */ 948 val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG)); 949 val &= ~BIT(0); 950 __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG)); 951 952 /* Get the multiplier needed for 1.5GHz PLL output */ 953 for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++) 954 if (da850_sata_xtal[i] == da850_sata_refclkpn) 955 break; 956 957 if (i == ARRAY_SIZE(da850_sata_xtal)) { 958 ret = -EINVAL; 959 goto err1; 960 } 961 962 val = SATA_PHY_MPY(i + 1) | 963 SATA_PHY_LOS(1) | 964 SATA_PHY_RXCDR(4) | 965 SATA_PHY_RXEQ(1) | 966 SATA_PHY_TXSWING(3) | 967 SATA_PHY_ENPLL(1); 968 969 __raw_writel(val, addr + SATA_P0PHYCR_REG); 970 971 return 0; 972 973 err1: 974 clk_disable_unprepare(da850_sata_clk); 975 err0: 976 clk_put(da850_sata_clk); 977 return ret; 978 } 979 980 static void da850_sata_exit(struct device *dev) 981 { 982 clk_disable_unprepare(da850_sata_clk); 983 clk_put(da850_sata_clk); 984 } 985 986 static struct ahci_platform_data da850_sata_pdata = { 987 .init = da850_sata_init, 988 .exit = da850_sata_exit, 989 }; 990 991 static u64 da850_sata_dmamask = DMA_BIT_MASK(32); 992 993 static struct platform_device da850_sata_device = { 994 .name = "ahci", 995 .id = -1, 996 .dev = { 997 .platform_data = &da850_sata_pdata, 998 .dma_mask = &da850_sata_dmamask, 999 .coherent_dma_mask = DMA_BIT_MASK(32), 1000 }, 1001 .num_resources = ARRAY_SIZE(da850_sata_resources), 1002 .resource = da850_sata_resources, 1003 }; 1004 1005 int __init da850_register_sata(unsigned long refclkpn) 1006 { 1007 da850_sata_refclkpn = refclkpn; 1008 if (!da850_sata_refclkpn) 1009 return -EINVAL; 1010 1011 return platform_device_register(&da850_sata_device); 1012 } 1013 #endif 1014