1 /* 2 * DA8XX/OMAP L1XX platform device data 3 * 4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> 5 * Derived from code that was: 6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 #include <linux/init.h> 14 #include <linux/platform_device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/serial_8250.h> 17 #include <linux/ahci_platform.h> 18 #include <linux/clk.h> 19 20 #include <mach/cputype.h> 21 #include <mach/common.h> 22 #include <mach/time.h> 23 #include <mach/da8xx.h> 24 #include <mach/cpuidle.h> 25 26 #include "clock.h" 27 28 #define DA8XX_TPCC_BASE 0x01c00000 29 #define DA8XX_TPTC0_BASE 0x01c08000 30 #define DA8XX_TPTC1_BASE 0x01c08400 31 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ 32 #define DA8XX_I2C0_BASE 0x01c22000 33 #define DA8XX_RTC_BASE 0x01c23000 34 #define DA8XX_MMCSD0_BASE 0x01c40000 35 #define DA8XX_SPI0_BASE 0x01c41000 36 #define DA830_SPI1_BASE 0x01e12000 37 #define DA8XX_LCD_CNTRL_BASE 0x01e13000 38 #define DA850_SATA_BASE 0x01e18000 39 #define DA850_MMCSD1_BASE 0x01e1b000 40 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 41 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 42 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 43 #define DA8XX_EMAC_MDIO_BASE 0x01e24000 44 #define DA8XX_I2C1_BASE 0x01e28000 45 #define DA850_TPCC1_BASE 0x01e30000 46 #define DA850_TPTC2_BASE 0x01e38000 47 #define DA850_SPI1_BASE 0x01f0e000 48 #define DA8XX_DDR2_CTL_BASE 0xb0000000 49 50 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 51 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 52 #define DA8XX_EMAC_RAM_OFFSET 0x0000 53 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K 54 55 #define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14) 56 #define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15) 57 #define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16) 58 #define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17) 59 #define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18) 60 #define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19) 61 #define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28) 62 #define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29) 63 64 void __iomem *da8xx_syscfg0_base; 65 void __iomem *da8xx_syscfg1_base; 66 67 static struct plat_serial8250_port da8xx_serial_pdata[] = { 68 { 69 .mapbase = DA8XX_UART0_BASE, 70 .irq = IRQ_DA8XX_UARTINT0, 71 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 72 UPF_IOREMAP, 73 .iotype = UPIO_MEM, 74 .regshift = 2, 75 }, 76 { 77 .mapbase = DA8XX_UART1_BASE, 78 .irq = IRQ_DA8XX_UARTINT1, 79 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 80 UPF_IOREMAP, 81 .iotype = UPIO_MEM, 82 .regshift = 2, 83 }, 84 { 85 .mapbase = DA8XX_UART2_BASE, 86 .irq = IRQ_DA8XX_UARTINT2, 87 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 88 UPF_IOREMAP, 89 .iotype = UPIO_MEM, 90 .regshift = 2, 91 }, 92 { 93 .flags = 0, 94 }, 95 }; 96 97 struct platform_device da8xx_serial_device = { 98 .name = "serial8250", 99 .id = PLAT8250_DEV_PLATFORM, 100 .dev = { 101 .platform_data = da8xx_serial_pdata, 102 }, 103 }; 104 105 static const s8 da8xx_queue_tc_mapping[][2] = { 106 /* {event queue no, TC no} */ 107 {0, 0}, 108 {1, 1}, 109 {-1, -1} 110 }; 111 112 static const s8 da8xx_queue_priority_mapping[][2] = { 113 /* {event queue no, Priority} */ 114 {0, 3}, 115 {1, 7}, 116 {-1, -1} 117 }; 118 119 static const s8 da850_queue_tc_mapping[][2] = { 120 /* {event queue no, TC no} */ 121 {0, 0}, 122 {-1, -1} 123 }; 124 125 static const s8 da850_queue_priority_mapping[][2] = { 126 /* {event queue no, Priority} */ 127 {0, 3}, 128 {-1, -1} 129 }; 130 131 static struct edma_soc_info da830_edma_cc0_info = { 132 .n_channel = 32, 133 .n_region = 4, 134 .n_slot = 128, 135 .n_tc = 2, 136 .n_cc = 1, 137 .queue_tc_mapping = da8xx_queue_tc_mapping, 138 .queue_priority_mapping = da8xx_queue_priority_mapping, 139 .default_queue = EVENTQ_1, 140 }; 141 142 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = { 143 &da830_edma_cc0_info, 144 }; 145 146 static struct edma_soc_info da850_edma_cc_info[] = { 147 { 148 .n_channel = 32, 149 .n_region = 4, 150 .n_slot = 128, 151 .n_tc = 2, 152 .n_cc = 1, 153 .queue_tc_mapping = da8xx_queue_tc_mapping, 154 .queue_priority_mapping = da8xx_queue_priority_mapping, 155 .default_queue = EVENTQ_1, 156 }, 157 { 158 .n_channel = 32, 159 .n_region = 4, 160 .n_slot = 128, 161 .n_tc = 1, 162 .n_cc = 1, 163 .queue_tc_mapping = da850_queue_tc_mapping, 164 .queue_priority_mapping = da850_queue_priority_mapping, 165 .default_queue = EVENTQ_0, 166 }, 167 }; 168 169 static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = { 170 &da850_edma_cc_info[0], 171 &da850_edma_cc_info[1], 172 }; 173 174 static struct resource da830_edma_resources[] = { 175 { 176 .name = "edma_cc0", 177 .start = DA8XX_TPCC_BASE, 178 .end = DA8XX_TPCC_BASE + SZ_32K - 1, 179 .flags = IORESOURCE_MEM, 180 }, 181 { 182 .name = "edma_tc0", 183 .start = DA8XX_TPTC0_BASE, 184 .end = DA8XX_TPTC0_BASE + SZ_1K - 1, 185 .flags = IORESOURCE_MEM, 186 }, 187 { 188 .name = "edma_tc1", 189 .start = DA8XX_TPTC1_BASE, 190 .end = DA8XX_TPTC1_BASE + SZ_1K - 1, 191 .flags = IORESOURCE_MEM, 192 }, 193 { 194 .name = "edma0", 195 .start = IRQ_DA8XX_CCINT0, 196 .flags = IORESOURCE_IRQ, 197 }, 198 { 199 .name = "edma0_err", 200 .start = IRQ_DA8XX_CCERRINT, 201 .flags = IORESOURCE_IRQ, 202 }, 203 }; 204 205 static struct resource da850_edma_resources[] = { 206 { 207 .name = "edma_cc0", 208 .start = DA8XX_TPCC_BASE, 209 .end = DA8XX_TPCC_BASE + SZ_32K - 1, 210 .flags = IORESOURCE_MEM, 211 }, 212 { 213 .name = "edma_tc0", 214 .start = DA8XX_TPTC0_BASE, 215 .end = DA8XX_TPTC0_BASE + SZ_1K - 1, 216 .flags = IORESOURCE_MEM, 217 }, 218 { 219 .name = "edma_tc1", 220 .start = DA8XX_TPTC1_BASE, 221 .end = DA8XX_TPTC1_BASE + SZ_1K - 1, 222 .flags = IORESOURCE_MEM, 223 }, 224 { 225 .name = "edma_cc1", 226 .start = DA850_TPCC1_BASE, 227 .end = DA850_TPCC1_BASE + SZ_32K - 1, 228 .flags = IORESOURCE_MEM, 229 }, 230 { 231 .name = "edma_tc2", 232 .start = DA850_TPTC2_BASE, 233 .end = DA850_TPTC2_BASE + SZ_1K - 1, 234 .flags = IORESOURCE_MEM, 235 }, 236 { 237 .name = "edma0", 238 .start = IRQ_DA8XX_CCINT0, 239 .flags = IORESOURCE_IRQ, 240 }, 241 { 242 .name = "edma0_err", 243 .start = IRQ_DA8XX_CCERRINT, 244 .flags = IORESOURCE_IRQ, 245 }, 246 { 247 .name = "edma1", 248 .start = IRQ_DA850_CCINT1, 249 .flags = IORESOURCE_IRQ, 250 }, 251 { 252 .name = "edma1_err", 253 .start = IRQ_DA850_CCERRINT1, 254 .flags = IORESOURCE_IRQ, 255 }, 256 }; 257 258 static struct platform_device da830_edma_device = { 259 .name = "edma", 260 .id = -1, 261 .dev = { 262 .platform_data = da830_edma_info, 263 }, 264 .num_resources = ARRAY_SIZE(da830_edma_resources), 265 .resource = da830_edma_resources, 266 }; 267 268 static struct platform_device da850_edma_device = { 269 .name = "edma", 270 .id = -1, 271 .dev = { 272 .platform_data = da850_edma_info, 273 }, 274 .num_resources = ARRAY_SIZE(da850_edma_resources), 275 .resource = da850_edma_resources, 276 }; 277 278 int __init da830_register_edma(struct edma_rsv_info *rsv) 279 { 280 da830_edma_cc0_info.rsv = rsv; 281 282 return platform_device_register(&da830_edma_device); 283 } 284 285 int __init da850_register_edma(struct edma_rsv_info *rsv[2]) 286 { 287 if (rsv) { 288 da850_edma_cc_info[0].rsv = rsv[0]; 289 da850_edma_cc_info[1].rsv = rsv[1]; 290 } 291 292 return platform_device_register(&da850_edma_device); 293 } 294 295 static struct resource da8xx_i2c_resources0[] = { 296 { 297 .start = DA8XX_I2C0_BASE, 298 .end = DA8XX_I2C0_BASE + SZ_4K - 1, 299 .flags = IORESOURCE_MEM, 300 }, 301 { 302 .start = IRQ_DA8XX_I2CINT0, 303 .end = IRQ_DA8XX_I2CINT0, 304 .flags = IORESOURCE_IRQ, 305 }, 306 }; 307 308 static struct platform_device da8xx_i2c_device0 = { 309 .name = "i2c_davinci", 310 .id = 1, 311 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), 312 .resource = da8xx_i2c_resources0, 313 }; 314 315 static struct resource da8xx_i2c_resources1[] = { 316 { 317 .start = DA8XX_I2C1_BASE, 318 .end = DA8XX_I2C1_BASE + SZ_4K - 1, 319 .flags = IORESOURCE_MEM, 320 }, 321 { 322 .start = IRQ_DA8XX_I2CINT1, 323 .end = IRQ_DA8XX_I2CINT1, 324 .flags = IORESOURCE_IRQ, 325 }, 326 }; 327 328 static struct platform_device da8xx_i2c_device1 = { 329 .name = "i2c_davinci", 330 .id = 2, 331 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), 332 .resource = da8xx_i2c_resources1, 333 }; 334 335 int __init da8xx_register_i2c(int instance, 336 struct davinci_i2c_platform_data *pdata) 337 { 338 struct platform_device *pdev; 339 340 if (instance == 0) 341 pdev = &da8xx_i2c_device0; 342 else if (instance == 1) 343 pdev = &da8xx_i2c_device1; 344 else 345 return -EINVAL; 346 347 pdev->dev.platform_data = pdata; 348 return platform_device_register(pdev); 349 } 350 351 static struct resource da8xx_watchdog_resources[] = { 352 { 353 .start = DA8XX_WDOG_BASE, 354 .end = DA8XX_WDOG_BASE + SZ_4K - 1, 355 .flags = IORESOURCE_MEM, 356 }, 357 }; 358 359 struct platform_device da8xx_wdt_device = { 360 .name = "watchdog", 361 .id = -1, 362 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), 363 .resource = da8xx_watchdog_resources, 364 }; 365 366 void da8xx_restart(char mode, const char *cmd) 367 { 368 davinci_watchdog_reset(&da8xx_wdt_device); 369 } 370 371 int __init da8xx_register_watchdog(void) 372 { 373 return platform_device_register(&da8xx_wdt_device); 374 } 375 376 static struct resource da8xx_emac_resources[] = { 377 { 378 .start = DA8XX_EMAC_CPPI_PORT_BASE, 379 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1, 380 .flags = IORESOURCE_MEM, 381 }, 382 { 383 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE, 384 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE, 385 .flags = IORESOURCE_IRQ, 386 }, 387 { 388 .start = IRQ_DA8XX_C0_RX_PULSE, 389 .end = IRQ_DA8XX_C0_RX_PULSE, 390 .flags = IORESOURCE_IRQ, 391 }, 392 { 393 .start = IRQ_DA8XX_C0_TX_PULSE, 394 .end = IRQ_DA8XX_C0_TX_PULSE, 395 .flags = IORESOURCE_IRQ, 396 }, 397 { 398 .start = IRQ_DA8XX_C0_MISC_PULSE, 399 .end = IRQ_DA8XX_C0_MISC_PULSE, 400 .flags = IORESOURCE_IRQ, 401 }, 402 }; 403 404 struct emac_platform_data da8xx_emac_pdata = { 405 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, 406 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, 407 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, 408 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, 409 .version = EMAC_VERSION_2, 410 }; 411 412 static struct platform_device da8xx_emac_device = { 413 .name = "davinci_emac", 414 .id = 1, 415 .dev = { 416 .platform_data = &da8xx_emac_pdata, 417 }, 418 .num_resources = ARRAY_SIZE(da8xx_emac_resources), 419 .resource = da8xx_emac_resources, 420 }; 421 422 static struct resource da8xx_mdio_resources[] = { 423 { 424 .start = DA8XX_EMAC_MDIO_BASE, 425 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1, 426 .flags = IORESOURCE_MEM, 427 }, 428 }; 429 430 static struct platform_device da8xx_mdio_device = { 431 .name = "davinci_mdio", 432 .id = 0, 433 .num_resources = ARRAY_SIZE(da8xx_mdio_resources), 434 .resource = da8xx_mdio_resources, 435 }; 436 437 int __init da8xx_register_emac(void) 438 { 439 int ret; 440 441 ret = platform_device_register(&da8xx_mdio_device); 442 if (ret < 0) 443 return ret; 444 ret = platform_device_register(&da8xx_emac_device); 445 if (ret < 0) 446 return ret; 447 ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev), 448 NULL, &da8xx_emac_device.dev); 449 return ret; 450 } 451 452 static struct resource da830_mcasp1_resources[] = { 453 { 454 .name = "mcasp1", 455 .start = DAVINCI_DA830_MCASP1_REG_BASE, 456 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, 457 .flags = IORESOURCE_MEM, 458 }, 459 /* TX event */ 460 { 461 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, 462 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, 463 .flags = IORESOURCE_DMA, 464 }, 465 /* RX event */ 466 { 467 .start = DAVINCI_DA830_DMA_MCASP1_AREVT, 468 .end = DAVINCI_DA830_DMA_MCASP1_AREVT, 469 .flags = IORESOURCE_DMA, 470 }, 471 }; 472 473 static struct platform_device da830_mcasp1_device = { 474 .name = "davinci-mcasp", 475 .id = 1, 476 .num_resources = ARRAY_SIZE(da830_mcasp1_resources), 477 .resource = da830_mcasp1_resources, 478 }; 479 480 static struct resource da850_mcasp_resources[] = { 481 { 482 .name = "mcasp", 483 .start = DAVINCI_DA8XX_MCASP0_REG_BASE, 484 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, 485 .flags = IORESOURCE_MEM, 486 }, 487 /* TX event */ 488 { 489 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 490 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 491 .flags = IORESOURCE_DMA, 492 }, 493 /* RX event */ 494 { 495 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 496 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 497 .flags = IORESOURCE_DMA, 498 }, 499 }; 500 501 static struct platform_device da850_mcasp_device = { 502 .name = "davinci-mcasp", 503 .id = 0, 504 .num_resources = ARRAY_SIZE(da850_mcasp_resources), 505 .resource = da850_mcasp_resources, 506 }; 507 508 static struct platform_device davinci_pcm_device = { 509 .name = "davinci-pcm-audio", 510 .id = -1, 511 }; 512 513 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) 514 { 515 platform_device_register(&davinci_pcm_device); 516 517 /* DA830/OMAP-L137 has 3 instances of McASP */ 518 if (cpu_is_davinci_da830() && id == 1) { 519 da830_mcasp1_device.dev.platform_data = pdata; 520 platform_device_register(&da830_mcasp1_device); 521 } else if (cpu_is_davinci_da850()) { 522 da850_mcasp_device.dev.platform_data = pdata; 523 platform_device_register(&da850_mcasp_device); 524 } 525 } 526 527 static const struct display_panel disp_panel = { 528 QVGA, 529 16, 530 16, 531 COLOR_ACTIVE, 532 }; 533 534 static struct lcd_ctrl_config lcd_cfg = { 535 &disp_panel, 536 .ac_bias = 255, 537 .ac_bias_intrpt = 0, 538 .dma_burst_sz = 16, 539 .bpp = 16, 540 .fdd = 255, 541 .tft_alt_mode = 0, 542 .stn_565_mode = 0, 543 .mono_8bit_mode = 0, 544 .invert_line_clock = 1, 545 .invert_frm_clock = 1, 546 .sync_edge = 0, 547 .sync_ctrl = 1, 548 .raster_order = 0, 549 .fifo_th = 6, 550 }; 551 552 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = { 553 .manu_name = "sharp", 554 .controller_data = &lcd_cfg, 555 .type = "Sharp_LCD035Q3DG01", 556 }; 557 558 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = { 559 .manu_name = "sharp", 560 .controller_data = &lcd_cfg, 561 .type = "Sharp_LK043T1DG01", 562 }; 563 564 static struct resource da8xx_lcdc_resources[] = { 565 [0] = { /* registers */ 566 .start = DA8XX_LCD_CNTRL_BASE, 567 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, 568 .flags = IORESOURCE_MEM, 569 }, 570 [1] = { /* interrupt */ 571 .start = IRQ_DA8XX_LCDINT, 572 .end = IRQ_DA8XX_LCDINT, 573 .flags = IORESOURCE_IRQ, 574 }, 575 }; 576 577 static struct platform_device da8xx_lcdc_device = { 578 .name = "da8xx_lcdc", 579 .id = 0, 580 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), 581 .resource = da8xx_lcdc_resources, 582 }; 583 584 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) 585 { 586 da8xx_lcdc_device.dev.platform_data = pdata; 587 return platform_device_register(&da8xx_lcdc_device); 588 } 589 590 static struct resource da8xx_mmcsd0_resources[] = { 591 { /* registers */ 592 .start = DA8XX_MMCSD0_BASE, 593 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, 594 .flags = IORESOURCE_MEM, 595 }, 596 { /* interrupt */ 597 .start = IRQ_DA8XX_MMCSDINT0, 598 .end = IRQ_DA8XX_MMCSDINT0, 599 .flags = IORESOURCE_IRQ, 600 }, 601 { /* DMA RX */ 602 .start = DA8XX_DMA_MMCSD0_RX, 603 .end = DA8XX_DMA_MMCSD0_RX, 604 .flags = IORESOURCE_DMA, 605 }, 606 { /* DMA TX */ 607 .start = DA8XX_DMA_MMCSD0_TX, 608 .end = DA8XX_DMA_MMCSD0_TX, 609 .flags = IORESOURCE_DMA, 610 }, 611 }; 612 613 static struct platform_device da8xx_mmcsd0_device = { 614 .name = "davinci_mmc", 615 .id = 0, 616 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), 617 .resource = da8xx_mmcsd0_resources, 618 }; 619 620 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) 621 { 622 da8xx_mmcsd0_device.dev.platform_data = config; 623 return platform_device_register(&da8xx_mmcsd0_device); 624 } 625 626 #ifdef CONFIG_ARCH_DAVINCI_DA850 627 static struct resource da850_mmcsd1_resources[] = { 628 { /* registers */ 629 .start = DA850_MMCSD1_BASE, 630 .end = DA850_MMCSD1_BASE + SZ_4K - 1, 631 .flags = IORESOURCE_MEM, 632 }, 633 { /* interrupt */ 634 .start = IRQ_DA850_MMCSDINT0_1, 635 .end = IRQ_DA850_MMCSDINT0_1, 636 .flags = IORESOURCE_IRQ, 637 }, 638 { /* DMA RX */ 639 .start = DA850_DMA_MMCSD1_RX, 640 .end = DA850_DMA_MMCSD1_RX, 641 .flags = IORESOURCE_DMA, 642 }, 643 { /* DMA TX */ 644 .start = DA850_DMA_MMCSD1_TX, 645 .end = DA850_DMA_MMCSD1_TX, 646 .flags = IORESOURCE_DMA, 647 }, 648 }; 649 650 static struct platform_device da850_mmcsd1_device = { 651 .name = "davinci_mmc", 652 .id = 1, 653 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), 654 .resource = da850_mmcsd1_resources, 655 }; 656 657 int __init da850_register_mmcsd1(struct davinci_mmc_config *config) 658 { 659 da850_mmcsd1_device.dev.platform_data = config; 660 return platform_device_register(&da850_mmcsd1_device); 661 } 662 #endif 663 664 static struct resource da8xx_rtc_resources[] = { 665 { 666 .start = DA8XX_RTC_BASE, 667 .end = DA8XX_RTC_BASE + SZ_4K - 1, 668 .flags = IORESOURCE_MEM, 669 }, 670 { /* timer irq */ 671 .start = IRQ_DA8XX_RTC, 672 .end = IRQ_DA8XX_RTC, 673 .flags = IORESOURCE_IRQ, 674 }, 675 { /* alarm irq */ 676 .start = IRQ_DA8XX_RTC, 677 .end = IRQ_DA8XX_RTC, 678 .flags = IORESOURCE_IRQ, 679 }, 680 }; 681 682 static struct platform_device da8xx_rtc_device = { 683 .name = "omap_rtc", 684 .id = -1, 685 .num_resources = ARRAY_SIZE(da8xx_rtc_resources), 686 .resource = da8xx_rtc_resources, 687 }; 688 689 int da8xx_register_rtc(void) 690 { 691 int ret; 692 void __iomem *base; 693 694 base = ioremap(DA8XX_RTC_BASE, SZ_4K); 695 if (WARN_ON(!base)) 696 return -ENOMEM; 697 698 /* Unlock the rtc's registers */ 699 __raw_writel(0x83e70b13, base + 0x6c); 700 __raw_writel(0x95a4f1e0, base + 0x70); 701 702 iounmap(base); 703 704 ret = platform_device_register(&da8xx_rtc_device); 705 if (!ret) 706 /* Atleast on DA850, RTC is a wakeup source */ 707 device_init_wakeup(&da8xx_rtc_device.dev, true); 708 709 return ret; 710 } 711 712 static void __iomem *da8xx_ddr2_ctlr_base; 713 void __iomem * __init da8xx_get_mem_ctlr(void) 714 { 715 if (da8xx_ddr2_ctlr_base) 716 return da8xx_ddr2_ctlr_base; 717 718 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K); 719 if (!da8xx_ddr2_ctlr_base) 720 pr_warning("%s: Unable to map DDR2 controller", __func__); 721 722 return da8xx_ddr2_ctlr_base; 723 } 724 725 static struct resource da8xx_cpuidle_resources[] = { 726 { 727 .start = DA8XX_DDR2_CTL_BASE, 728 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1, 729 .flags = IORESOURCE_MEM, 730 }, 731 }; 732 733 /* DA8XX devices support DDR2 power down */ 734 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = { 735 .ddr2_pdown = 1, 736 }; 737 738 739 static struct platform_device da8xx_cpuidle_device = { 740 .name = "cpuidle-davinci", 741 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources), 742 .resource = da8xx_cpuidle_resources, 743 .dev = { 744 .platform_data = &da8xx_cpuidle_pdata, 745 }, 746 }; 747 748 int __init da8xx_register_cpuidle(void) 749 { 750 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr(); 751 752 return platform_device_register(&da8xx_cpuidle_device); 753 } 754 755 static struct resource da8xx_spi0_resources[] = { 756 [0] = { 757 .start = DA8XX_SPI0_BASE, 758 .end = DA8XX_SPI0_BASE + SZ_4K - 1, 759 .flags = IORESOURCE_MEM, 760 }, 761 [1] = { 762 .start = IRQ_DA8XX_SPINT0, 763 .end = IRQ_DA8XX_SPINT0, 764 .flags = IORESOURCE_IRQ, 765 }, 766 [2] = { 767 .start = DA8XX_DMA_SPI0_RX, 768 .end = DA8XX_DMA_SPI0_RX, 769 .flags = IORESOURCE_DMA, 770 }, 771 [3] = { 772 .start = DA8XX_DMA_SPI0_TX, 773 .end = DA8XX_DMA_SPI0_TX, 774 .flags = IORESOURCE_DMA, 775 }, 776 }; 777 778 static struct resource da8xx_spi1_resources[] = { 779 [0] = { 780 .start = DA830_SPI1_BASE, 781 .end = DA830_SPI1_BASE + SZ_4K - 1, 782 .flags = IORESOURCE_MEM, 783 }, 784 [1] = { 785 .start = IRQ_DA8XX_SPINT1, 786 .end = IRQ_DA8XX_SPINT1, 787 .flags = IORESOURCE_IRQ, 788 }, 789 [2] = { 790 .start = DA8XX_DMA_SPI1_RX, 791 .end = DA8XX_DMA_SPI1_RX, 792 .flags = IORESOURCE_DMA, 793 }, 794 [3] = { 795 .start = DA8XX_DMA_SPI1_TX, 796 .end = DA8XX_DMA_SPI1_TX, 797 .flags = IORESOURCE_DMA, 798 }, 799 }; 800 801 struct davinci_spi_platform_data da8xx_spi_pdata[] = { 802 [0] = { 803 .version = SPI_VERSION_2, 804 .intr_line = 1, 805 .dma_event_q = EVENTQ_0, 806 }, 807 [1] = { 808 .version = SPI_VERSION_2, 809 .intr_line = 1, 810 .dma_event_q = EVENTQ_0, 811 }, 812 }; 813 814 static struct platform_device da8xx_spi_device[] = { 815 [0] = { 816 .name = "spi_davinci", 817 .id = 0, 818 .num_resources = ARRAY_SIZE(da8xx_spi0_resources), 819 .resource = da8xx_spi0_resources, 820 .dev = { 821 .platform_data = &da8xx_spi_pdata[0], 822 }, 823 }, 824 [1] = { 825 .name = "spi_davinci", 826 .id = 1, 827 .num_resources = ARRAY_SIZE(da8xx_spi1_resources), 828 .resource = da8xx_spi1_resources, 829 .dev = { 830 .platform_data = &da8xx_spi_pdata[1], 831 }, 832 }, 833 }; 834 835 int __init da8xx_register_spi(int instance, const struct spi_board_info *info, 836 unsigned len) 837 { 838 int ret; 839 840 if (instance < 0 || instance > 1) 841 return -EINVAL; 842 843 ret = spi_register_board_info(info, len); 844 if (ret) 845 pr_warning("%s: failed to register board info for spi %d :" 846 " %d\n", __func__, instance, ret); 847 848 da8xx_spi_pdata[instance].num_chipselect = len; 849 850 if (instance == 1 && cpu_is_davinci_da850()) { 851 da8xx_spi1_resources[0].start = DA850_SPI1_BASE; 852 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; 853 } 854 855 return platform_device_register(&da8xx_spi_device[instance]); 856 } 857 858 #ifdef CONFIG_ARCH_DAVINCI_DA850 859 860 static struct resource da850_sata_resources[] = { 861 { 862 .start = DA850_SATA_BASE, 863 .end = DA850_SATA_BASE + 0x1fff, 864 .flags = IORESOURCE_MEM, 865 }, 866 { 867 .start = IRQ_DA850_SATAINT, 868 .flags = IORESOURCE_IRQ, 869 }, 870 }; 871 872 /* SATA PHY Control Register offset from AHCI base */ 873 #define SATA_P0PHYCR_REG 0x178 874 875 #define SATA_PHY_MPY(x) ((x) << 0) 876 #define SATA_PHY_LOS(x) ((x) << 6) 877 #define SATA_PHY_RXCDR(x) ((x) << 10) 878 #define SATA_PHY_RXEQ(x) ((x) << 13) 879 #define SATA_PHY_TXSWING(x) ((x) << 19) 880 #define SATA_PHY_ENPLL(x) ((x) << 31) 881 882 static struct clk *da850_sata_clk; 883 static unsigned long da850_sata_refclkpn; 884 885 /* Supported DA850 SATA crystal frequencies */ 886 #define KHZ_TO_HZ(freq) ((freq) * 1000) 887 static unsigned long da850_sata_xtal[] = { 888 KHZ_TO_HZ(300000), 889 KHZ_TO_HZ(250000), 890 0, /* Reserved */ 891 KHZ_TO_HZ(187500), 892 KHZ_TO_HZ(150000), 893 KHZ_TO_HZ(125000), 894 KHZ_TO_HZ(120000), 895 KHZ_TO_HZ(100000), 896 KHZ_TO_HZ(75000), 897 KHZ_TO_HZ(60000), 898 }; 899 900 static int da850_sata_init(struct device *dev, void __iomem *addr) 901 { 902 int i, ret; 903 unsigned int val; 904 905 da850_sata_clk = clk_get(dev, NULL); 906 if (IS_ERR(da850_sata_clk)) 907 return PTR_ERR(da850_sata_clk); 908 909 ret = clk_enable(da850_sata_clk); 910 if (ret) 911 goto err0; 912 913 /* Enable SATA clock receiver */ 914 val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG)); 915 val &= ~BIT(0); 916 __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG)); 917 918 /* Get the multiplier needed for 1.5GHz PLL output */ 919 for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++) 920 if (da850_sata_xtal[i] == da850_sata_refclkpn) 921 break; 922 923 if (i == ARRAY_SIZE(da850_sata_xtal)) { 924 ret = -EINVAL; 925 goto err1; 926 } 927 928 val = SATA_PHY_MPY(i + 1) | 929 SATA_PHY_LOS(1) | 930 SATA_PHY_RXCDR(4) | 931 SATA_PHY_RXEQ(1) | 932 SATA_PHY_TXSWING(3) | 933 SATA_PHY_ENPLL(1); 934 935 __raw_writel(val, addr + SATA_P0PHYCR_REG); 936 937 return 0; 938 939 err1: 940 clk_disable(da850_sata_clk); 941 err0: 942 clk_put(da850_sata_clk); 943 return ret; 944 } 945 946 static void da850_sata_exit(struct device *dev) 947 { 948 clk_disable(da850_sata_clk); 949 clk_put(da850_sata_clk); 950 } 951 952 static struct ahci_platform_data da850_sata_pdata = { 953 .init = da850_sata_init, 954 .exit = da850_sata_exit, 955 }; 956 957 static u64 da850_sata_dmamask = DMA_BIT_MASK(32); 958 959 static struct platform_device da850_sata_device = { 960 .name = "ahci", 961 .id = -1, 962 .dev = { 963 .platform_data = &da850_sata_pdata, 964 .dma_mask = &da850_sata_dmamask, 965 .coherent_dma_mask = DMA_BIT_MASK(32), 966 }, 967 .num_resources = ARRAY_SIZE(da850_sata_resources), 968 .resource = da850_sata_resources, 969 }; 970 971 int __init da850_register_sata(unsigned long refclkpn) 972 { 973 da850_sata_refclkpn = refclkpn; 974 if (!da850_sata_refclkpn) 975 return -EINVAL; 976 977 return platform_device_register(&da850_sata_device); 978 } 979 #endif 980