1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * DA8XX/OMAP L1XX platform device data
4  *
5  * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
6  * Derived from code that was:
7  *	Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
8  */
9 #include <linux/ahci_platform.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk.h>
12 #include <linux/clkdev.h>
13 #include <linux/dma-map-ops.h>
14 #include <linux/dmaengine.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/platform_device.h>
18 #include <linux/reboot.h>
19 #include <linux/serial_8250.h>
20 
21 #include "common.h"
22 #include "cputype.h"
23 #include "da8xx.h"
24 #include "asp.h"
25 #include "cpuidle.h"
26 #include "irqs.h"
27 #include "sram.h"
28 
29 #define DA8XX_TPCC_BASE			0x01c00000
30 #define DA8XX_TPTC0_BASE		0x01c08000
31 #define DA8XX_TPTC1_BASE		0x01c08400
32 #define DA8XX_WDOG_BASE			0x01c21000 /* DA8XX_TIMER64P1_BASE */
33 #define DA8XX_I2C0_BASE			0x01c22000
34 #define DA8XX_RTC_BASE			0x01c23000
35 #define DA8XX_PRUSS_MEM_BASE		0x01c30000
36 #define DA8XX_MMCSD0_BASE		0x01c40000
37 #define DA8XX_SPI0_BASE			0x01c41000
38 #define DA830_SPI1_BASE			0x01e12000
39 #define DA8XX_LCD_CNTRL_BASE		0x01e13000
40 #define DA850_SATA_BASE			0x01e18000
41 #define DA850_MMCSD1_BASE		0x01e1b000
42 #define DA8XX_EMAC_CPPI_PORT_BASE	0x01e20000
43 #define DA8XX_EMAC_CPGMACSS_BASE	0x01e22000
44 #define DA8XX_EMAC_CPGMAC_BASE		0x01e23000
45 #define DA8XX_EMAC_MDIO_BASE		0x01e24000
46 #define DA8XX_I2C1_BASE			0x01e28000
47 #define DA850_TPCC1_BASE		0x01e30000
48 #define DA850_TPTC2_BASE		0x01e38000
49 #define DA850_SPI1_BASE			0x01f0e000
50 #define DA8XX_DDR2_CTL_BASE		0xb0000000
51 
52 #define DA8XX_EMAC_CTRL_REG_OFFSET	0x3000
53 #define DA8XX_EMAC_MOD_REG_OFFSET	0x2000
54 #define DA8XX_EMAC_RAM_OFFSET		0x0000
55 #define DA8XX_EMAC_CTRL_RAM_SIZE	SZ_8K
56 
57 void __iomem *da8xx_syscfg0_base;
58 void __iomem *da8xx_syscfg1_base;
59 
60 static struct plat_serial8250_port da8xx_serial0_pdata[] = {
61 	{
62 		.mapbase	= DA8XX_UART0_BASE,
63 		.irq		= DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0),
64 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
65 					UPF_IOREMAP,
66 		.iotype		= UPIO_MEM,
67 		.regshift	= 2,
68 	},
69 	{
70 		.flags	= 0,
71 	}
72 };
73 static struct plat_serial8250_port da8xx_serial1_pdata[] = {
74 	{
75 		.mapbase	= DA8XX_UART1_BASE,
76 		.irq		= DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1),
77 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
78 					UPF_IOREMAP,
79 		.iotype		= UPIO_MEM,
80 		.regshift	= 2,
81 	},
82 	{
83 		.flags	= 0,
84 	}
85 };
86 static struct plat_serial8250_port da8xx_serial2_pdata[] = {
87 	{
88 		.mapbase	= DA8XX_UART2_BASE,
89 		.irq		= DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2),
90 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
91 					UPF_IOREMAP,
92 		.iotype		= UPIO_MEM,
93 		.regshift	= 2,
94 	},
95 	{
96 		.flags	= 0,
97 	}
98 };
99 
100 struct platform_device da8xx_serial_device[] = {
101 	{
102 		.name	= "serial8250",
103 		.id	= PLAT8250_DEV_PLATFORM,
104 		.dev	= {
105 			.platform_data	= da8xx_serial0_pdata,
106 		}
107 	},
108 	{
109 		.name	= "serial8250",
110 		.id	= PLAT8250_DEV_PLATFORM1,
111 		.dev	= {
112 			.platform_data	= da8xx_serial1_pdata,
113 		}
114 	},
115 	{
116 		.name	= "serial8250",
117 		.id	= PLAT8250_DEV_PLATFORM2,
118 		.dev	= {
119 			.platform_data	= da8xx_serial2_pdata,
120 		}
121 	},
122 	{
123 	}
124 };
125 
126 static s8 da8xx_queue_priority_mapping[][2] = {
127 	/* {event queue no, Priority} */
128 	{0, 3},
129 	{1, 7},
130 	{-1, -1}
131 };
132 
133 static s8 da850_queue_priority_mapping[][2] = {
134 	/* {event queue no, Priority} */
135 	{0, 3},
136 	{-1, -1}
137 };
138 
139 static struct edma_soc_info da8xx_edma0_pdata = {
140 	.queue_priority_mapping	= da8xx_queue_priority_mapping,
141 	.default_queue		= EVENTQ_1,
142 };
143 
144 static struct edma_soc_info da850_edma1_pdata = {
145 	.queue_priority_mapping	= da850_queue_priority_mapping,
146 	.default_queue		= EVENTQ_0,
147 };
148 
149 static struct resource da8xx_edma0_resources[] = {
150 	{
151 		.name	= "edma3_cc",
152 		.start	= DA8XX_TPCC_BASE,
153 		.end	= DA8XX_TPCC_BASE + SZ_32K - 1,
154 		.flags	= IORESOURCE_MEM,
155 	},
156 	{
157 		.name	= "edma3_tc0",
158 		.start	= DA8XX_TPTC0_BASE,
159 		.end	= DA8XX_TPTC0_BASE + SZ_1K - 1,
160 		.flags	= IORESOURCE_MEM,
161 	},
162 	{
163 		.name	= "edma3_tc1",
164 		.start	= DA8XX_TPTC1_BASE,
165 		.end	= DA8XX_TPTC1_BASE + SZ_1K - 1,
166 		.flags	= IORESOURCE_MEM,
167 	},
168 	{
169 		.name	= "edma3_ccint",
170 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0),
171 		.flags	= IORESOURCE_IRQ,
172 	},
173 	{
174 		.name	= "edma3_ccerrint",
175 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT),
176 		.flags	= IORESOURCE_IRQ,
177 	},
178 };
179 
180 static struct resource da850_edma1_resources[] = {
181 	{
182 		.name	= "edma3_cc",
183 		.start	= DA850_TPCC1_BASE,
184 		.end	= DA850_TPCC1_BASE + SZ_32K - 1,
185 		.flags	= IORESOURCE_MEM,
186 	},
187 	{
188 		.name	= "edma3_tc0",
189 		.start	= DA850_TPTC2_BASE,
190 		.end	= DA850_TPTC2_BASE + SZ_1K - 1,
191 		.flags	= IORESOURCE_MEM,
192 	},
193 	{
194 		.name	= "edma3_ccint",
195 		.start	= DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1),
196 		.flags	= IORESOURCE_IRQ,
197 	},
198 	{
199 		.name	= "edma3_ccerrint",
200 		.start	= DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1),
201 		.flags	= IORESOURCE_IRQ,
202 	},
203 };
204 
205 static const struct platform_device_info da8xx_edma0_device __initconst = {
206 	.name		= "edma",
207 	.id		= 0,
208 	.dma_mask	= DMA_BIT_MASK(32),
209 	.res		= da8xx_edma0_resources,
210 	.num_res	= ARRAY_SIZE(da8xx_edma0_resources),
211 	.data		= &da8xx_edma0_pdata,
212 	.size_data	= sizeof(da8xx_edma0_pdata),
213 };
214 
215 static const struct platform_device_info da850_edma1_device __initconst = {
216 	.name		= "edma",
217 	.id		= 1,
218 	.dma_mask	= DMA_BIT_MASK(32),
219 	.res		= da850_edma1_resources,
220 	.num_res	= ARRAY_SIZE(da850_edma1_resources),
221 	.data		= &da850_edma1_pdata,
222 	.size_data	= sizeof(da850_edma1_pdata),
223 };
224 
225 static const struct dma_slave_map da830_edma_map[] = {
226 	{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
227 	{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
228 	{ "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
229 	{ "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
230 	{ "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
231 	{ "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
232 	{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
233 	{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
234 	{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
235 	{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
236 	{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
237 	{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
238 };
239 
240 int __init da830_register_edma(struct edma_rsv_info *rsv)
241 {
242 	struct platform_device *edma_pdev;
243 
244 	da8xx_edma0_pdata.rsv = rsv;
245 
246 	da8xx_edma0_pdata.slave_map = da830_edma_map;
247 	da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
248 
249 	edma_pdev = platform_device_register_full(&da8xx_edma0_device);
250 	return PTR_ERR_OR_ZERO(edma_pdev);
251 }
252 
253 static const struct dma_slave_map da850_edma0_map[] = {
254 	{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
255 	{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
256 	{ "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
257 	{ "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
258 	{ "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
259 	{ "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
260 	{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
261 	{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
262 	{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
263 	{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
264 	{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
265 	{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
266 };
267 
268 static const struct dma_slave_map da850_edma1_map[] = {
269 	{ "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
270 	{ "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
271 };
272 
273 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
274 {
275 	struct platform_device *edma_pdev;
276 
277 	if (rsv) {
278 		da8xx_edma0_pdata.rsv = rsv[0];
279 		da850_edma1_pdata.rsv = rsv[1];
280 	}
281 
282 	da8xx_edma0_pdata.slave_map = da850_edma0_map;
283 	da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
284 
285 	edma_pdev = platform_device_register_full(&da8xx_edma0_device);
286 	if (IS_ERR(edma_pdev)) {
287 		pr_warn("%s: Failed to register eDMA0\n", __func__);
288 		return PTR_ERR(edma_pdev);
289 	}
290 
291 	da850_edma1_pdata.slave_map = da850_edma1_map;
292 	da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
293 
294 	edma_pdev = platform_device_register_full(&da850_edma1_device);
295 	return PTR_ERR_OR_ZERO(edma_pdev);
296 }
297 
298 static struct resource da8xx_i2c_resources0[] = {
299 	{
300 		.start	= DA8XX_I2C0_BASE,
301 		.end	= DA8XX_I2C0_BASE + SZ_4K - 1,
302 		.flags	= IORESOURCE_MEM,
303 	},
304 	{
305 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
306 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
307 		.flags	= IORESOURCE_IRQ,
308 	},
309 };
310 
311 static struct platform_device da8xx_i2c_device0 = {
312 	.name		= "i2c_davinci",
313 	.id		= 1,
314 	.num_resources	= ARRAY_SIZE(da8xx_i2c_resources0),
315 	.resource	= da8xx_i2c_resources0,
316 };
317 
318 static struct resource da8xx_i2c_resources1[] = {
319 	{
320 		.start	= DA8XX_I2C1_BASE,
321 		.end	= DA8XX_I2C1_BASE + SZ_4K - 1,
322 		.flags	= IORESOURCE_MEM,
323 	},
324 	{
325 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
326 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
327 		.flags	= IORESOURCE_IRQ,
328 	},
329 };
330 
331 static struct platform_device da8xx_i2c_device1 = {
332 	.name		= "i2c_davinci",
333 	.id		= 2,
334 	.num_resources	= ARRAY_SIZE(da8xx_i2c_resources1),
335 	.resource	= da8xx_i2c_resources1,
336 };
337 
338 int __init da8xx_register_i2c(int instance,
339 		struct davinci_i2c_platform_data *pdata)
340 {
341 	struct platform_device *pdev;
342 
343 	if (instance == 0)
344 		pdev = &da8xx_i2c_device0;
345 	else if (instance == 1)
346 		pdev = &da8xx_i2c_device1;
347 	else
348 		return -EINVAL;
349 
350 	pdev->dev.platform_data = pdata;
351 	return platform_device_register(pdev);
352 }
353 
354 static struct resource da8xx_watchdog_resources[] = {
355 	{
356 		.start	= DA8XX_WDOG_BASE,
357 		.end	= DA8XX_WDOG_BASE + SZ_4K - 1,
358 		.flags	= IORESOURCE_MEM,
359 	},
360 };
361 
362 static struct platform_device da8xx_wdt_device = {
363 	.name		= "davinci-wdt",
364 	.id		= -1,
365 	.num_resources	= ARRAY_SIZE(da8xx_watchdog_resources),
366 	.resource	= da8xx_watchdog_resources,
367 };
368 
369 int __init da8xx_register_watchdog(void)
370 {
371 	return platform_device_register(&da8xx_wdt_device);
372 }
373 
374 static struct resource da8xx_emac_resources[] = {
375 	{
376 		.start	= DA8XX_EMAC_CPPI_PORT_BASE,
377 		.end	= DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
378 		.flags	= IORESOURCE_MEM,
379 	},
380 	{
381 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
382 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
383 		.flags	= IORESOURCE_IRQ,
384 	},
385 	{
386 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
387 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
388 		.flags	= IORESOURCE_IRQ,
389 	},
390 	{
391 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
392 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
393 		.flags	= IORESOURCE_IRQ,
394 	},
395 	{
396 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
397 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
398 		.flags	= IORESOURCE_IRQ,
399 	},
400 };
401 
402 struct emac_platform_data da8xx_emac_pdata = {
403 	.ctrl_reg_offset	= DA8XX_EMAC_CTRL_REG_OFFSET,
404 	.ctrl_mod_reg_offset	= DA8XX_EMAC_MOD_REG_OFFSET,
405 	.ctrl_ram_offset	= DA8XX_EMAC_RAM_OFFSET,
406 	.ctrl_ram_size		= DA8XX_EMAC_CTRL_RAM_SIZE,
407 	.version		= EMAC_VERSION_2,
408 };
409 
410 static struct platform_device da8xx_emac_device = {
411 	.name		= "davinci_emac",
412 	.id		= 1,
413 	.dev = {
414 		.platform_data	= &da8xx_emac_pdata,
415 	},
416 	.num_resources	= ARRAY_SIZE(da8xx_emac_resources),
417 	.resource	= da8xx_emac_resources,
418 };
419 
420 static struct resource da8xx_mdio_resources[] = {
421 	{
422 		.start	= DA8XX_EMAC_MDIO_BASE,
423 		.end	= DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
424 		.flags	= IORESOURCE_MEM,
425 	},
426 };
427 
428 static struct platform_device da8xx_mdio_device = {
429 	.name		= "davinci_mdio",
430 	.id		= 0,
431 	.num_resources	= ARRAY_SIZE(da8xx_mdio_resources),
432 	.resource	= da8xx_mdio_resources,
433 };
434 
435 int __init da8xx_register_emac(void)
436 {
437 	int ret;
438 
439 	ret = platform_device_register(&da8xx_mdio_device);
440 	if (ret < 0)
441 		return ret;
442 
443 	return platform_device_register(&da8xx_emac_device);
444 }
445 
446 static struct resource da830_mcasp1_resources[] = {
447 	{
448 		.name	= "mpu",
449 		.start	= DAVINCI_DA830_MCASP1_REG_BASE,
450 		.end	= DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
451 		.flags	= IORESOURCE_MEM,
452 	},
453 	/* TX event */
454 	{
455 		.name	= "tx",
456 		.start	= DAVINCI_DA830_DMA_MCASP1_AXEVT,
457 		.end	= DAVINCI_DA830_DMA_MCASP1_AXEVT,
458 		.flags	= IORESOURCE_DMA,
459 	},
460 	/* RX event */
461 	{
462 		.name	= "rx",
463 		.start	= DAVINCI_DA830_DMA_MCASP1_AREVT,
464 		.end	= DAVINCI_DA830_DMA_MCASP1_AREVT,
465 		.flags	= IORESOURCE_DMA,
466 	},
467 	{
468 		.name	= "common",
469 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
470 		.flags	= IORESOURCE_IRQ,
471 	},
472 };
473 
474 static struct platform_device da830_mcasp1_device = {
475 	.name		= "davinci-mcasp",
476 	.id		= 1,
477 	.num_resources	= ARRAY_SIZE(da830_mcasp1_resources),
478 	.resource	= da830_mcasp1_resources,
479 };
480 
481 static struct resource da830_mcasp2_resources[] = {
482 	{
483 		.name	= "mpu",
484 		.start	= DAVINCI_DA830_MCASP2_REG_BASE,
485 		.end	= DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
486 		.flags	= IORESOURCE_MEM,
487 	},
488 	/* TX event */
489 	{
490 		.name	= "tx",
491 		.start	= DAVINCI_DA830_DMA_MCASP2_AXEVT,
492 		.end	= DAVINCI_DA830_DMA_MCASP2_AXEVT,
493 		.flags	= IORESOURCE_DMA,
494 	},
495 	/* RX event */
496 	{
497 		.name	= "rx",
498 		.start	= DAVINCI_DA830_DMA_MCASP2_AREVT,
499 		.end	= DAVINCI_DA830_DMA_MCASP2_AREVT,
500 		.flags	= IORESOURCE_DMA,
501 	},
502 	{
503 		.name	= "common",
504 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
505 		.flags	= IORESOURCE_IRQ,
506 	},
507 };
508 
509 static struct platform_device da830_mcasp2_device = {
510 	.name		= "davinci-mcasp",
511 	.id		= 2,
512 	.num_resources	= ARRAY_SIZE(da830_mcasp2_resources),
513 	.resource	= da830_mcasp2_resources,
514 };
515 
516 static struct resource da850_mcasp_resources[] = {
517 	{
518 		.name	= "mpu",
519 		.start	= DAVINCI_DA8XX_MCASP0_REG_BASE,
520 		.end	= DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
521 		.flags	= IORESOURCE_MEM,
522 	},
523 	/* TX event */
524 	{
525 		.name	= "tx",
526 		.start	= DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
527 		.end	= DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
528 		.flags	= IORESOURCE_DMA,
529 	},
530 	/* RX event */
531 	{
532 		.name	= "rx",
533 		.start	= DAVINCI_DA8XX_DMA_MCASP0_AREVT,
534 		.end	= DAVINCI_DA8XX_DMA_MCASP0_AREVT,
535 		.flags	= IORESOURCE_DMA,
536 	},
537 	{
538 		.name	= "common",
539 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
540 		.flags	= IORESOURCE_IRQ,
541 	},
542 };
543 
544 static struct platform_device da850_mcasp_device = {
545 	.name		= "davinci-mcasp",
546 	.id		= 0,
547 	.num_resources	= ARRAY_SIZE(da850_mcasp_resources),
548 	.resource	= da850_mcasp_resources,
549 };
550 
551 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
552 {
553 	struct platform_device *pdev;
554 
555 	switch (id) {
556 	case 0:
557 		/* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
558 		pdev = &da850_mcasp_device;
559 		break;
560 	case 1:
561 		/* Valid for DA830/OMAP-L137 only */
562 		if (!cpu_is_davinci_da830())
563 			return;
564 		pdev = &da830_mcasp1_device;
565 		break;
566 	case 2:
567 		/* Valid for DA830/OMAP-L137 only */
568 		if (!cpu_is_davinci_da830())
569 			return;
570 		pdev = &da830_mcasp2_device;
571 		break;
572 	default:
573 		return;
574 	}
575 
576 	pdev->dev.platform_data = pdata;
577 	platform_device_register(pdev);
578 }
579 
580 static struct resource da8xx_pruss_resources[] = {
581 	{
582 		.start	= DA8XX_PRUSS_MEM_BASE,
583 		.end	= DA8XX_PRUSS_MEM_BASE + 0xFFFF,
584 		.flags	= IORESOURCE_MEM,
585 	},
586 	{
587 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
588 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
589 		.flags	= IORESOURCE_IRQ,
590 	},
591 	{
592 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
593 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
594 		.flags	= IORESOURCE_IRQ,
595 	},
596 	{
597 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
598 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
599 		.flags	= IORESOURCE_IRQ,
600 	},
601 	{
602 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
603 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
604 		.flags	= IORESOURCE_IRQ,
605 	},
606 	{
607 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
608 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
609 		.flags	= IORESOURCE_IRQ,
610 	},
611 	{
612 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
613 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
614 		.flags	= IORESOURCE_IRQ,
615 	},
616 	{
617 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
618 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
619 		.flags	= IORESOURCE_IRQ,
620 	},
621 	{
622 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
623 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
624 		.flags	= IORESOURCE_IRQ,
625 	},
626 };
627 
628 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
629 	.pintc_base	= 0x4000,
630 };
631 
632 static struct platform_device da8xx_uio_pruss_dev = {
633 	.name		= "pruss_uio",
634 	.id		= -1,
635 	.num_resources	= ARRAY_SIZE(da8xx_pruss_resources),
636 	.resource	= da8xx_pruss_resources,
637 	.dev		= {
638 		.coherent_dma_mask	= DMA_BIT_MASK(32),
639 		.platform_data		= &da8xx_uio_pruss_pdata,
640 	}
641 };
642 
643 int __init da8xx_register_uio_pruss(void)
644 {
645 	da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
646 	return platform_device_register(&da8xx_uio_pruss_dev);
647 }
648 
649 static struct lcd_ctrl_config lcd_cfg = {
650 	.panel_shade		= COLOR_ACTIVE,
651 	.bpp			= 16,
652 };
653 
654 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
655 	.manu_name		= "sharp",
656 	.controller_data	= &lcd_cfg,
657 	.type			= "Sharp_LCD035Q3DG01",
658 };
659 
660 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
661 	.manu_name		= "sharp",
662 	.controller_data	= &lcd_cfg,
663 	.type			= "Sharp_LK043T1DG01",
664 };
665 
666 static struct resource da8xx_lcdc_resources[] = {
667 	[0] = { /* registers */
668 		.start  = DA8XX_LCD_CNTRL_BASE,
669 		.end    = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
670 		.flags  = IORESOURCE_MEM,
671 	},
672 	[1] = { /* interrupt */
673 		.start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
674 		.end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
675 		.flags  = IORESOURCE_IRQ,
676 	},
677 };
678 
679 static struct platform_device da8xx_lcdc_device = {
680 	.name		= "da8xx_lcdc",
681 	.id		= 0,
682 	.num_resources	= ARRAY_SIZE(da8xx_lcdc_resources),
683 	.resource	= da8xx_lcdc_resources,
684 	.dev		= {
685 		.coherent_dma_mask	= DMA_BIT_MASK(32),
686 	}
687 };
688 
689 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
690 {
691 	da8xx_lcdc_device.dev.platform_data = pdata;
692 	return platform_device_register(&da8xx_lcdc_device);
693 }
694 
695 static struct resource da8xx_gpio_resources[] = {
696 	{ /* registers */
697 		.start	= DA8XX_GPIO_BASE,
698 		.end	= DA8XX_GPIO_BASE + SZ_4K - 1,
699 		.flags	= IORESOURCE_MEM,
700 	},
701 	{ /* interrupt */
702 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
703 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
704 		.flags	= IORESOURCE_IRQ,
705 	},
706 	{
707 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
708 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
709 		.flags	= IORESOURCE_IRQ,
710 	},
711 	{
712 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
713 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
714 		.flags	= IORESOURCE_IRQ,
715 	},
716 	{
717 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
718 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
719 		.flags	= IORESOURCE_IRQ,
720 	},
721 	{
722 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
723 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
724 		.flags	= IORESOURCE_IRQ,
725 	},
726 	{
727 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
728 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
729 		.flags	= IORESOURCE_IRQ,
730 	},
731 	{
732 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
733 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
734 		.flags	= IORESOURCE_IRQ,
735 	},
736 	{
737 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
738 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
739 		.flags	= IORESOURCE_IRQ,
740 	},
741 	{
742 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
743 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
744 		.flags	= IORESOURCE_IRQ,
745 	},
746 };
747 
748 static struct platform_device da8xx_gpio_device = {
749 	.name		= "davinci_gpio",
750 	.id		= -1,
751 	.num_resources	= ARRAY_SIZE(da8xx_gpio_resources),
752 	.resource	= da8xx_gpio_resources,
753 };
754 
755 int __init da8xx_register_gpio(void *pdata)
756 {
757 	da8xx_gpio_device.dev.platform_data = pdata;
758 	return platform_device_register(&da8xx_gpio_device);
759 }
760 
761 static struct resource da8xx_mmcsd0_resources[] = {
762 	{		/* registers */
763 		.start	= DA8XX_MMCSD0_BASE,
764 		.end	= DA8XX_MMCSD0_BASE + SZ_4K - 1,
765 		.flags	= IORESOURCE_MEM,
766 	},
767 	{		/* interrupt */
768 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
769 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
770 		.flags	= IORESOURCE_IRQ,
771 	},
772 };
773 
774 static struct platform_device da8xx_mmcsd0_device = {
775 	.name		= "da830-mmc",
776 	.id		= 0,
777 	.num_resources	= ARRAY_SIZE(da8xx_mmcsd0_resources),
778 	.resource	= da8xx_mmcsd0_resources,
779 };
780 
781 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
782 {
783 	da8xx_mmcsd0_device.dev.platform_data = config;
784 	return platform_device_register(&da8xx_mmcsd0_device);
785 }
786 
787 #ifdef CONFIG_ARCH_DAVINCI_DA850
788 static struct resource da850_mmcsd1_resources[] = {
789 	{		/* registers */
790 		.start	= DA850_MMCSD1_BASE,
791 		.end	= DA850_MMCSD1_BASE + SZ_4K - 1,
792 		.flags	= IORESOURCE_MEM,
793 	},
794 	{		/* interrupt */
795 		.start	= DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
796 		.end	= DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
797 		.flags	= IORESOURCE_IRQ,
798 	},
799 };
800 
801 static struct platform_device da850_mmcsd1_device = {
802 	.name		= "da830-mmc",
803 	.id		= 1,
804 	.num_resources	= ARRAY_SIZE(da850_mmcsd1_resources),
805 	.resource	= da850_mmcsd1_resources,
806 };
807 
808 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
809 {
810 	da850_mmcsd1_device.dev.platform_data = config;
811 	return platform_device_register(&da850_mmcsd1_device);
812 }
813 #endif
814 
815 static struct resource da8xx_rproc_resources[] = {
816 	{ /* DSP boot address */
817 		.name		= "host1cfg",
818 		.start		= DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
819 		.end		= DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
820 		.flags		= IORESOURCE_MEM,
821 	},
822 	{ /* DSP interrupt registers */
823 		.name		= "chipsig",
824 		.start		= DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
825 		.end		= DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
826 		.flags		= IORESOURCE_MEM,
827 	},
828 	{ /* DSP L2 RAM */
829 		.name		= "l2sram",
830 		.start		= DA8XX_DSP_L2_RAM_BASE,
831 		.end		= DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
832 		.flags		= IORESOURCE_MEM,
833 	},
834 	{ /* DSP L1P RAM */
835 		.name		= "l1pram",
836 		.start		= DA8XX_DSP_L1P_RAM_BASE,
837 		.end		= DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
838 		.flags		= IORESOURCE_MEM,
839 	},
840 	{ /* DSP L1D RAM */
841 		.name		= "l1dram",
842 		.start		= DA8XX_DSP_L1D_RAM_BASE,
843 		.end		= DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
844 		.flags		= IORESOURCE_MEM,
845 	},
846 	{ /* dsp irq */
847 		.start		= DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
848 		.end		= DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
849 		.flags		= IORESOURCE_IRQ,
850 	},
851 };
852 
853 static struct platform_device da8xx_dsp = {
854 	.name	= "davinci-rproc",
855 	.dev	= {
856 		.coherent_dma_mask	= DMA_BIT_MASK(32),
857 	},
858 	.num_resources	= ARRAY_SIZE(da8xx_rproc_resources),
859 	.resource	= da8xx_rproc_resources,
860 };
861 
862 static bool rproc_mem_inited __initdata;
863 
864 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
865 
866 static phys_addr_t rproc_base __initdata;
867 static unsigned long rproc_size __initdata;
868 
869 static int __init early_rproc_mem(char *p)
870 {
871 	char *endp;
872 
873 	if (p == NULL)
874 		return 0;
875 
876 	rproc_size = memparse(p, &endp);
877 	if (*endp == '@')
878 		rproc_base = memparse(endp + 1, NULL);
879 
880 	return 0;
881 }
882 early_param("rproc_mem", early_rproc_mem);
883 
884 void __init da8xx_rproc_reserve_cma(void)
885 {
886 	struct cma *cma;
887 	int ret;
888 
889 	if (!rproc_base || !rproc_size) {
890 		pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
891 		       "    'nn' and 'address' must both be non-zero\n",
892 		       __func__);
893 
894 		return;
895 	}
896 
897 	pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
898 		__func__, rproc_size, (unsigned long)rproc_base);
899 
900 	ret = dma_contiguous_reserve_area(rproc_size, rproc_base, 0, &cma,
901 			true);
902 	if (ret) {
903 		pr_err("%s: dma_contiguous_reserve_area failed %d\n",
904 			__func__, ret);
905 		return;
906 	}
907 	da8xx_dsp.dev.cma_area = cma;
908 	rproc_mem_inited = true;
909 }
910 #else
911 
912 void __init da8xx_rproc_reserve_cma(void)
913 {
914 }
915 
916 #endif
917 
918 int __init da8xx_register_rproc(void)
919 {
920 	int ret;
921 
922 	if (!rproc_mem_inited) {
923 		pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
924 			__func__);
925 		return -ENOMEM;
926 	}
927 
928 	ret = platform_device_register(&da8xx_dsp);
929 	if (ret)
930 		pr_err("%s: can't register DSP device: %d\n", __func__, ret);
931 
932 	return ret;
933 };
934 
935 static struct resource da8xx_rtc_resources[] = {
936 	{
937 		.start		= DA8XX_RTC_BASE,
938 		.end		= DA8XX_RTC_BASE + SZ_4K - 1,
939 		.flags		= IORESOURCE_MEM,
940 	},
941 	{ /* timer irq */
942 		.start		= DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
943 		.end		= DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
944 		.flags		= IORESOURCE_IRQ,
945 	},
946 	{ /* alarm irq */
947 		.start		= DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
948 		.end		= DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
949 		.flags		= IORESOURCE_IRQ,
950 	},
951 };
952 
953 static struct platform_device da8xx_rtc_device = {
954 	.name           = "da830-rtc",
955 	.id             = -1,
956 	.num_resources	= ARRAY_SIZE(da8xx_rtc_resources),
957 	.resource	= da8xx_rtc_resources,
958 };
959 
960 int da8xx_register_rtc(void)
961 {
962 	return platform_device_register(&da8xx_rtc_device);
963 }
964 
965 static void __iomem *da8xx_ddr2_ctlr_base;
966 void __iomem * __init da8xx_get_mem_ctlr(void)
967 {
968 	if (da8xx_ddr2_ctlr_base)
969 		return da8xx_ddr2_ctlr_base;
970 
971 	da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
972 	if (!da8xx_ddr2_ctlr_base)
973 		pr_warn("%s: Unable to map DDR2 controller", __func__);
974 
975 	return da8xx_ddr2_ctlr_base;
976 }
977 
978 static struct resource da8xx_cpuidle_resources[] = {
979 	{
980 		.start		= DA8XX_DDR2_CTL_BASE,
981 		.end		= DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
982 		.flags		= IORESOURCE_MEM,
983 	},
984 };
985 
986 /* DA8XX devices support DDR2 power down */
987 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
988 	.ddr2_pdown	= 1,
989 };
990 
991 
992 static struct platform_device da8xx_cpuidle_device = {
993 	.name			= "cpuidle-davinci",
994 	.num_resources		= ARRAY_SIZE(da8xx_cpuidle_resources),
995 	.resource		= da8xx_cpuidle_resources,
996 	.dev = {
997 		.platform_data	= &da8xx_cpuidle_pdata,
998 	},
999 };
1000 
1001 int __init da8xx_register_cpuidle(void)
1002 {
1003 	da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
1004 
1005 	return platform_device_register(&da8xx_cpuidle_device);
1006 }
1007 
1008 static struct resource da8xx_spi0_resources[] = {
1009 	[0] = {
1010 		.start	= DA8XX_SPI0_BASE,
1011 		.end	= DA8XX_SPI0_BASE + SZ_4K - 1,
1012 		.flags	= IORESOURCE_MEM,
1013 	},
1014 	[1] = {
1015 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
1016 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
1017 		.flags	= IORESOURCE_IRQ,
1018 	},
1019 };
1020 
1021 static struct resource da8xx_spi1_resources[] = {
1022 	[0] = {
1023 		.start	= DA830_SPI1_BASE,
1024 		.end	= DA830_SPI1_BASE + SZ_4K - 1,
1025 		.flags	= IORESOURCE_MEM,
1026 	},
1027 	[1] = {
1028 		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
1029 		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
1030 		.flags	= IORESOURCE_IRQ,
1031 	},
1032 };
1033 
1034 static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
1035 	[0] = {
1036 		.version	= SPI_VERSION_2,
1037 		.intr_line	= 1,
1038 		.dma_event_q	= EVENTQ_0,
1039 		.prescaler_limit = 2,
1040 	},
1041 	[1] = {
1042 		.version	= SPI_VERSION_2,
1043 		.intr_line	= 1,
1044 		.dma_event_q	= EVENTQ_0,
1045 		.prescaler_limit = 2,
1046 	},
1047 };
1048 
1049 static struct platform_device da8xx_spi_device[] = {
1050 	[0] = {
1051 		.name		= "spi_davinci",
1052 		.id		= 0,
1053 		.num_resources	= ARRAY_SIZE(da8xx_spi0_resources),
1054 		.resource	= da8xx_spi0_resources,
1055 		.dev		= {
1056 			.platform_data = &da8xx_spi_pdata[0],
1057 		},
1058 	},
1059 	[1] = {
1060 		.name		= "spi_davinci",
1061 		.id		= 1,
1062 		.num_resources	= ARRAY_SIZE(da8xx_spi1_resources),
1063 		.resource	= da8xx_spi1_resources,
1064 		.dev		= {
1065 			.platform_data = &da8xx_spi_pdata[1],
1066 		},
1067 	},
1068 };
1069 
1070 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
1071 {
1072 	if (instance < 0 || instance > 1)
1073 		return -EINVAL;
1074 
1075 	da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
1076 
1077 	if (instance == 1 && cpu_is_davinci_da850()) {
1078 		da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
1079 		da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
1080 	}
1081 
1082 	return platform_device_register(&da8xx_spi_device[instance]);
1083 }
1084 
1085 #ifdef CONFIG_ARCH_DAVINCI_DA850
1086 int __init da850_register_sata_refclk(int rate)
1087 {
1088 	struct clk *clk;
1089 
1090 	clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate);
1091 	if (IS_ERR(clk))
1092 		return PTR_ERR(clk);
1093 
1094 	return clk_register_clkdev(clk, "refclk", "ahci_da850");
1095 }
1096 
1097 static struct resource da850_sata_resources[] = {
1098 	{
1099 		.start	= DA850_SATA_BASE,
1100 		.end	= DA850_SATA_BASE + 0x1fff,
1101 		.flags	= IORESOURCE_MEM,
1102 	},
1103 	{
1104 		.start	= DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
1105 		.end	= DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
1106 		.flags	= IORESOURCE_MEM,
1107 	},
1108 	{
1109 		.start	= DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT),
1110 		.flags	= IORESOURCE_IRQ,
1111 	},
1112 };
1113 
1114 static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1115 
1116 static struct platform_device da850_sata_device = {
1117 	.name	= "ahci_da850",
1118 	.id	= -1,
1119 	.dev	= {
1120 		.dma_mask		= &da850_sata_dmamask,
1121 		.coherent_dma_mask	= DMA_BIT_MASK(32),
1122 	},
1123 	.num_resources	= ARRAY_SIZE(da850_sata_resources),
1124 	.resource	= da850_sata_resources,
1125 };
1126 
1127 int __init da850_register_sata(unsigned long refclkpn)
1128 {
1129 	int ret;
1130 
1131 	ret = da850_register_sata_refclk(refclkpn);
1132 	if (ret)
1133 		return ret;
1134 
1135 	return platform_device_register(&da850_sata_device);
1136 }
1137 #endif
1138 
1139 static struct regmap *da8xx_cfgchip;
1140 
1141 static const struct regmap_config da8xx_cfgchip_config __initconst = {
1142 	.name		= "cfgchip",
1143 	.reg_bits	= 32,
1144 	.val_bits	= 32,
1145 	.reg_stride	= 4,
1146 	.max_register	= DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG,
1147 };
1148 
1149 /**
1150  * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap
1151  *
1152  * This is for use on non-DT boards only. For DT boards, use
1153  * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip")
1154  *
1155  * Returns: Pointer to the CFGCHIP regmap or negative error code.
1156  */
1157 struct regmap * __init da8xx_get_cfgchip(void)
1158 {
1159 	if (IS_ERR_OR_NULL(da8xx_cfgchip))
1160 		da8xx_cfgchip = regmap_init_mmio(NULL,
1161 					DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG),
1162 					&da8xx_cfgchip_config);
1163 
1164 	return da8xx_cfgchip;
1165 }
1166