1 /* 2 * DA8XX/OMAP L1XX platform device data 3 * 4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> 5 * Derived from code that was: 6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 #include <linux/ahci_platform.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clk.h> 16 #include <linux/clkdev.h> 17 #include <linux/dma-contiguous.h> 18 #include <linux/dmaengine.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/platform_device.h> 22 #include <linux/reboot.h> 23 #include <linux/serial_8250.h> 24 25 #include <mach/common.h> 26 #include <mach/cputype.h> 27 #include <mach/da8xx.h> 28 #include <mach/time.h> 29 30 #include "asp.h" 31 #include "cpuidle.h" 32 #include "irqs.h" 33 #include "sram.h" 34 35 #define DA8XX_TPCC_BASE 0x01c00000 36 #define DA8XX_TPTC0_BASE 0x01c08000 37 #define DA8XX_TPTC1_BASE 0x01c08400 38 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ 39 #define DA8XX_I2C0_BASE 0x01c22000 40 #define DA8XX_RTC_BASE 0x01c23000 41 #define DA8XX_PRUSS_MEM_BASE 0x01c30000 42 #define DA8XX_MMCSD0_BASE 0x01c40000 43 #define DA8XX_SPI0_BASE 0x01c41000 44 #define DA830_SPI1_BASE 0x01e12000 45 #define DA8XX_LCD_CNTRL_BASE 0x01e13000 46 #define DA850_SATA_BASE 0x01e18000 47 #define DA850_MMCSD1_BASE 0x01e1b000 48 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 49 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 50 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 51 #define DA8XX_EMAC_MDIO_BASE 0x01e24000 52 #define DA8XX_I2C1_BASE 0x01e28000 53 #define DA850_TPCC1_BASE 0x01e30000 54 #define DA850_TPTC2_BASE 0x01e38000 55 #define DA850_SPI1_BASE 0x01f0e000 56 #define DA8XX_DDR2_CTL_BASE 0xb0000000 57 58 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 59 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 60 #define DA8XX_EMAC_RAM_OFFSET 0x0000 61 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K 62 63 void __iomem *da8xx_syscfg0_base; 64 void __iomem *da8xx_syscfg1_base; 65 66 static struct plat_serial8250_port da8xx_serial0_pdata[] = { 67 { 68 .mapbase = DA8XX_UART0_BASE, 69 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0), 70 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 71 UPF_IOREMAP, 72 .iotype = UPIO_MEM, 73 .regshift = 2, 74 }, 75 { 76 .flags = 0, 77 } 78 }; 79 static struct plat_serial8250_port da8xx_serial1_pdata[] = { 80 { 81 .mapbase = DA8XX_UART1_BASE, 82 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1), 83 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 84 UPF_IOREMAP, 85 .iotype = UPIO_MEM, 86 .regshift = 2, 87 }, 88 { 89 .flags = 0, 90 } 91 }; 92 static struct plat_serial8250_port da8xx_serial2_pdata[] = { 93 { 94 .mapbase = DA8XX_UART2_BASE, 95 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2), 96 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 97 UPF_IOREMAP, 98 .iotype = UPIO_MEM, 99 .regshift = 2, 100 }, 101 { 102 .flags = 0, 103 } 104 }; 105 106 struct platform_device da8xx_serial_device[] = { 107 { 108 .name = "serial8250", 109 .id = PLAT8250_DEV_PLATFORM, 110 .dev = { 111 .platform_data = da8xx_serial0_pdata, 112 } 113 }, 114 { 115 .name = "serial8250", 116 .id = PLAT8250_DEV_PLATFORM1, 117 .dev = { 118 .platform_data = da8xx_serial1_pdata, 119 } 120 }, 121 { 122 .name = "serial8250", 123 .id = PLAT8250_DEV_PLATFORM2, 124 .dev = { 125 .platform_data = da8xx_serial2_pdata, 126 } 127 }, 128 { 129 } 130 }; 131 132 static s8 da8xx_queue_priority_mapping[][2] = { 133 /* {event queue no, Priority} */ 134 {0, 3}, 135 {1, 7}, 136 {-1, -1} 137 }; 138 139 static s8 da850_queue_priority_mapping[][2] = { 140 /* {event queue no, Priority} */ 141 {0, 3}, 142 {-1, -1} 143 }; 144 145 static struct edma_soc_info da8xx_edma0_pdata = { 146 .queue_priority_mapping = da8xx_queue_priority_mapping, 147 .default_queue = EVENTQ_1, 148 }; 149 150 static struct edma_soc_info da850_edma1_pdata = { 151 .queue_priority_mapping = da850_queue_priority_mapping, 152 .default_queue = EVENTQ_0, 153 }; 154 155 static struct resource da8xx_edma0_resources[] = { 156 { 157 .name = "edma3_cc", 158 .start = DA8XX_TPCC_BASE, 159 .end = DA8XX_TPCC_BASE + SZ_32K - 1, 160 .flags = IORESOURCE_MEM, 161 }, 162 { 163 .name = "edma3_tc0", 164 .start = DA8XX_TPTC0_BASE, 165 .end = DA8XX_TPTC0_BASE + SZ_1K - 1, 166 .flags = IORESOURCE_MEM, 167 }, 168 { 169 .name = "edma3_tc1", 170 .start = DA8XX_TPTC1_BASE, 171 .end = DA8XX_TPTC1_BASE + SZ_1K - 1, 172 .flags = IORESOURCE_MEM, 173 }, 174 { 175 .name = "edma3_ccint", 176 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0), 177 .flags = IORESOURCE_IRQ, 178 }, 179 { 180 .name = "edma3_ccerrint", 181 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT), 182 .flags = IORESOURCE_IRQ, 183 }, 184 }; 185 186 static struct resource da850_edma1_resources[] = { 187 { 188 .name = "edma3_cc", 189 .start = DA850_TPCC1_BASE, 190 .end = DA850_TPCC1_BASE + SZ_32K - 1, 191 .flags = IORESOURCE_MEM, 192 }, 193 { 194 .name = "edma3_tc0", 195 .start = DA850_TPTC2_BASE, 196 .end = DA850_TPTC2_BASE + SZ_1K - 1, 197 .flags = IORESOURCE_MEM, 198 }, 199 { 200 .name = "edma3_ccint", 201 .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1), 202 .flags = IORESOURCE_IRQ, 203 }, 204 { 205 .name = "edma3_ccerrint", 206 .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1), 207 .flags = IORESOURCE_IRQ, 208 }, 209 }; 210 211 static const struct platform_device_info da8xx_edma0_device __initconst = { 212 .name = "edma", 213 .id = 0, 214 .dma_mask = DMA_BIT_MASK(32), 215 .res = da8xx_edma0_resources, 216 .num_res = ARRAY_SIZE(da8xx_edma0_resources), 217 .data = &da8xx_edma0_pdata, 218 .size_data = sizeof(da8xx_edma0_pdata), 219 }; 220 221 static const struct platform_device_info da850_edma1_device __initconst = { 222 .name = "edma", 223 .id = 1, 224 .dma_mask = DMA_BIT_MASK(32), 225 .res = da850_edma1_resources, 226 .num_res = ARRAY_SIZE(da850_edma1_resources), 227 .data = &da850_edma1_pdata, 228 .size_data = sizeof(da850_edma1_pdata), 229 }; 230 231 static const struct dma_slave_map da830_edma_map[] = { 232 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) }, 233 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) }, 234 { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) }, 235 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) }, 236 { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) }, 237 { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) }, 238 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) }, 239 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) }, 240 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) }, 241 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) }, 242 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) }, 243 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) }, 244 }; 245 246 int __init da830_register_edma(struct edma_rsv_info *rsv) 247 { 248 struct platform_device *edma_pdev; 249 250 da8xx_edma0_pdata.rsv = rsv; 251 252 da8xx_edma0_pdata.slave_map = da830_edma_map; 253 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map); 254 255 edma_pdev = platform_device_register_full(&da8xx_edma0_device); 256 return PTR_ERR_OR_ZERO(edma_pdev); 257 } 258 259 static const struct dma_slave_map da850_edma0_map[] = { 260 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) }, 261 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) }, 262 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) }, 263 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) }, 264 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) }, 265 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) }, 266 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) }, 267 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) }, 268 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) }, 269 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) }, 270 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) }, 271 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) }, 272 }; 273 274 static const struct dma_slave_map da850_edma1_map[] = { 275 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) }, 276 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) }, 277 }; 278 279 int __init da850_register_edma(struct edma_rsv_info *rsv[2]) 280 { 281 struct platform_device *edma_pdev; 282 283 if (rsv) { 284 da8xx_edma0_pdata.rsv = rsv[0]; 285 da850_edma1_pdata.rsv = rsv[1]; 286 } 287 288 da8xx_edma0_pdata.slave_map = da850_edma0_map; 289 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map); 290 291 edma_pdev = platform_device_register_full(&da8xx_edma0_device); 292 if (IS_ERR(edma_pdev)) { 293 pr_warn("%s: Failed to register eDMA0\n", __func__); 294 return PTR_ERR(edma_pdev); 295 } 296 297 da850_edma1_pdata.slave_map = da850_edma1_map; 298 da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map); 299 300 edma_pdev = platform_device_register_full(&da850_edma1_device); 301 return PTR_ERR_OR_ZERO(edma_pdev); 302 } 303 304 static struct resource da8xx_i2c_resources0[] = { 305 { 306 .start = DA8XX_I2C0_BASE, 307 .end = DA8XX_I2C0_BASE + SZ_4K - 1, 308 .flags = IORESOURCE_MEM, 309 }, 310 { 311 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0), 312 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0), 313 .flags = IORESOURCE_IRQ, 314 }, 315 }; 316 317 static struct platform_device da8xx_i2c_device0 = { 318 .name = "i2c_davinci", 319 .id = 1, 320 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), 321 .resource = da8xx_i2c_resources0, 322 }; 323 324 static struct resource da8xx_i2c_resources1[] = { 325 { 326 .start = DA8XX_I2C1_BASE, 327 .end = DA8XX_I2C1_BASE + SZ_4K - 1, 328 .flags = IORESOURCE_MEM, 329 }, 330 { 331 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1), 332 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1), 333 .flags = IORESOURCE_IRQ, 334 }, 335 }; 336 337 static struct platform_device da8xx_i2c_device1 = { 338 .name = "i2c_davinci", 339 .id = 2, 340 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), 341 .resource = da8xx_i2c_resources1, 342 }; 343 344 int __init da8xx_register_i2c(int instance, 345 struct davinci_i2c_platform_data *pdata) 346 { 347 struct platform_device *pdev; 348 349 if (instance == 0) 350 pdev = &da8xx_i2c_device0; 351 else if (instance == 1) 352 pdev = &da8xx_i2c_device1; 353 else 354 return -EINVAL; 355 356 pdev->dev.platform_data = pdata; 357 return platform_device_register(pdev); 358 } 359 360 static struct resource da8xx_watchdog_resources[] = { 361 { 362 .start = DA8XX_WDOG_BASE, 363 .end = DA8XX_WDOG_BASE + SZ_4K - 1, 364 .flags = IORESOURCE_MEM, 365 }, 366 }; 367 368 static struct platform_device da8xx_wdt_device = { 369 .name = "davinci-wdt", 370 .id = -1, 371 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), 372 .resource = da8xx_watchdog_resources, 373 }; 374 375 int __init da8xx_register_watchdog(void) 376 { 377 return platform_device_register(&da8xx_wdt_device); 378 } 379 380 static struct resource da8xx_emac_resources[] = { 381 { 382 .start = DA8XX_EMAC_CPPI_PORT_BASE, 383 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1, 384 .flags = IORESOURCE_MEM, 385 }, 386 { 387 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE), 388 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE), 389 .flags = IORESOURCE_IRQ, 390 }, 391 { 392 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE), 393 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE), 394 .flags = IORESOURCE_IRQ, 395 }, 396 { 397 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE), 398 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE), 399 .flags = IORESOURCE_IRQ, 400 }, 401 { 402 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE), 403 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE), 404 .flags = IORESOURCE_IRQ, 405 }, 406 }; 407 408 struct emac_platform_data da8xx_emac_pdata = { 409 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, 410 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, 411 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, 412 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, 413 .version = EMAC_VERSION_2, 414 }; 415 416 static struct platform_device da8xx_emac_device = { 417 .name = "davinci_emac", 418 .id = 1, 419 .dev = { 420 .platform_data = &da8xx_emac_pdata, 421 }, 422 .num_resources = ARRAY_SIZE(da8xx_emac_resources), 423 .resource = da8xx_emac_resources, 424 }; 425 426 static struct resource da8xx_mdio_resources[] = { 427 { 428 .start = DA8XX_EMAC_MDIO_BASE, 429 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1, 430 .flags = IORESOURCE_MEM, 431 }, 432 }; 433 434 static struct platform_device da8xx_mdio_device = { 435 .name = "davinci_mdio", 436 .id = 0, 437 .num_resources = ARRAY_SIZE(da8xx_mdio_resources), 438 .resource = da8xx_mdio_resources, 439 }; 440 441 int __init da8xx_register_emac(void) 442 { 443 int ret; 444 445 ret = platform_device_register(&da8xx_mdio_device); 446 if (ret < 0) 447 return ret; 448 449 return platform_device_register(&da8xx_emac_device); 450 } 451 452 static struct resource da830_mcasp1_resources[] = { 453 { 454 .name = "mpu", 455 .start = DAVINCI_DA830_MCASP1_REG_BASE, 456 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, 457 .flags = IORESOURCE_MEM, 458 }, 459 /* TX event */ 460 { 461 .name = "tx", 462 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, 463 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, 464 .flags = IORESOURCE_DMA, 465 }, 466 /* RX event */ 467 { 468 .name = "rx", 469 .start = DAVINCI_DA830_DMA_MCASP1_AREVT, 470 .end = DAVINCI_DA830_DMA_MCASP1_AREVT, 471 .flags = IORESOURCE_DMA, 472 }, 473 { 474 .name = "common", 475 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT), 476 .flags = IORESOURCE_IRQ, 477 }, 478 }; 479 480 static struct platform_device da830_mcasp1_device = { 481 .name = "davinci-mcasp", 482 .id = 1, 483 .num_resources = ARRAY_SIZE(da830_mcasp1_resources), 484 .resource = da830_mcasp1_resources, 485 }; 486 487 static struct resource da830_mcasp2_resources[] = { 488 { 489 .name = "mpu", 490 .start = DAVINCI_DA830_MCASP2_REG_BASE, 491 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1, 492 .flags = IORESOURCE_MEM, 493 }, 494 /* TX event */ 495 { 496 .name = "tx", 497 .start = DAVINCI_DA830_DMA_MCASP2_AXEVT, 498 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT, 499 .flags = IORESOURCE_DMA, 500 }, 501 /* RX event */ 502 { 503 .name = "rx", 504 .start = DAVINCI_DA830_DMA_MCASP2_AREVT, 505 .end = DAVINCI_DA830_DMA_MCASP2_AREVT, 506 .flags = IORESOURCE_DMA, 507 }, 508 { 509 .name = "common", 510 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT), 511 .flags = IORESOURCE_IRQ, 512 }, 513 }; 514 515 static struct platform_device da830_mcasp2_device = { 516 .name = "davinci-mcasp", 517 .id = 2, 518 .num_resources = ARRAY_SIZE(da830_mcasp2_resources), 519 .resource = da830_mcasp2_resources, 520 }; 521 522 static struct resource da850_mcasp_resources[] = { 523 { 524 .name = "mpu", 525 .start = DAVINCI_DA8XX_MCASP0_REG_BASE, 526 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, 527 .flags = IORESOURCE_MEM, 528 }, 529 /* TX event */ 530 { 531 .name = "tx", 532 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 533 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 534 .flags = IORESOURCE_DMA, 535 }, 536 /* RX event */ 537 { 538 .name = "rx", 539 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 540 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 541 .flags = IORESOURCE_DMA, 542 }, 543 { 544 .name = "common", 545 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT), 546 .flags = IORESOURCE_IRQ, 547 }, 548 }; 549 550 static struct platform_device da850_mcasp_device = { 551 .name = "davinci-mcasp", 552 .id = 0, 553 .num_resources = ARRAY_SIZE(da850_mcasp_resources), 554 .resource = da850_mcasp_resources, 555 }; 556 557 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) 558 { 559 struct platform_device *pdev; 560 561 switch (id) { 562 case 0: 563 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */ 564 pdev = &da850_mcasp_device; 565 break; 566 case 1: 567 /* Valid for DA830/OMAP-L137 only */ 568 if (!cpu_is_davinci_da830()) 569 return; 570 pdev = &da830_mcasp1_device; 571 break; 572 case 2: 573 /* Valid for DA830/OMAP-L137 only */ 574 if (!cpu_is_davinci_da830()) 575 return; 576 pdev = &da830_mcasp2_device; 577 break; 578 default: 579 return; 580 } 581 582 pdev->dev.platform_data = pdata; 583 platform_device_register(pdev); 584 } 585 586 static struct resource da8xx_pruss_resources[] = { 587 { 588 .start = DA8XX_PRUSS_MEM_BASE, 589 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF, 590 .flags = IORESOURCE_MEM, 591 }, 592 { 593 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0), 594 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0), 595 .flags = IORESOURCE_IRQ, 596 }, 597 { 598 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1), 599 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1), 600 .flags = IORESOURCE_IRQ, 601 }, 602 { 603 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2), 604 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2), 605 .flags = IORESOURCE_IRQ, 606 }, 607 { 608 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3), 609 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3), 610 .flags = IORESOURCE_IRQ, 611 }, 612 { 613 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4), 614 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4), 615 .flags = IORESOURCE_IRQ, 616 }, 617 { 618 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5), 619 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5), 620 .flags = IORESOURCE_IRQ, 621 }, 622 { 623 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6), 624 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6), 625 .flags = IORESOURCE_IRQ, 626 }, 627 { 628 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7), 629 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7), 630 .flags = IORESOURCE_IRQ, 631 }, 632 }; 633 634 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = { 635 .pintc_base = 0x4000, 636 }; 637 638 static struct platform_device da8xx_uio_pruss_dev = { 639 .name = "pruss_uio", 640 .id = -1, 641 .num_resources = ARRAY_SIZE(da8xx_pruss_resources), 642 .resource = da8xx_pruss_resources, 643 .dev = { 644 .coherent_dma_mask = DMA_BIT_MASK(32), 645 .platform_data = &da8xx_uio_pruss_pdata, 646 } 647 }; 648 649 int __init da8xx_register_uio_pruss(void) 650 { 651 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool(); 652 return platform_device_register(&da8xx_uio_pruss_dev); 653 } 654 655 static struct lcd_ctrl_config lcd_cfg = { 656 .panel_shade = COLOR_ACTIVE, 657 .bpp = 16, 658 }; 659 660 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = { 661 .manu_name = "sharp", 662 .controller_data = &lcd_cfg, 663 .type = "Sharp_LCD035Q3DG01", 664 }; 665 666 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = { 667 .manu_name = "sharp", 668 .controller_data = &lcd_cfg, 669 .type = "Sharp_LK043T1DG01", 670 }; 671 672 static struct resource da8xx_lcdc_resources[] = { 673 [0] = { /* registers */ 674 .start = DA8XX_LCD_CNTRL_BASE, 675 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, 676 .flags = IORESOURCE_MEM, 677 }, 678 [1] = { /* interrupt */ 679 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT), 680 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT), 681 .flags = IORESOURCE_IRQ, 682 }, 683 }; 684 685 static struct platform_device da8xx_lcdc_device = { 686 .name = "da8xx_lcdc", 687 .id = 0, 688 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), 689 .resource = da8xx_lcdc_resources, 690 }; 691 692 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) 693 { 694 da8xx_lcdc_device.dev.platform_data = pdata; 695 return platform_device_register(&da8xx_lcdc_device); 696 } 697 698 static struct resource da8xx_gpio_resources[] = { 699 { /* registers */ 700 .start = DA8XX_GPIO_BASE, 701 .end = DA8XX_GPIO_BASE + SZ_4K - 1, 702 .flags = IORESOURCE_MEM, 703 }, 704 { /* interrupt */ 705 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0), 706 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0), 707 .flags = IORESOURCE_IRQ, 708 }, 709 { 710 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1), 711 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1), 712 .flags = IORESOURCE_IRQ, 713 }, 714 { 715 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2), 716 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2), 717 .flags = IORESOURCE_IRQ, 718 }, 719 { 720 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3), 721 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3), 722 .flags = IORESOURCE_IRQ, 723 }, 724 { 725 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4), 726 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4), 727 .flags = IORESOURCE_IRQ, 728 }, 729 { 730 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5), 731 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5), 732 .flags = IORESOURCE_IRQ, 733 }, 734 { 735 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6), 736 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6), 737 .flags = IORESOURCE_IRQ, 738 }, 739 { 740 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7), 741 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7), 742 .flags = IORESOURCE_IRQ, 743 }, 744 { 745 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8), 746 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8), 747 .flags = IORESOURCE_IRQ, 748 }, 749 }; 750 751 static struct platform_device da8xx_gpio_device = { 752 .name = "davinci_gpio", 753 .id = -1, 754 .num_resources = ARRAY_SIZE(da8xx_gpio_resources), 755 .resource = da8xx_gpio_resources, 756 }; 757 758 int __init da8xx_register_gpio(void *pdata) 759 { 760 da8xx_gpio_device.dev.platform_data = pdata; 761 return platform_device_register(&da8xx_gpio_device); 762 } 763 764 static struct resource da8xx_mmcsd0_resources[] = { 765 { /* registers */ 766 .start = DA8XX_MMCSD0_BASE, 767 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, 768 .flags = IORESOURCE_MEM, 769 }, 770 { /* interrupt */ 771 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0), 772 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0), 773 .flags = IORESOURCE_IRQ, 774 }, 775 }; 776 777 static struct platform_device da8xx_mmcsd0_device = { 778 .name = "da830-mmc", 779 .id = 0, 780 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), 781 .resource = da8xx_mmcsd0_resources, 782 }; 783 784 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) 785 { 786 da8xx_mmcsd0_device.dev.platform_data = config; 787 return platform_device_register(&da8xx_mmcsd0_device); 788 } 789 790 #ifdef CONFIG_ARCH_DAVINCI_DA850 791 static struct resource da850_mmcsd1_resources[] = { 792 { /* registers */ 793 .start = DA850_MMCSD1_BASE, 794 .end = DA850_MMCSD1_BASE + SZ_4K - 1, 795 .flags = IORESOURCE_MEM, 796 }, 797 { /* interrupt */ 798 .start = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1), 799 .end = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1), 800 .flags = IORESOURCE_IRQ, 801 }, 802 }; 803 804 static struct platform_device da850_mmcsd1_device = { 805 .name = "da830-mmc", 806 .id = 1, 807 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), 808 .resource = da850_mmcsd1_resources, 809 }; 810 811 int __init da850_register_mmcsd1(struct davinci_mmc_config *config) 812 { 813 da850_mmcsd1_device.dev.platform_data = config; 814 return platform_device_register(&da850_mmcsd1_device); 815 } 816 #endif 817 818 static struct resource da8xx_rproc_resources[] = { 819 { /* DSP boot address */ 820 .name = "host1cfg", 821 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG, 822 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3, 823 .flags = IORESOURCE_MEM, 824 }, 825 { /* DSP interrupt registers */ 826 .name = "chipsig", 827 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG, 828 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7, 829 .flags = IORESOURCE_MEM, 830 }, 831 { /* DSP L2 RAM */ 832 .name = "l2sram", 833 .start = DA8XX_DSP_L2_RAM_BASE, 834 .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1, 835 .flags = IORESOURCE_MEM, 836 }, 837 { /* DSP L1P RAM */ 838 .name = "l1pram", 839 .start = DA8XX_DSP_L1P_RAM_BASE, 840 .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1, 841 .flags = IORESOURCE_MEM, 842 }, 843 { /* DSP L1D RAM */ 844 .name = "l1dram", 845 .start = DA8XX_DSP_L1D_RAM_BASE, 846 .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1, 847 .flags = IORESOURCE_MEM, 848 }, 849 { /* dsp irq */ 850 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0), 851 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0), 852 .flags = IORESOURCE_IRQ, 853 }, 854 }; 855 856 static struct platform_device da8xx_dsp = { 857 .name = "davinci-rproc", 858 .dev = { 859 .coherent_dma_mask = DMA_BIT_MASK(32), 860 }, 861 .num_resources = ARRAY_SIZE(da8xx_rproc_resources), 862 .resource = da8xx_rproc_resources, 863 }; 864 865 static bool rproc_mem_inited __initdata; 866 867 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC) 868 869 static phys_addr_t rproc_base __initdata; 870 static unsigned long rproc_size __initdata; 871 872 static int __init early_rproc_mem(char *p) 873 { 874 char *endp; 875 876 if (p == NULL) 877 return 0; 878 879 rproc_size = memparse(p, &endp); 880 if (*endp == '@') 881 rproc_base = memparse(endp + 1, NULL); 882 883 return 0; 884 } 885 early_param("rproc_mem", early_rproc_mem); 886 887 void __init da8xx_rproc_reserve_cma(void) 888 { 889 int ret; 890 891 if (!rproc_base || !rproc_size) { 892 pr_err("%s: 'rproc_mem=nn@address' badly specified\n" 893 " 'nn' and 'address' must both be non-zero\n", 894 __func__); 895 896 return; 897 } 898 899 pr_info("%s: reserving 0x%lx @ 0x%lx...\n", 900 __func__, rproc_size, (unsigned long)rproc_base); 901 902 ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0); 903 if (ret) 904 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret); 905 else 906 rproc_mem_inited = true; 907 } 908 909 #else 910 911 void __init da8xx_rproc_reserve_cma(void) 912 { 913 } 914 915 #endif 916 917 int __init da8xx_register_rproc(void) 918 { 919 int ret; 920 921 if (!rproc_mem_inited) { 922 pr_warn("%s: memory not reserved for DSP, not registering DSP device\n", 923 __func__); 924 return -ENOMEM; 925 } 926 927 ret = platform_device_register(&da8xx_dsp); 928 if (ret) 929 pr_err("%s: can't register DSP device: %d\n", __func__, ret); 930 931 return ret; 932 }; 933 934 static struct resource da8xx_rtc_resources[] = { 935 { 936 .start = DA8XX_RTC_BASE, 937 .end = DA8XX_RTC_BASE + SZ_4K - 1, 938 .flags = IORESOURCE_MEM, 939 }, 940 { /* timer irq */ 941 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), 942 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), 943 .flags = IORESOURCE_IRQ, 944 }, 945 { /* alarm irq */ 946 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), 947 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), 948 .flags = IORESOURCE_IRQ, 949 }, 950 }; 951 952 static struct platform_device da8xx_rtc_device = { 953 .name = "da830-rtc", 954 .id = -1, 955 .num_resources = ARRAY_SIZE(da8xx_rtc_resources), 956 .resource = da8xx_rtc_resources, 957 }; 958 959 int da8xx_register_rtc(void) 960 { 961 return platform_device_register(&da8xx_rtc_device); 962 } 963 964 static void __iomem *da8xx_ddr2_ctlr_base; 965 void __iomem * __init da8xx_get_mem_ctlr(void) 966 { 967 if (da8xx_ddr2_ctlr_base) 968 return da8xx_ddr2_ctlr_base; 969 970 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K); 971 if (!da8xx_ddr2_ctlr_base) 972 pr_warn("%s: Unable to map DDR2 controller", __func__); 973 974 return da8xx_ddr2_ctlr_base; 975 } 976 977 static struct resource da8xx_cpuidle_resources[] = { 978 { 979 .start = DA8XX_DDR2_CTL_BASE, 980 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1, 981 .flags = IORESOURCE_MEM, 982 }, 983 }; 984 985 /* DA8XX devices support DDR2 power down */ 986 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = { 987 .ddr2_pdown = 1, 988 }; 989 990 991 static struct platform_device da8xx_cpuidle_device = { 992 .name = "cpuidle-davinci", 993 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources), 994 .resource = da8xx_cpuidle_resources, 995 .dev = { 996 .platform_data = &da8xx_cpuidle_pdata, 997 }, 998 }; 999 1000 int __init da8xx_register_cpuidle(void) 1001 { 1002 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr(); 1003 1004 return platform_device_register(&da8xx_cpuidle_device); 1005 } 1006 1007 static struct resource da8xx_spi0_resources[] = { 1008 [0] = { 1009 .start = DA8XX_SPI0_BASE, 1010 .end = DA8XX_SPI0_BASE + SZ_4K - 1, 1011 .flags = IORESOURCE_MEM, 1012 }, 1013 [1] = { 1014 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0), 1015 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0), 1016 .flags = IORESOURCE_IRQ, 1017 }, 1018 }; 1019 1020 static struct resource da8xx_spi1_resources[] = { 1021 [0] = { 1022 .start = DA830_SPI1_BASE, 1023 .end = DA830_SPI1_BASE + SZ_4K - 1, 1024 .flags = IORESOURCE_MEM, 1025 }, 1026 [1] = { 1027 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1), 1028 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1), 1029 .flags = IORESOURCE_IRQ, 1030 }, 1031 }; 1032 1033 static struct davinci_spi_platform_data da8xx_spi_pdata[] = { 1034 [0] = { 1035 .version = SPI_VERSION_2, 1036 .intr_line = 1, 1037 .dma_event_q = EVENTQ_0, 1038 .prescaler_limit = 2, 1039 }, 1040 [1] = { 1041 .version = SPI_VERSION_2, 1042 .intr_line = 1, 1043 .dma_event_q = EVENTQ_0, 1044 .prescaler_limit = 2, 1045 }, 1046 }; 1047 1048 static struct platform_device da8xx_spi_device[] = { 1049 [0] = { 1050 .name = "spi_davinci", 1051 .id = 0, 1052 .num_resources = ARRAY_SIZE(da8xx_spi0_resources), 1053 .resource = da8xx_spi0_resources, 1054 .dev = { 1055 .platform_data = &da8xx_spi_pdata[0], 1056 }, 1057 }, 1058 [1] = { 1059 .name = "spi_davinci", 1060 .id = 1, 1061 .num_resources = ARRAY_SIZE(da8xx_spi1_resources), 1062 .resource = da8xx_spi1_resources, 1063 .dev = { 1064 .platform_data = &da8xx_spi_pdata[1], 1065 }, 1066 }, 1067 }; 1068 1069 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect) 1070 { 1071 if (instance < 0 || instance > 1) 1072 return -EINVAL; 1073 1074 da8xx_spi_pdata[instance].num_chipselect = num_chipselect; 1075 1076 if (instance == 1 && cpu_is_davinci_da850()) { 1077 da8xx_spi1_resources[0].start = DA850_SPI1_BASE; 1078 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; 1079 } 1080 1081 return platform_device_register(&da8xx_spi_device[instance]); 1082 } 1083 1084 #ifdef CONFIG_ARCH_DAVINCI_DA850 1085 int __init da850_register_sata_refclk(int rate) 1086 { 1087 struct clk *clk; 1088 1089 clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate); 1090 if (IS_ERR(clk)) 1091 return PTR_ERR(clk); 1092 1093 return clk_register_clkdev(clk, "refclk", "ahci_da850"); 1094 } 1095 1096 static struct resource da850_sata_resources[] = { 1097 { 1098 .start = DA850_SATA_BASE, 1099 .end = DA850_SATA_BASE + 0x1fff, 1100 .flags = IORESOURCE_MEM, 1101 }, 1102 { 1103 .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG, 1104 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3, 1105 .flags = IORESOURCE_MEM, 1106 }, 1107 { 1108 .start = DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT), 1109 .flags = IORESOURCE_IRQ, 1110 }, 1111 }; 1112 1113 static u64 da850_sata_dmamask = DMA_BIT_MASK(32); 1114 1115 static struct platform_device da850_sata_device = { 1116 .name = "ahci_da850", 1117 .id = -1, 1118 .dev = { 1119 .dma_mask = &da850_sata_dmamask, 1120 .coherent_dma_mask = DMA_BIT_MASK(32), 1121 }, 1122 .num_resources = ARRAY_SIZE(da850_sata_resources), 1123 .resource = da850_sata_resources, 1124 }; 1125 1126 int __init da850_register_sata(unsigned long refclkpn) 1127 { 1128 int ret; 1129 1130 ret = da850_register_sata_refclk(refclkpn); 1131 if (ret) 1132 return ret; 1133 1134 return platform_device_register(&da850_sata_device); 1135 } 1136 #endif 1137 1138 static struct regmap *da8xx_cfgchip; 1139 1140 static const struct regmap_config da8xx_cfgchip_config __initconst = { 1141 .name = "cfgchip", 1142 .reg_bits = 32, 1143 .val_bits = 32, 1144 .reg_stride = 4, 1145 .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG, 1146 }; 1147 1148 /** 1149 * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap 1150 * 1151 * This is for use on non-DT boards only. For DT boards, use 1152 * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip") 1153 * 1154 * Returns: Pointer to the CFGCHIP regmap or negative error code. 1155 */ 1156 struct regmap * __init da8xx_get_cfgchip(void) 1157 { 1158 if (IS_ERR_OR_NULL(da8xx_cfgchip)) 1159 da8xx_cfgchip = regmap_init_mmio(NULL, 1160 DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG), 1161 &da8xx_cfgchip_config); 1162 1163 return da8xx_cfgchip; 1164 } 1165