1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DA8XX/OMAP L1XX platform device data 4 * 5 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> 6 * Derived from code that was: 7 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> 8 */ 9 #include <linux/ahci_platform.h> 10 #include <linux/clk-provider.h> 11 #include <linux/clk.h> 12 #include <linux/clkdev.h> 13 #include <linux/dma-contiguous.h> 14 #include <linux/dmaengine.h> 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/platform_device.h> 18 #include <linux/reboot.h> 19 #include <linux/serial_8250.h> 20 21 #include <mach/common.h> 22 #include <mach/cputype.h> 23 #include <mach/da8xx.h> 24 #include <mach/time.h> 25 26 #include "asp.h" 27 #include "cpuidle.h" 28 #include "irqs.h" 29 #include "sram.h" 30 31 #define DA8XX_TPCC_BASE 0x01c00000 32 #define DA8XX_TPTC0_BASE 0x01c08000 33 #define DA8XX_TPTC1_BASE 0x01c08400 34 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ 35 #define DA8XX_I2C0_BASE 0x01c22000 36 #define DA8XX_RTC_BASE 0x01c23000 37 #define DA8XX_PRUSS_MEM_BASE 0x01c30000 38 #define DA8XX_MMCSD0_BASE 0x01c40000 39 #define DA8XX_SPI0_BASE 0x01c41000 40 #define DA830_SPI1_BASE 0x01e12000 41 #define DA8XX_LCD_CNTRL_BASE 0x01e13000 42 #define DA850_SATA_BASE 0x01e18000 43 #define DA850_MMCSD1_BASE 0x01e1b000 44 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 45 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 46 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 47 #define DA8XX_EMAC_MDIO_BASE 0x01e24000 48 #define DA8XX_I2C1_BASE 0x01e28000 49 #define DA850_TPCC1_BASE 0x01e30000 50 #define DA850_TPTC2_BASE 0x01e38000 51 #define DA850_SPI1_BASE 0x01f0e000 52 #define DA8XX_DDR2_CTL_BASE 0xb0000000 53 54 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 55 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 56 #define DA8XX_EMAC_RAM_OFFSET 0x0000 57 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K 58 59 void __iomem *da8xx_syscfg0_base; 60 void __iomem *da8xx_syscfg1_base; 61 62 static struct plat_serial8250_port da8xx_serial0_pdata[] = { 63 { 64 .mapbase = DA8XX_UART0_BASE, 65 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0), 66 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 67 UPF_IOREMAP, 68 .iotype = UPIO_MEM, 69 .regshift = 2, 70 }, 71 { 72 .flags = 0, 73 } 74 }; 75 static struct plat_serial8250_port da8xx_serial1_pdata[] = { 76 { 77 .mapbase = DA8XX_UART1_BASE, 78 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1), 79 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 80 UPF_IOREMAP, 81 .iotype = UPIO_MEM, 82 .regshift = 2, 83 }, 84 { 85 .flags = 0, 86 } 87 }; 88 static struct plat_serial8250_port da8xx_serial2_pdata[] = { 89 { 90 .mapbase = DA8XX_UART2_BASE, 91 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2), 92 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 93 UPF_IOREMAP, 94 .iotype = UPIO_MEM, 95 .regshift = 2, 96 }, 97 { 98 .flags = 0, 99 } 100 }; 101 102 struct platform_device da8xx_serial_device[] = { 103 { 104 .name = "serial8250", 105 .id = PLAT8250_DEV_PLATFORM, 106 .dev = { 107 .platform_data = da8xx_serial0_pdata, 108 } 109 }, 110 { 111 .name = "serial8250", 112 .id = PLAT8250_DEV_PLATFORM1, 113 .dev = { 114 .platform_data = da8xx_serial1_pdata, 115 } 116 }, 117 { 118 .name = "serial8250", 119 .id = PLAT8250_DEV_PLATFORM2, 120 .dev = { 121 .platform_data = da8xx_serial2_pdata, 122 } 123 }, 124 { 125 } 126 }; 127 128 static s8 da8xx_queue_priority_mapping[][2] = { 129 /* {event queue no, Priority} */ 130 {0, 3}, 131 {1, 7}, 132 {-1, -1} 133 }; 134 135 static s8 da850_queue_priority_mapping[][2] = { 136 /* {event queue no, Priority} */ 137 {0, 3}, 138 {-1, -1} 139 }; 140 141 static struct edma_soc_info da8xx_edma0_pdata = { 142 .queue_priority_mapping = da8xx_queue_priority_mapping, 143 .default_queue = EVENTQ_1, 144 }; 145 146 static struct edma_soc_info da850_edma1_pdata = { 147 .queue_priority_mapping = da850_queue_priority_mapping, 148 .default_queue = EVENTQ_0, 149 }; 150 151 static struct resource da8xx_edma0_resources[] = { 152 { 153 .name = "edma3_cc", 154 .start = DA8XX_TPCC_BASE, 155 .end = DA8XX_TPCC_BASE + SZ_32K - 1, 156 .flags = IORESOURCE_MEM, 157 }, 158 { 159 .name = "edma3_tc0", 160 .start = DA8XX_TPTC0_BASE, 161 .end = DA8XX_TPTC0_BASE + SZ_1K - 1, 162 .flags = IORESOURCE_MEM, 163 }, 164 { 165 .name = "edma3_tc1", 166 .start = DA8XX_TPTC1_BASE, 167 .end = DA8XX_TPTC1_BASE + SZ_1K - 1, 168 .flags = IORESOURCE_MEM, 169 }, 170 { 171 .name = "edma3_ccint", 172 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0), 173 .flags = IORESOURCE_IRQ, 174 }, 175 { 176 .name = "edma3_ccerrint", 177 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT), 178 .flags = IORESOURCE_IRQ, 179 }, 180 }; 181 182 static struct resource da850_edma1_resources[] = { 183 { 184 .name = "edma3_cc", 185 .start = DA850_TPCC1_BASE, 186 .end = DA850_TPCC1_BASE + SZ_32K - 1, 187 .flags = IORESOURCE_MEM, 188 }, 189 { 190 .name = "edma3_tc0", 191 .start = DA850_TPTC2_BASE, 192 .end = DA850_TPTC2_BASE + SZ_1K - 1, 193 .flags = IORESOURCE_MEM, 194 }, 195 { 196 .name = "edma3_ccint", 197 .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1), 198 .flags = IORESOURCE_IRQ, 199 }, 200 { 201 .name = "edma3_ccerrint", 202 .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1), 203 .flags = IORESOURCE_IRQ, 204 }, 205 }; 206 207 static const struct platform_device_info da8xx_edma0_device __initconst = { 208 .name = "edma", 209 .id = 0, 210 .dma_mask = DMA_BIT_MASK(32), 211 .res = da8xx_edma0_resources, 212 .num_res = ARRAY_SIZE(da8xx_edma0_resources), 213 .data = &da8xx_edma0_pdata, 214 .size_data = sizeof(da8xx_edma0_pdata), 215 }; 216 217 static const struct platform_device_info da850_edma1_device __initconst = { 218 .name = "edma", 219 .id = 1, 220 .dma_mask = DMA_BIT_MASK(32), 221 .res = da850_edma1_resources, 222 .num_res = ARRAY_SIZE(da850_edma1_resources), 223 .data = &da850_edma1_pdata, 224 .size_data = sizeof(da850_edma1_pdata), 225 }; 226 227 static const struct dma_slave_map da830_edma_map[] = { 228 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) }, 229 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) }, 230 { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) }, 231 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) }, 232 { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) }, 233 { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) }, 234 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) }, 235 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) }, 236 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) }, 237 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) }, 238 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) }, 239 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) }, 240 }; 241 242 int __init da830_register_edma(struct edma_rsv_info *rsv) 243 { 244 struct platform_device *edma_pdev; 245 246 da8xx_edma0_pdata.rsv = rsv; 247 248 da8xx_edma0_pdata.slave_map = da830_edma_map; 249 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map); 250 251 edma_pdev = platform_device_register_full(&da8xx_edma0_device); 252 return PTR_ERR_OR_ZERO(edma_pdev); 253 } 254 255 static const struct dma_slave_map da850_edma0_map[] = { 256 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) }, 257 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) }, 258 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) }, 259 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) }, 260 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) }, 261 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) }, 262 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) }, 263 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) }, 264 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) }, 265 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) }, 266 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) }, 267 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) }, 268 }; 269 270 static const struct dma_slave_map da850_edma1_map[] = { 271 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) }, 272 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) }, 273 }; 274 275 int __init da850_register_edma(struct edma_rsv_info *rsv[2]) 276 { 277 struct platform_device *edma_pdev; 278 279 if (rsv) { 280 da8xx_edma0_pdata.rsv = rsv[0]; 281 da850_edma1_pdata.rsv = rsv[1]; 282 } 283 284 da8xx_edma0_pdata.slave_map = da850_edma0_map; 285 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map); 286 287 edma_pdev = platform_device_register_full(&da8xx_edma0_device); 288 if (IS_ERR(edma_pdev)) { 289 pr_warn("%s: Failed to register eDMA0\n", __func__); 290 return PTR_ERR(edma_pdev); 291 } 292 293 da850_edma1_pdata.slave_map = da850_edma1_map; 294 da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map); 295 296 edma_pdev = platform_device_register_full(&da850_edma1_device); 297 return PTR_ERR_OR_ZERO(edma_pdev); 298 } 299 300 static struct resource da8xx_i2c_resources0[] = { 301 { 302 .start = DA8XX_I2C0_BASE, 303 .end = DA8XX_I2C0_BASE + SZ_4K - 1, 304 .flags = IORESOURCE_MEM, 305 }, 306 { 307 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0), 308 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0), 309 .flags = IORESOURCE_IRQ, 310 }, 311 }; 312 313 static struct platform_device da8xx_i2c_device0 = { 314 .name = "i2c_davinci", 315 .id = 1, 316 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), 317 .resource = da8xx_i2c_resources0, 318 }; 319 320 static struct resource da8xx_i2c_resources1[] = { 321 { 322 .start = DA8XX_I2C1_BASE, 323 .end = DA8XX_I2C1_BASE + SZ_4K - 1, 324 .flags = IORESOURCE_MEM, 325 }, 326 { 327 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1), 328 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1), 329 .flags = IORESOURCE_IRQ, 330 }, 331 }; 332 333 static struct platform_device da8xx_i2c_device1 = { 334 .name = "i2c_davinci", 335 .id = 2, 336 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), 337 .resource = da8xx_i2c_resources1, 338 }; 339 340 int __init da8xx_register_i2c(int instance, 341 struct davinci_i2c_platform_data *pdata) 342 { 343 struct platform_device *pdev; 344 345 if (instance == 0) 346 pdev = &da8xx_i2c_device0; 347 else if (instance == 1) 348 pdev = &da8xx_i2c_device1; 349 else 350 return -EINVAL; 351 352 pdev->dev.platform_data = pdata; 353 return platform_device_register(pdev); 354 } 355 356 static struct resource da8xx_watchdog_resources[] = { 357 { 358 .start = DA8XX_WDOG_BASE, 359 .end = DA8XX_WDOG_BASE + SZ_4K - 1, 360 .flags = IORESOURCE_MEM, 361 }, 362 }; 363 364 static struct platform_device da8xx_wdt_device = { 365 .name = "davinci-wdt", 366 .id = -1, 367 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), 368 .resource = da8xx_watchdog_resources, 369 }; 370 371 int __init da8xx_register_watchdog(void) 372 { 373 return platform_device_register(&da8xx_wdt_device); 374 } 375 376 static struct resource da8xx_emac_resources[] = { 377 { 378 .start = DA8XX_EMAC_CPPI_PORT_BASE, 379 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1, 380 .flags = IORESOURCE_MEM, 381 }, 382 { 383 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE), 384 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE), 385 .flags = IORESOURCE_IRQ, 386 }, 387 { 388 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE), 389 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE), 390 .flags = IORESOURCE_IRQ, 391 }, 392 { 393 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE), 394 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE), 395 .flags = IORESOURCE_IRQ, 396 }, 397 { 398 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE), 399 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE), 400 .flags = IORESOURCE_IRQ, 401 }, 402 }; 403 404 struct emac_platform_data da8xx_emac_pdata = { 405 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, 406 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, 407 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, 408 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, 409 .version = EMAC_VERSION_2, 410 }; 411 412 static struct platform_device da8xx_emac_device = { 413 .name = "davinci_emac", 414 .id = 1, 415 .dev = { 416 .platform_data = &da8xx_emac_pdata, 417 }, 418 .num_resources = ARRAY_SIZE(da8xx_emac_resources), 419 .resource = da8xx_emac_resources, 420 }; 421 422 static struct resource da8xx_mdio_resources[] = { 423 { 424 .start = DA8XX_EMAC_MDIO_BASE, 425 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1, 426 .flags = IORESOURCE_MEM, 427 }, 428 }; 429 430 static struct platform_device da8xx_mdio_device = { 431 .name = "davinci_mdio", 432 .id = 0, 433 .num_resources = ARRAY_SIZE(da8xx_mdio_resources), 434 .resource = da8xx_mdio_resources, 435 }; 436 437 int __init da8xx_register_emac(void) 438 { 439 int ret; 440 441 ret = platform_device_register(&da8xx_mdio_device); 442 if (ret < 0) 443 return ret; 444 445 return platform_device_register(&da8xx_emac_device); 446 } 447 448 static struct resource da830_mcasp1_resources[] = { 449 { 450 .name = "mpu", 451 .start = DAVINCI_DA830_MCASP1_REG_BASE, 452 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, 453 .flags = IORESOURCE_MEM, 454 }, 455 /* TX event */ 456 { 457 .name = "tx", 458 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, 459 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, 460 .flags = IORESOURCE_DMA, 461 }, 462 /* RX event */ 463 { 464 .name = "rx", 465 .start = DAVINCI_DA830_DMA_MCASP1_AREVT, 466 .end = DAVINCI_DA830_DMA_MCASP1_AREVT, 467 .flags = IORESOURCE_DMA, 468 }, 469 { 470 .name = "common", 471 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT), 472 .flags = IORESOURCE_IRQ, 473 }, 474 }; 475 476 static struct platform_device da830_mcasp1_device = { 477 .name = "davinci-mcasp", 478 .id = 1, 479 .num_resources = ARRAY_SIZE(da830_mcasp1_resources), 480 .resource = da830_mcasp1_resources, 481 }; 482 483 static struct resource da830_mcasp2_resources[] = { 484 { 485 .name = "mpu", 486 .start = DAVINCI_DA830_MCASP2_REG_BASE, 487 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1, 488 .flags = IORESOURCE_MEM, 489 }, 490 /* TX event */ 491 { 492 .name = "tx", 493 .start = DAVINCI_DA830_DMA_MCASP2_AXEVT, 494 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT, 495 .flags = IORESOURCE_DMA, 496 }, 497 /* RX event */ 498 { 499 .name = "rx", 500 .start = DAVINCI_DA830_DMA_MCASP2_AREVT, 501 .end = DAVINCI_DA830_DMA_MCASP2_AREVT, 502 .flags = IORESOURCE_DMA, 503 }, 504 { 505 .name = "common", 506 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT), 507 .flags = IORESOURCE_IRQ, 508 }, 509 }; 510 511 static struct platform_device da830_mcasp2_device = { 512 .name = "davinci-mcasp", 513 .id = 2, 514 .num_resources = ARRAY_SIZE(da830_mcasp2_resources), 515 .resource = da830_mcasp2_resources, 516 }; 517 518 static struct resource da850_mcasp_resources[] = { 519 { 520 .name = "mpu", 521 .start = DAVINCI_DA8XX_MCASP0_REG_BASE, 522 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, 523 .flags = IORESOURCE_MEM, 524 }, 525 /* TX event */ 526 { 527 .name = "tx", 528 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 529 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 530 .flags = IORESOURCE_DMA, 531 }, 532 /* RX event */ 533 { 534 .name = "rx", 535 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 536 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 537 .flags = IORESOURCE_DMA, 538 }, 539 { 540 .name = "common", 541 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT), 542 .flags = IORESOURCE_IRQ, 543 }, 544 }; 545 546 static struct platform_device da850_mcasp_device = { 547 .name = "davinci-mcasp", 548 .id = 0, 549 .num_resources = ARRAY_SIZE(da850_mcasp_resources), 550 .resource = da850_mcasp_resources, 551 }; 552 553 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) 554 { 555 struct platform_device *pdev; 556 557 switch (id) { 558 case 0: 559 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */ 560 pdev = &da850_mcasp_device; 561 break; 562 case 1: 563 /* Valid for DA830/OMAP-L137 only */ 564 if (!cpu_is_davinci_da830()) 565 return; 566 pdev = &da830_mcasp1_device; 567 break; 568 case 2: 569 /* Valid for DA830/OMAP-L137 only */ 570 if (!cpu_is_davinci_da830()) 571 return; 572 pdev = &da830_mcasp2_device; 573 break; 574 default: 575 return; 576 } 577 578 pdev->dev.platform_data = pdata; 579 platform_device_register(pdev); 580 } 581 582 static struct resource da8xx_pruss_resources[] = { 583 { 584 .start = DA8XX_PRUSS_MEM_BASE, 585 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF, 586 .flags = IORESOURCE_MEM, 587 }, 588 { 589 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0), 590 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0), 591 .flags = IORESOURCE_IRQ, 592 }, 593 { 594 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1), 595 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1), 596 .flags = IORESOURCE_IRQ, 597 }, 598 { 599 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2), 600 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2), 601 .flags = IORESOURCE_IRQ, 602 }, 603 { 604 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3), 605 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3), 606 .flags = IORESOURCE_IRQ, 607 }, 608 { 609 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4), 610 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4), 611 .flags = IORESOURCE_IRQ, 612 }, 613 { 614 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5), 615 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5), 616 .flags = IORESOURCE_IRQ, 617 }, 618 { 619 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6), 620 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6), 621 .flags = IORESOURCE_IRQ, 622 }, 623 { 624 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7), 625 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7), 626 .flags = IORESOURCE_IRQ, 627 }, 628 }; 629 630 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = { 631 .pintc_base = 0x4000, 632 }; 633 634 static struct platform_device da8xx_uio_pruss_dev = { 635 .name = "pruss_uio", 636 .id = -1, 637 .num_resources = ARRAY_SIZE(da8xx_pruss_resources), 638 .resource = da8xx_pruss_resources, 639 .dev = { 640 .coherent_dma_mask = DMA_BIT_MASK(32), 641 .platform_data = &da8xx_uio_pruss_pdata, 642 } 643 }; 644 645 int __init da8xx_register_uio_pruss(void) 646 { 647 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool(); 648 return platform_device_register(&da8xx_uio_pruss_dev); 649 } 650 651 static struct lcd_ctrl_config lcd_cfg = { 652 .panel_shade = COLOR_ACTIVE, 653 .bpp = 16, 654 }; 655 656 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = { 657 .manu_name = "sharp", 658 .controller_data = &lcd_cfg, 659 .type = "Sharp_LCD035Q3DG01", 660 }; 661 662 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = { 663 .manu_name = "sharp", 664 .controller_data = &lcd_cfg, 665 .type = "Sharp_LK043T1DG01", 666 }; 667 668 static struct resource da8xx_lcdc_resources[] = { 669 [0] = { /* registers */ 670 .start = DA8XX_LCD_CNTRL_BASE, 671 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, 672 .flags = IORESOURCE_MEM, 673 }, 674 [1] = { /* interrupt */ 675 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT), 676 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT), 677 .flags = IORESOURCE_IRQ, 678 }, 679 }; 680 681 static struct platform_device da8xx_lcdc_device = { 682 .name = "da8xx_lcdc", 683 .id = 0, 684 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), 685 .resource = da8xx_lcdc_resources, 686 }; 687 688 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) 689 { 690 da8xx_lcdc_device.dev.platform_data = pdata; 691 return platform_device_register(&da8xx_lcdc_device); 692 } 693 694 static struct resource da8xx_gpio_resources[] = { 695 { /* registers */ 696 .start = DA8XX_GPIO_BASE, 697 .end = DA8XX_GPIO_BASE + SZ_4K - 1, 698 .flags = IORESOURCE_MEM, 699 }, 700 { /* interrupt */ 701 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0), 702 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0), 703 .flags = IORESOURCE_IRQ, 704 }, 705 { 706 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1), 707 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1), 708 .flags = IORESOURCE_IRQ, 709 }, 710 { 711 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2), 712 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2), 713 .flags = IORESOURCE_IRQ, 714 }, 715 { 716 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3), 717 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3), 718 .flags = IORESOURCE_IRQ, 719 }, 720 { 721 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4), 722 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4), 723 .flags = IORESOURCE_IRQ, 724 }, 725 { 726 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5), 727 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5), 728 .flags = IORESOURCE_IRQ, 729 }, 730 { 731 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6), 732 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6), 733 .flags = IORESOURCE_IRQ, 734 }, 735 { 736 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7), 737 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7), 738 .flags = IORESOURCE_IRQ, 739 }, 740 { 741 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8), 742 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8), 743 .flags = IORESOURCE_IRQ, 744 }, 745 }; 746 747 static struct platform_device da8xx_gpio_device = { 748 .name = "davinci_gpio", 749 .id = -1, 750 .num_resources = ARRAY_SIZE(da8xx_gpio_resources), 751 .resource = da8xx_gpio_resources, 752 }; 753 754 int __init da8xx_register_gpio(void *pdata) 755 { 756 da8xx_gpio_device.dev.platform_data = pdata; 757 return platform_device_register(&da8xx_gpio_device); 758 } 759 760 static struct resource da8xx_mmcsd0_resources[] = { 761 { /* registers */ 762 .start = DA8XX_MMCSD0_BASE, 763 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, 764 .flags = IORESOURCE_MEM, 765 }, 766 { /* interrupt */ 767 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0), 768 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0), 769 .flags = IORESOURCE_IRQ, 770 }, 771 }; 772 773 static struct platform_device da8xx_mmcsd0_device = { 774 .name = "da830-mmc", 775 .id = 0, 776 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), 777 .resource = da8xx_mmcsd0_resources, 778 }; 779 780 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) 781 { 782 da8xx_mmcsd0_device.dev.platform_data = config; 783 return platform_device_register(&da8xx_mmcsd0_device); 784 } 785 786 #ifdef CONFIG_ARCH_DAVINCI_DA850 787 static struct resource da850_mmcsd1_resources[] = { 788 { /* registers */ 789 .start = DA850_MMCSD1_BASE, 790 .end = DA850_MMCSD1_BASE + SZ_4K - 1, 791 .flags = IORESOURCE_MEM, 792 }, 793 { /* interrupt */ 794 .start = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1), 795 .end = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1), 796 .flags = IORESOURCE_IRQ, 797 }, 798 }; 799 800 static struct platform_device da850_mmcsd1_device = { 801 .name = "da830-mmc", 802 .id = 1, 803 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), 804 .resource = da850_mmcsd1_resources, 805 }; 806 807 int __init da850_register_mmcsd1(struct davinci_mmc_config *config) 808 { 809 da850_mmcsd1_device.dev.platform_data = config; 810 return platform_device_register(&da850_mmcsd1_device); 811 } 812 #endif 813 814 static struct resource da8xx_rproc_resources[] = { 815 { /* DSP boot address */ 816 .name = "host1cfg", 817 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG, 818 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3, 819 .flags = IORESOURCE_MEM, 820 }, 821 { /* DSP interrupt registers */ 822 .name = "chipsig", 823 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG, 824 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7, 825 .flags = IORESOURCE_MEM, 826 }, 827 { /* DSP L2 RAM */ 828 .name = "l2sram", 829 .start = DA8XX_DSP_L2_RAM_BASE, 830 .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1, 831 .flags = IORESOURCE_MEM, 832 }, 833 { /* DSP L1P RAM */ 834 .name = "l1pram", 835 .start = DA8XX_DSP_L1P_RAM_BASE, 836 .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1, 837 .flags = IORESOURCE_MEM, 838 }, 839 { /* DSP L1D RAM */ 840 .name = "l1dram", 841 .start = DA8XX_DSP_L1D_RAM_BASE, 842 .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1, 843 .flags = IORESOURCE_MEM, 844 }, 845 { /* dsp irq */ 846 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0), 847 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0), 848 .flags = IORESOURCE_IRQ, 849 }, 850 }; 851 852 static struct platform_device da8xx_dsp = { 853 .name = "davinci-rproc", 854 .dev = { 855 .coherent_dma_mask = DMA_BIT_MASK(32), 856 }, 857 .num_resources = ARRAY_SIZE(da8xx_rproc_resources), 858 .resource = da8xx_rproc_resources, 859 }; 860 861 static bool rproc_mem_inited __initdata; 862 863 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC) 864 865 static phys_addr_t rproc_base __initdata; 866 static unsigned long rproc_size __initdata; 867 868 static int __init early_rproc_mem(char *p) 869 { 870 char *endp; 871 872 if (p == NULL) 873 return 0; 874 875 rproc_size = memparse(p, &endp); 876 if (*endp == '@') 877 rproc_base = memparse(endp + 1, NULL); 878 879 return 0; 880 } 881 early_param("rproc_mem", early_rproc_mem); 882 883 void __init da8xx_rproc_reserve_cma(void) 884 { 885 int ret; 886 887 if (!rproc_base || !rproc_size) { 888 pr_err("%s: 'rproc_mem=nn@address' badly specified\n" 889 " 'nn' and 'address' must both be non-zero\n", 890 __func__); 891 892 return; 893 } 894 895 pr_info("%s: reserving 0x%lx @ 0x%lx...\n", 896 __func__, rproc_size, (unsigned long)rproc_base); 897 898 ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0); 899 if (ret) 900 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret); 901 else 902 rproc_mem_inited = true; 903 } 904 905 #else 906 907 void __init da8xx_rproc_reserve_cma(void) 908 { 909 } 910 911 #endif 912 913 int __init da8xx_register_rproc(void) 914 { 915 int ret; 916 917 if (!rproc_mem_inited) { 918 pr_warn("%s: memory not reserved for DSP, not registering DSP device\n", 919 __func__); 920 return -ENOMEM; 921 } 922 923 ret = platform_device_register(&da8xx_dsp); 924 if (ret) 925 pr_err("%s: can't register DSP device: %d\n", __func__, ret); 926 927 return ret; 928 }; 929 930 static struct resource da8xx_rtc_resources[] = { 931 { 932 .start = DA8XX_RTC_BASE, 933 .end = DA8XX_RTC_BASE + SZ_4K - 1, 934 .flags = IORESOURCE_MEM, 935 }, 936 { /* timer irq */ 937 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), 938 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), 939 .flags = IORESOURCE_IRQ, 940 }, 941 { /* alarm irq */ 942 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), 943 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), 944 .flags = IORESOURCE_IRQ, 945 }, 946 }; 947 948 static struct platform_device da8xx_rtc_device = { 949 .name = "da830-rtc", 950 .id = -1, 951 .num_resources = ARRAY_SIZE(da8xx_rtc_resources), 952 .resource = da8xx_rtc_resources, 953 }; 954 955 int da8xx_register_rtc(void) 956 { 957 return platform_device_register(&da8xx_rtc_device); 958 } 959 960 static void __iomem *da8xx_ddr2_ctlr_base; 961 void __iomem * __init da8xx_get_mem_ctlr(void) 962 { 963 if (da8xx_ddr2_ctlr_base) 964 return da8xx_ddr2_ctlr_base; 965 966 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K); 967 if (!da8xx_ddr2_ctlr_base) 968 pr_warn("%s: Unable to map DDR2 controller", __func__); 969 970 return da8xx_ddr2_ctlr_base; 971 } 972 973 static struct resource da8xx_cpuidle_resources[] = { 974 { 975 .start = DA8XX_DDR2_CTL_BASE, 976 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1, 977 .flags = IORESOURCE_MEM, 978 }, 979 }; 980 981 /* DA8XX devices support DDR2 power down */ 982 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = { 983 .ddr2_pdown = 1, 984 }; 985 986 987 static struct platform_device da8xx_cpuidle_device = { 988 .name = "cpuidle-davinci", 989 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources), 990 .resource = da8xx_cpuidle_resources, 991 .dev = { 992 .platform_data = &da8xx_cpuidle_pdata, 993 }, 994 }; 995 996 int __init da8xx_register_cpuidle(void) 997 { 998 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr(); 999 1000 return platform_device_register(&da8xx_cpuidle_device); 1001 } 1002 1003 static struct resource da8xx_spi0_resources[] = { 1004 [0] = { 1005 .start = DA8XX_SPI0_BASE, 1006 .end = DA8XX_SPI0_BASE + SZ_4K - 1, 1007 .flags = IORESOURCE_MEM, 1008 }, 1009 [1] = { 1010 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0), 1011 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0), 1012 .flags = IORESOURCE_IRQ, 1013 }, 1014 }; 1015 1016 static struct resource da8xx_spi1_resources[] = { 1017 [0] = { 1018 .start = DA830_SPI1_BASE, 1019 .end = DA830_SPI1_BASE + SZ_4K - 1, 1020 .flags = IORESOURCE_MEM, 1021 }, 1022 [1] = { 1023 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1), 1024 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1), 1025 .flags = IORESOURCE_IRQ, 1026 }, 1027 }; 1028 1029 static struct davinci_spi_platform_data da8xx_spi_pdata[] = { 1030 [0] = { 1031 .version = SPI_VERSION_2, 1032 .intr_line = 1, 1033 .dma_event_q = EVENTQ_0, 1034 .prescaler_limit = 2, 1035 }, 1036 [1] = { 1037 .version = SPI_VERSION_2, 1038 .intr_line = 1, 1039 .dma_event_q = EVENTQ_0, 1040 .prescaler_limit = 2, 1041 }, 1042 }; 1043 1044 static struct platform_device da8xx_spi_device[] = { 1045 [0] = { 1046 .name = "spi_davinci", 1047 .id = 0, 1048 .num_resources = ARRAY_SIZE(da8xx_spi0_resources), 1049 .resource = da8xx_spi0_resources, 1050 .dev = { 1051 .platform_data = &da8xx_spi_pdata[0], 1052 }, 1053 }, 1054 [1] = { 1055 .name = "spi_davinci", 1056 .id = 1, 1057 .num_resources = ARRAY_SIZE(da8xx_spi1_resources), 1058 .resource = da8xx_spi1_resources, 1059 .dev = { 1060 .platform_data = &da8xx_spi_pdata[1], 1061 }, 1062 }, 1063 }; 1064 1065 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect) 1066 { 1067 if (instance < 0 || instance > 1) 1068 return -EINVAL; 1069 1070 da8xx_spi_pdata[instance].num_chipselect = num_chipselect; 1071 1072 if (instance == 1 && cpu_is_davinci_da850()) { 1073 da8xx_spi1_resources[0].start = DA850_SPI1_BASE; 1074 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; 1075 } 1076 1077 return platform_device_register(&da8xx_spi_device[instance]); 1078 } 1079 1080 #ifdef CONFIG_ARCH_DAVINCI_DA850 1081 int __init da850_register_sata_refclk(int rate) 1082 { 1083 struct clk *clk; 1084 1085 clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate); 1086 if (IS_ERR(clk)) 1087 return PTR_ERR(clk); 1088 1089 return clk_register_clkdev(clk, "refclk", "ahci_da850"); 1090 } 1091 1092 static struct resource da850_sata_resources[] = { 1093 { 1094 .start = DA850_SATA_BASE, 1095 .end = DA850_SATA_BASE + 0x1fff, 1096 .flags = IORESOURCE_MEM, 1097 }, 1098 { 1099 .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG, 1100 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3, 1101 .flags = IORESOURCE_MEM, 1102 }, 1103 { 1104 .start = DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT), 1105 .flags = IORESOURCE_IRQ, 1106 }, 1107 }; 1108 1109 static u64 da850_sata_dmamask = DMA_BIT_MASK(32); 1110 1111 static struct platform_device da850_sata_device = { 1112 .name = "ahci_da850", 1113 .id = -1, 1114 .dev = { 1115 .dma_mask = &da850_sata_dmamask, 1116 .coherent_dma_mask = DMA_BIT_MASK(32), 1117 }, 1118 .num_resources = ARRAY_SIZE(da850_sata_resources), 1119 .resource = da850_sata_resources, 1120 }; 1121 1122 int __init da850_register_sata(unsigned long refclkpn) 1123 { 1124 int ret; 1125 1126 ret = da850_register_sata_refclk(refclkpn); 1127 if (ret) 1128 return ret; 1129 1130 return platform_device_register(&da850_sata_device); 1131 } 1132 #endif 1133 1134 static struct regmap *da8xx_cfgchip; 1135 1136 static const struct regmap_config da8xx_cfgchip_config __initconst = { 1137 .name = "cfgchip", 1138 .reg_bits = 32, 1139 .val_bits = 32, 1140 .reg_stride = 4, 1141 .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG, 1142 }; 1143 1144 /** 1145 * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap 1146 * 1147 * This is for use on non-DT boards only. For DT boards, use 1148 * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip") 1149 * 1150 * Returns: Pointer to the CFGCHIP regmap or negative error code. 1151 */ 1152 struct regmap * __init da8xx_get_cfgchip(void) 1153 { 1154 if (IS_ERR_OR_NULL(da8xx_cfgchip)) 1155 da8xx_cfgchip = regmap_init_mmio(NULL, 1156 DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG), 1157 &da8xx_cfgchip_config); 1158 1159 return da8xx_cfgchip; 1160 } 1161