1 /*
2  * DA8XX/OMAP L1XX platform device data
3  *
4  * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5  * Derived from code that was:
6  *	Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  */
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-contiguous.h>
16 #include <linux/serial_8250.h>
17 #include <linux/ahci_platform.h>
18 #include <linux/clk.h>
19 #include <linux/reboot.h>
20 
21 #include <mach/cputype.h>
22 #include <mach/common.h>
23 #include <mach/time.h>
24 #include <mach/da8xx.h>
25 #include <mach/cpuidle.h>
26 #include <mach/sram.h>
27 
28 #include "clock.h"
29 #include "asp.h"
30 
31 #define DA8XX_TPCC_BASE			0x01c00000
32 #define DA8XX_TPTC0_BASE		0x01c08000
33 #define DA8XX_TPTC1_BASE		0x01c08400
34 #define DA8XX_WDOG_BASE			0x01c21000 /* DA8XX_TIMER64P1_BASE */
35 #define DA8XX_I2C0_BASE			0x01c22000
36 #define DA8XX_RTC_BASE			0x01c23000
37 #define DA8XX_PRUSS_MEM_BASE		0x01c30000
38 #define DA8XX_MMCSD0_BASE		0x01c40000
39 #define DA8XX_SPI0_BASE			0x01c41000
40 #define DA830_SPI1_BASE			0x01e12000
41 #define DA8XX_LCD_CNTRL_BASE		0x01e13000
42 #define DA850_SATA_BASE			0x01e18000
43 #define DA850_MMCSD1_BASE		0x01e1b000
44 #define DA8XX_EMAC_CPPI_PORT_BASE	0x01e20000
45 #define DA8XX_EMAC_CPGMACSS_BASE	0x01e22000
46 #define DA8XX_EMAC_CPGMAC_BASE		0x01e23000
47 #define DA8XX_EMAC_MDIO_BASE		0x01e24000
48 #define DA8XX_I2C1_BASE			0x01e28000
49 #define DA850_TPCC1_BASE		0x01e30000
50 #define DA850_TPTC2_BASE		0x01e38000
51 #define DA850_SPI1_BASE			0x01f0e000
52 #define DA8XX_DDR2_CTL_BASE		0xb0000000
53 
54 #define DA8XX_EMAC_CTRL_REG_OFFSET	0x3000
55 #define DA8XX_EMAC_MOD_REG_OFFSET	0x2000
56 #define DA8XX_EMAC_RAM_OFFSET		0x0000
57 #define DA8XX_EMAC_CTRL_RAM_SIZE	SZ_8K
58 
59 #define DA8XX_DMA_SPI0_RX	EDMA_CTLR_CHAN(0, 14)
60 #define DA8XX_DMA_SPI0_TX	EDMA_CTLR_CHAN(0, 15)
61 #define DA8XX_DMA_MMCSD0_RX	EDMA_CTLR_CHAN(0, 16)
62 #define DA8XX_DMA_MMCSD0_TX	EDMA_CTLR_CHAN(0, 17)
63 #define DA8XX_DMA_SPI1_RX	EDMA_CTLR_CHAN(0, 18)
64 #define DA8XX_DMA_SPI1_TX	EDMA_CTLR_CHAN(0, 19)
65 #define DA850_DMA_MMCSD1_RX	EDMA_CTLR_CHAN(1, 28)
66 #define DA850_DMA_MMCSD1_TX	EDMA_CTLR_CHAN(1, 29)
67 
68 void __iomem *da8xx_syscfg0_base;
69 void __iomem *da8xx_syscfg1_base;
70 
71 static struct plat_serial8250_port da8xx_serial0_pdata[] = {
72 	{
73 		.mapbase	= DA8XX_UART0_BASE,
74 		.irq		= IRQ_DA8XX_UARTINT0,
75 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
76 					UPF_IOREMAP,
77 		.iotype		= UPIO_MEM,
78 		.regshift	= 2,
79 	},
80 	{
81 		.flags	= 0,
82 	}
83 };
84 static struct plat_serial8250_port da8xx_serial1_pdata[] = {
85 	{
86 		.mapbase	= DA8XX_UART1_BASE,
87 		.irq		= IRQ_DA8XX_UARTINT1,
88 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
89 					UPF_IOREMAP,
90 		.iotype		= UPIO_MEM,
91 		.regshift	= 2,
92 	},
93 	{
94 		.flags	= 0,
95 	}
96 };
97 static struct plat_serial8250_port da8xx_serial2_pdata[] = {
98 	{
99 		.mapbase	= DA8XX_UART2_BASE,
100 		.irq		= IRQ_DA8XX_UARTINT2,
101 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
102 					UPF_IOREMAP,
103 		.iotype		= UPIO_MEM,
104 		.regshift	= 2,
105 	},
106 	{
107 		.flags	= 0,
108 	}
109 };
110 
111 struct platform_device da8xx_serial_device[] = {
112 	{
113 		.name	= "serial8250",
114 		.id	= PLAT8250_DEV_PLATFORM,
115 		.dev	= {
116 			.platform_data	= da8xx_serial0_pdata,
117 		}
118 	},
119 	{
120 		.name	= "serial8250",
121 		.id	= PLAT8250_DEV_PLATFORM1,
122 		.dev	= {
123 			.platform_data	= da8xx_serial1_pdata,
124 		}
125 	},
126 	{
127 		.name	= "serial8250",
128 		.id	= PLAT8250_DEV_PLATFORM2,
129 		.dev	= {
130 			.platform_data	= da8xx_serial2_pdata,
131 		}
132 	},
133 	{
134 	}
135 };
136 
137 static s8 da8xx_queue_tc_mapping[][2] = {
138 	/* {event queue no, TC no} */
139 	{0, 0},
140 	{1, 1},
141 	{-1, -1}
142 };
143 
144 static s8 da8xx_queue_priority_mapping[][2] = {
145 	/* {event queue no, Priority} */
146 	{0, 3},
147 	{1, 7},
148 	{-1, -1}
149 };
150 
151 static s8 da850_queue_tc_mapping[][2] = {
152 	/* {event queue no, TC no} */
153 	{0, 0},
154 	{-1, -1}
155 };
156 
157 static s8 da850_queue_priority_mapping[][2] = {
158 	/* {event queue no, Priority} */
159 	{0, 3},
160 	{-1, -1}
161 };
162 
163 static struct edma_soc_info da830_edma_cc0_info = {
164 	.n_channel		= 32,
165 	.n_region		= 4,
166 	.n_slot			= 128,
167 	.n_tc			= 2,
168 	.n_cc			= 1,
169 	.queue_tc_mapping	= da8xx_queue_tc_mapping,
170 	.queue_priority_mapping	= da8xx_queue_priority_mapping,
171 	.default_queue		= EVENTQ_1,
172 };
173 
174 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
175 	&da830_edma_cc0_info,
176 };
177 
178 static struct edma_soc_info da850_edma_cc_info[] = {
179 	{
180 		.n_channel		= 32,
181 		.n_region		= 4,
182 		.n_slot			= 128,
183 		.n_tc			= 2,
184 		.n_cc			= 1,
185 		.queue_tc_mapping	= da8xx_queue_tc_mapping,
186 		.queue_priority_mapping	= da8xx_queue_priority_mapping,
187 		.default_queue		= EVENTQ_1,
188 	},
189 	{
190 		.n_channel		= 32,
191 		.n_region		= 4,
192 		.n_slot			= 128,
193 		.n_tc			= 1,
194 		.n_cc			= 1,
195 		.queue_tc_mapping	= da850_queue_tc_mapping,
196 		.queue_priority_mapping	= da850_queue_priority_mapping,
197 		.default_queue		= EVENTQ_0,
198 	},
199 };
200 
201 static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
202 	&da850_edma_cc_info[0],
203 	&da850_edma_cc_info[1],
204 };
205 
206 static struct resource da830_edma_resources[] = {
207 	{
208 		.name	= "edma_cc0",
209 		.start	= DA8XX_TPCC_BASE,
210 		.end	= DA8XX_TPCC_BASE + SZ_32K - 1,
211 		.flags	= IORESOURCE_MEM,
212 	},
213 	{
214 		.name	= "edma_tc0",
215 		.start	= DA8XX_TPTC0_BASE,
216 		.end	= DA8XX_TPTC0_BASE + SZ_1K - 1,
217 		.flags	= IORESOURCE_MEM,
218 	},
219 	{
220 		.name	= "edma_tc1",
221 		.start	= DA8XX_TPTC1_BASE,
222 		.end	= DA8XX_TPTC1_BASE + SZ_1K - 1,
223 		.flags	= IORESOURCE_MEM,
224 	},
225 	{
226 		.name	= "edma0",
227 		.start	= IRQ_DA8XX_CCINT0,
228 		.flags	= IORESOURCE_IRQ,
229 	},
230 	{
231 		.name	= "edma0_err",
232 		.start	= IRQ_DA8XX_CCERRINT,
233 		.flags	= IORESOURCE_IRQ,
234 	},
235 };
236 
237 static struct resource da850_edma_resources[] = {
238 	{
239 		.name	= "edma_cc0",
240 		.start	= DA8XX_TPCC_BASE,
241 		.end	= DA8XX_TPCC_BASE + SZ_32K - 1,
242 		.flags	= IORESOURCE_MEM,
243 	},
244 	{
245 		.name	= "edma_tc0",
246 		.start	= DA8XX_TPTC0_BASE,
247 		.end	= DA8XX_TPTC0_BASE + SZ_1K - 1,
248 		.flags	= IORESOURCE_MEM,
249 	},
250 	{
251 		.name	= "edma_tc1",
252 		.start	= DA8XX_TPTC1_BASE,
253 		.end	= DA8XX_TPTC1_BASE + SZ_1K - 1,
254 		.flags	= IORESOURCE_MEM,
255 	},
256 	{
257 		.name	= "edma_cc1",
258 		.start	= DA850_TPCC1_BASE,
259 		.end	= DA850_TPCC1_BASE + SZ_32K - 1,
260 		.flags	= IORESOURCE_MEM,
261 	},
262 	{
263 		.name	= "edma_tc2",
264 		.start	= DA850_TPTC2_BASE,
265 		.end	= DA850_TPTC2_BASE + SZ_1K - 1,
266 		.flags	= IORESOURCE_MEM,
267 	},
268 	{
269 		.name	= "edma0",
270 		.start	= IRQ_DA8XX_CCINT0,
271 		.flags	= IORESOURCE_IRQ,
272 	},
273 	{
274 		.name	= "edma0_err",
275 		.start	= IRQ_DA8XX_CCERRINT,
276 		.flags	= IORESOURCE_IRQ,
277 	},
278 	{
279 		.name	= "edma1",
280 		.start	= IRQ_DA850_CCINT1,
281 		.flags	= IORESOURCE_IRQ,
282 	},
283 	{
284 		.name	= "edma1_err",
285 		.start	= IRQ_DA850_CCERRINT1,
286 		.flags	= IORESOURCE_IRQ,
287 	},
288 };
289 
290 static struct platform_device da830_edma_device = {
291 	.name		= "edma",
292 	.id		= -1,
293 	.dev = {
294 		.platform_data = da830_edma_info,
295 	},
296 	.num_resources	= ARRAY_SIZE(da830_edma_resources),
297 	.resource	= da830_edma_resources,
298 };
299 
300 static struct platform_device da850_edma_device = {
301 	.name		= "edma",
302 	.id		= -1,
303 	.dev = {
304 		.platform_data = da850_edma_info,
305 	},
306 	.num_resources	= ARRAY_SIZE(da850_edma_resources),
307 	.resource	= da850_edma_resources,
308 };
309 
310 int __init da830_register_edma(struct edma_rsv_info *rsv)
311 {
312 	da830_edma_cc0_info.rsv = rsv;
313 
314 	return platform_device_register(&da830_edma_device);
315 }
316 
317 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
318 {
319 	if (rsv) {
320 		da850_edma_cc_info[0].rsv = rsv[0];
321 		da850_edma_cc_info[1].rsv = rsv[1];
322 	}
323 
324 	return platform_device_register(&da850_edma_device);
325 }
326 
327 static struct resource da8xx_i2c_resources0[] = {
328 	{
329 		.start	= DA8XX_I2C0_BASE,
330 		.end	= DA8XX_I2C0_BASE + SZ_4K - 1,
331 		.flags	= IORESOURCE_MEM,
332 	},
333 	{
334 		.start	= IRQ_DA8XX_I2CINT0,
335 		.end	= IRQ_DA8XX_I2CINT0,
336 		.flags	= IORESOURCE_IRQ,
337 	},
338 };
339 
340 static struct platform_device da8xx_i2c_device0 = {
341 	.name		= "i2c_davinci",
342 	.id		= 1,
343 	.num_resources	= ARRAY_SIZE(da8xx_i2c_resources0),
344 	.resource	= da8xx_i2c_resources0,
345 };
346 
347 static struct resource da8xx_i2c_resources1[] = {
348 	{
349 		.start	= DA8XX_I2C1_BASE,
350 		.end	= DA8XX_I2C1_BASE + SZ_4K - 1,
351 		.flags	= IORESOURCE_MEM,
352 	},
353 	{
354 		.start	= IRQ_DA8XX_I2CINT1,
355 		.end	= IRQ_DA8XX_I2CINT1,
356 		.flags	= IORESOURCE_IRQ,
357 	},
358 };
359 
360 static struct platform_device da8xx_i2c_device1 = {
361 	.name		= "i2c_davinci",
362 	.id		= 2,
363 	.num_resources	= ARRAY_SIZE(da8xx_i2c_resources1),
364 	.resource	= da8xx_i2c_resources1,
365 };
366 
367 int __init da8xx_register_i2c(int instance,
368 		struct davinci_i2c_platform_data *pdata)
369 {
370 	struct platform_device *pdev;
371 
372 	if (instance == 0)
373 		pdev = &da8xx_i2c_device0;
374 	else if (instance == 1)
375 		pdev = &da8xx_i2c_device1;
376 	else
377 		return -EINVAL;
378 
379 	pdev->dev.platform_data = pdata;
380 	return platform_device_register(pdev);
381 }
382 
383 static struct resource da8xx_watchdog_resources[] = {
384 	{
385 		.start	= DA8XX_WDOG_BASE,
386 		.end	= DA8XX_WDOG_BASE + SZ_4K - 1,
387 		.flags	= IORESOURCE_MEM,
388 	},
389 };
390 
391 static struct platform_device da8xx_wdt_device = {
392 	.name		= "watchdog",
393 	.id		= -1,
394 	.num_resources	= ARRAY_SIZE(da8xx_watchdog_resources),
395 	.resource	= da8xx_watchdog_resources,
396 };
397 
398 void da8xx_restart(enum reboot_mode mode, const char *cmd)
399 {
400 	struct device *dev;
401 
402 	dev = bus_find_device_by_name(&platform_bus_type, NULL, "watchdog");
403 	if (!dev) {
404 		pr_err("%s: failed to find watchdog device\n", __func__);
405 		return;
406 	}
407 
408 	davinci_watchdog_reset(to_platform_device(dev));
409 }
410 
411 int __init da8xx_register_watchdog(void)
412 {
413 	return platform_device_register(&da8xx_wdt_device);
414 }
415 
416 static struct resource da8xx_emac_resources[] = {
417 	{
418 		.start	= DA8XX_EMAC_CPPI_PORT_BASE,
419 		.end	= DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
420 		.flags	= IORESOURCE_MEM,
421 	},
422 	{
423 		.start	= IRQ_DA8XX_C0_RX_THRESH_PULSE,
424 		.end	= IRQ_DA8XX_C0_RX_THRESH_PULSE,
425 		.flags	= IORESOURCE_IRQ,
426 	},
427 	{
428 		.start	= IRQ_DA8XX_C0_RX_PULSE,
429 		.end	= IRQ_DA8XX_C0_RX_PULSE,
430 		.flags	= IORESOURCE_IRQ,
431 	},
432 	{
433 		.start	= IRQ_DA8XX_C0_TX_PULSE,
434 		.end	= IRQ_DA8XX_C0_TX_PULSE,
435 		.flags	= IORESOURCE_IRQ,
436 	},
437 	{
438 		.start	= IRQ_DA8XX_C0_MISC_PULSE,
439 		.end	= IRQ_DA8XX_C0_MISC_PULSE,
440 		.flags	= IORESOURCE_IRQ,
441 	},
442 };
443 
444 struct emac_platform_data da8xx_emac_pdata = {
445 	.ctrl_reg_offset	= DA8XX_EMAC_CTRL_REG_OFFSET,
446 	.ctrl_mod_reg_offset	= DA8XX_EMAC_MOD_REG_OFFSET,
447 	.ctrl_ram_offset	= DA8XX_EMAC_RAM_OFFSET,
448 	.ctrl_ram_size		= DA8XX_EMAC_CTRL_RAM_SIZE,
449 	.version		= EMAC_VERSION_2,
450 };
451 
452 static struct platform_device da8xx_emac_device = {
453 	.name		= "davinci_emac",
454 	.id		= 1,
455 	.dev = {
456 		.platform_data	= &da8xx_emac_pdata,
457 	},
458 	.num_resources	= ARRAY_SIZE(da8xx_emac_resources),
459 	.resource	= da8xx_emac_resources,
460 };
461 
462 static struct resource da8xx_mdio_resources[] = {
463 	{
464 		.start	= DA8XX_EMAC_MDIO_BASE,
465 		.end	= DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
466 		.flags	= IORESOURCE_MEM,
467 	},
468 };
469 
470 static struct platform_device da8xx_mdio_device = {
471 	.name		= "davinci_mdio",
472 	.id		= 0,
473 	.num_resources	= ARRAY_SIZE(da8xx_mdio_resources),
474 	.resource	= da8xx_mdio_resources,
475 };
476 
477 int __init da8xx_register_emac(void)
478 {
479 	int ret;
480 
481 	ret = platform_device_register(&da8xx_mdio_device);
482 	if (ret < 0)
483 		return ret;
484 
485 	return platform_device_register(&da8xx_emac_device);
486 }
487 
488 static struct resource da830_mcasp1_resources[] = {
489 	{
490 		.name	= "mpu",
491 		.start	= DAVINCI_DA830_MCASP1_REG_BASE,
492 		.end	= DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
493 		.flags	= IORESOURCE_MEM,
494 	},
495 	/* TX event */
496 	{
497 		.start	= DAVINCI_DA830_DMA_MCASP1_AXEVT,
498 		.end	= DAVINCI_DA830_DMA_MCASP1_AXEVT,
499 		.flags	= IORESOURCE_DMA,
500 	},
501 	/* RX event */
502 	{
503 		.start	= DAVINCI_DA830_DMA_MCASP1_AREVT,
504 		.end	= DAVINCI_DA830_DMA_MCASP1_AREVT,
505 		.flags	= IORESOURCE_DMA,
506 	},
507 };
508 
509 static struct platform_device da830_mcasp1_device = {
510 	.name		= "davinci-mcasp",
511 	.id		= 1,
512 	.num_resources	= ARRAY_SIZE(da830_mcasp1_resources),
513 	.resource	= da830_mcasp1_resources,
514 };
515 
516 static struct resource da850_mcasp_resources[] = {
517 	{
518 		.name	= "mpu",
519 		.start	= DAVINCI_DA8XX_MCASP0_REG_BASE,
520 		.end	= DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
521 		.flags	= IORESOURCE_MEM,
522 	},
523 	/* TX event */
524 	{
525 		.start	= DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
526 		.end	= DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
527 		.flags	= IORESOURCE_DMA,
528 	},
529 	/* RX event */
530 	{
531 		.start	= DAVINCI_DA8XX_DMA_MCASP0_AREVT,
532 		.end	= DAVINCI_DA8XX_DMA_MCASP0_AREVT,
533 		.flags	= IORESOURCE_DMA,
534 	},
535 };
536 
537 static struct platform_device da850_mcasp_device = {
538 	.name		= "davinci-mcasp",
539 	.id		= 0,
540 	.num_resources	= ARRAY_SIZE(da850_mcasp_resources),
541 	.resource	= da850_mcasp_resources,
542 };
543 
544 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
545 {
546 	/* DA830/OMAP-L137 has 3 instances of McASP */
547 	if (cpu_is_davinci_da830() && id == 1) {
548 		da830_mcasp1_device.dev.platform_data = pdata;
549 		platform_device_register(&da830_mcasp1_device);
550 	} else if (cpu_is_davinci_da850()) {
551 		da850_mcasp_device.dev.platform_data = pdata;
552 		platform_device_register(&da850_mcasp_device);
553 	}
554 }
555 
556 static struct resource da8xx_pruss_resources[] = {
557 	{
558 		.start	= DA8XX_PRUSS_MEM_BASE,
559 		.end	= DA8XX_PRUSS_MEM_BASE + 0xFFFF,
560 		.flags	= IORESOURCE_MEM,
561 	},
562 	{
563 		.start	= IRQ_DA8XX_EVTOUT0,
564 		.end	= IRQ_DA8XX_EVTOUT0,
565 		.flags	= IORESOURCE_IRQ,
566 	},
567 	{
568 		.start	= IRQ_DA8XX_EVTOUT1,
569 		.end	= IRQ_DA8XX_EVTOUT1,
570 		.flags	= IORESOURCE_IRQ,
571 	},
572 	{
573 		.start	= IRQ_DA8XX_EVTOUT2,
574 		.end	= IRQ_DA8XX_EVTOUT2,
575 		.flags	= IORESOURCE_IRQ,
576 	},
577 	{
578 		.start	= IRQ_DA8XX_EVTOUT3,
579 		.end	= IRQ_DA8XX_EVTOUT3,
580 		.flags	= IORESOURCE_IRQ,
581 	},
582 	{
583 		.start	= IRQ_DA8XX_EVTOUT4,
584 		.end	= IRQ_DA8XX_EVTOUT4,
585 		.flags	= IORESOURCE_IRQ,
586 	},
587 	{
588 		.start	= IRQ_DA8XX_EVTOUT5,
589 		.end	= IRQ_DA8XX_EVTOUT5,
590 		.flags	= IORESOURCE_IRQ,
591 	},
592 	{
593 		.start	= IRQ_DA8XX_EVTOUT6,
594 		.end	= IRQ_DA8XX_EVTOUT6,
595 		.flags	= IORESOURCE_IRQ,
596 	},
597 	{
598 		.start	= IRQ_DA8XX_EVTOUT7,
599 		.end	= IRQ_DA8XX_EVTOUT7,
600 		.flags	= IORESOURCE_IRQ,
601 	},
602 };
603 
604 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
605 	.pintc_base	= 0x4000,
606 };
607 
608 static struct platform_device da8xx_uio_pruss_dev = {
609 	.name		= "pruss_uio",
610 	.id		= -1,
611 	.num_resources	= ARRAY_SIZE(da8xx_pruss_resources),
612 	.resource	= da8xx_pruss_resources,
613 	.dev		= {
614 		.coherent_dma_mask	= DMA_BIT_MASK(32),
615 		.platform_data		= &da8xx_uio_pruss_pdata,
616 	}
617 };
618 
619 int __init da8xx_register_uio_pruss(void)
620 {
621 	da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
622 	return platform_device_register(&da8xx_uio_pruss_dev);
623 }
624 
625 static struct lcd_ctrl_config lcd_cfg = {
626 	.panel_shade		= COLOR_ACTIVE,
627 	.bpp			= 16,
628 };
629 
630 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
631 	.manu_name		= "sharp",
632 	.controller_data	= &lcd_cfg,
633 	.type			= "Sharp_LCD035Q3DG01",
634 };
635 
636 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
637 	.manu_name		= "sharp",
638 	.controller_data	= &lcd_cfg,
639 	.type			= "Sharp_LK043T1DG01",
640 };
641 
642 static struct resource da8xx_lcdc_resources[] = {
643 	[0] = { /* registers */
644 		.start  = DA8XX_LCD_CNTRL_BASE,
645 		.end    = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
646 		.flags  = IORESOURCE_MEM,
647 	},
648 	[1] = { /* interrupt */
649 		.start  = IRQ_DA8XX_LCDINT,
650 		.end    = IRQ_DA8XX_LCDINT,
651 		.flags  = IORESOURCE_IRQ,
652 	},
653 };
654 
655 static struct platform_device da8xx_lcdc_device = {
656 	.name		= "da8xx_lcdc",
657 	.id		= 0,
658 	.num_resources	= ARRAY_SIZE(da8xx_lcdc_resources),
659 	.resource	= da8xx_lcdc_resources,
660 };
661 
662 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
663 {
664 	da8xx_lcdc_device.dev.platform_data = pdata;
665 	return platform_device_register(&da8xx_lcdc_device);
666 }
667 
668 static struct resource da8xx_gpio_resources[] = {
669 	{ /* registers */
670 		.start	= DA8XX_GPIO_BASE,
671 		.end	= DA8XX_GPIO_BASE + SZ_4K - 1,
672 		.flags	= IORESOURCE_MEM,
673 	},
674 	{ /* interrupt */
675 		.start	= IRQ_DA8XX_GPIO0,
676 		.end	= IRQ_DA8XX_GPIO8,
677 		.flags	= IORESOURCE_IRQ,
678 	},
679 };
680 
681 static struct platform_device da8xx_gpio_device = {
682 	.name		= "davinci_gpio",
683 	.id		= -1,
684 	.num_resources	= ARRAY_SIZE(da8xx_gpio_resources),
685 	.resource	= da8xx_gpio_resources,
686 };
687 
688 int __init da8xx_register_gpio(void *pdata)
689 {
690 	da8xx_gpio_device.dev.platform_data = pdata;
691 	return platform_device_register(&da8xx_gpio_device);
692 }
693 
694 static struct resource da8xx_mmcsd0_resources[] = {
695 	{		/* registers */
696 		.start	= DA8XX_MMCSD0_BASE,
697 		.end	= DA8XX_MMCSD0_BASE + SZ_4K - 1,
698 		.flags	= IORESOURCE_MEM,
699 	},
700 	{		/* interrupt */
701 		.start	= IRQ_DA8XX_MMCSDINT0,
702 		.end	= IRQ_DA8XX_MMCSDINT0,
703 		.flags	= IORESOURCE_IRQ,
704 	},
705 	{		/* DMA RX */
706 		.start	= DA8XX_DMA_MMCSD0_RX,
707 		.end	= DA8XX_DMA_MMCSD0_RX,
708 		.flags	= IORESOURCE_DMA,
709 	},
710 	{		/* DMA TX */
711 		.start	= DA8XX_DMA_MMCSD0_TX,
712 		.end	= DA8XX_DMA_MMCSD0_TX,
713 		.flags	= IORESOURCE_DMA,
714 	},
715 };
716 
717 static struct platform_device da8xx_mmcsd0_device = {
718 	.name		= "da830-mmc",
719 	.id		= 0,
720 	.num_resources	= ARRAY_SIZE(da8xx_mmcsd0_resources),
721 	.resource	= da8xx_mmcsd0_resources,
722 };
723 
724 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
725 {
726 	da8xx_mmcsd0_device.dev.platform_data = config;
727 	return platform_device_register(&da8xx_mmcsd0_device);
728 }
729 
730 #ifdef CONFIG_ARCH_DAVINCI_DA850
731 static struct resource da850_mmcsd1_resources[] = {
732 	{		/* registers */
733 		.start	= DA850_MMCSD1_BASE,
734 		.end	= DA850_MMCSD1_BASE + SZ_4K - 1,
735 		.flags	= IORESOURCE_MEM,
736 	},
737 	{		/* interrupt */
738 		.start	= IRQ_DA850_MMCSDINT0_1,
739 		.end	= IRQ_DA850_MMCSDINT0_1,
740 		.flags	= IORESOURCE_IRQ,
741 	},
742 	{		/* DMA RX */
743 		.start	= DA850_DMA_MMCSD1_RX,
744 		.end	= DA850_DMA_MMCSD1_RX,
745 		.flags	= IORESOURCE_DMA,
746 	},
747 	{		/* DMA TX */
748 		.start	= DA850_DMA_MMCSD1_TX,
749 		.end	= DA850_DMA_MMCSD1_TX,
750 		.flags	= IORESOURCE_DMA,
751 	},
752 };
753 
754 static struct platform_device da850_mmcsd1_device = {
755 	.name		= "da830-mmc",
756 	.id		= 1,
757 	.num_resources	= ARRAY_SIZE(da850_mmcsd1_resources),
758 	.resource	= da850_mmcsd1_resources,
759 };
760 
761 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
762 {
763 	da850_mmcsd1_device.dev.platform_data = config;
764 	return platform_device_register(&da850_mmcsd1_device);
765 }
766 #endif
767 
768 static struct resource da8xx_rproc_resources[] = {
769 	{ /* DSP boot address */
770 		.start		= DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
771 		.end		= DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
772 		.flags		= IORESOURCE_MEM,
773 	},
774 	{ /* DSP interrupt registers */
775 		.start		= DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
776 		.end		= DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
777 		.flags		= IORESOURCE_MEM,
778 	},
779 	{ /* dsp irq */
780 		.start		= IRQ_DA8XX_CHIPINT0,
781 		.end		= IRQ_DA8XX_CHIPINT0,
782 		.flags		= IORESOURCE_IRQ,
783 	},
784 };
785 
786 static struct platform_device da8xx_dsp = {
787 	.name	= "davinci-rproc",
788 	.dev	= {
789 		.coherent_dma_mask	= DMA_BIT_MASK(32),
790 	},
791 	.num_resources	= ARRAY_SIZE(da8xx_rproc_resources),
792 	.resource	= da8xx_rproc_resources,
793 };
794 
795 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
796 
797 static phys_addr_t rproc_base __initdata;
798 static unsigned long rproc_size __initdata;
799 
800 static int __init early_rproc_mem(char *p)
801 {
802 	char *endp;
803 
804 	if (p == NULL)
805 		return 0;
806 
807 	rproc_size = memparse(p, &endp);
808 	if (*endp == '@')
809 		rproc_base = memparse(endp + 1, NULL);
810 
811 	return 0;
812 }
813 early_param("rproc_mem", early_rproc_mem);
814 
815 void __init da8xx_rproc_reserve_cma(void)
816 {
817 	int ret;
818 
819 	if (!rproc_base || !rproc_size) {
820 		pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
821 		       "    'nn' and 'address' must both be non-zero\n",
822 		       __func__);
823 
824 		return;
825 	}
826 
827 	pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
828 		__func__, rproc_size, (unsigned long)rproc_base);
829 
830 	ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
831 	if (ret)
832 		pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
833 }
834 
835 #else
836 
837 void __init da8xx_rproc_reserve_cma(void)
838 {
839 }
840 
841 #endif
842 
843 int __init da8xx_register_rproc(void)
844 {
845 	int ret;
846 
847 	ret = platform_device_register(&da8xx_dsp);
848 	if (ret)
849 		pr_err("%s: can't register DSP device: %d\n", __func__, ret);
850 
851 	return ret;
852 };
853 
854 static struct resource da8xx_rtc_resources[] = {
855 	{
856 		.start		= DA8XX_RTC_BASE,
857 		.end		= DA8XX_RTC_BASE + SZ_4K - 1,
858 		.flags		= IORESOURCE_MEM,
859 	},
860 	{ /* timer irq */
861 		.start		= IRQ_DA8XX_RTC,
862 		.end		= IRQ_DA8XX_RTC,
863 		.flags		= IORESOURCE_IRQ,
864 	},
865 	{ /* alarm irq */
866 		.start		= IRQ_DA8XX_RTC,
867 		.end		= IRQ_DA8XX_RTC,
868 		.flags		= IORESOURCE_IRQ,
869 	},
870 };
871 
872 static struct platform_device da8xx_rtc_device = {
873 	.name           = "da830-rtc",
874 	.id             = -1,
875 	.num_resources	= ARRAY_SIZE(da8xx_rtc_resources),
876 	.resource	= da8xx_rtc_resources,
877 };
878 
879 int da8xx_register_rtc(void)
880 {
881 	return platform_device_register(&da8xx_rtc_device);
882 }
883 
884 static void __iomem *da8xx_ddr2_ctlr_base;
885 void __iomem * __init da8xx_get_mem_ctlr(void)
886 {
887 	if (da8xx_ddr2_ctlr_base)
888 		return da8xx_ddr2_ctlr_base;
889 
890 	da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
891 	if (!da8xx_ddr2_ctlr_base)
892 		pr_warn("%s: Unable to map DDR2 controller", __func__);
893 
894 	return da8xx_ddr2_ctlr_base;
895 }
896 
897 static struct resource da8xx_cpuidle_resources[] = {
898 	{
899 		.start		= DA8XX_DDR2_CTL_BASE,
900 		.end		= DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
901 		.flags		= IORESOURCE_MEM,
902 	},
903 };
904 
905 /* DA8XX devices support DDR2 power down */
906 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
907 	.ddr2_pdown	= 1,
908 };
909 
910 
911 static struct platform_device da8xx_cpuidle_device = {
912 	.name			= "cpuidle-davinci",
913 	.num_resources		= ARRAY_SIZE(da8xx_cpuidle_resources),
914 	.resource		= da8xx_cpuidle_resources,
915 	.dev = {
916 		.platform_data	= &da8xx_cpuidle_pdata,
917 	},
918 };
919 
920 int __init da8xx_register_cpuidle(void)
921 {
922 	da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
923 
924 	return platform_device_register(&da8xx_cpuidle_device);
925 }
926 
927 static struct resource da8xx_spi0_resources[] = {
928 	[0] = {
929 		.start	= DA8XX_SPI0_BASE,
930 		.end	= DA8XX_SPI0_BASE + SZ_4K - 1,
931 		.flags	= IORESOURCE_MEM,
932 	},
933 	[1] = {
934 		.start	= IRQ_DA8XX_SPINT0,
935 		.end	= IRQ_DA8XX_SPINT0,
936 		.flags	= IORESOURCE_IRQ,
937 	},
938 	[2] = {
939 		.start	= DA8XX_DMA_SPI0_RX,
940 		.end	= DA8XX_DMA_SPI0_RX,
941 		.flags	= IORESOURCE_DMA,
942 	},
943 	[3] = {
944 		.start	= DA8XX_DMA_SPI0_TX,
945 		.end	= DA8XX_DMA_SPI0_TX,
946 		.flags	= IORESOURCE_DMA,
947 	},
948 };
949 
950 static struct resource da8xx_spi1_resources[] = {
951 	[0] = {
952 		.start	= DA830_SPI1_BASE,
953 		.end	= DA830_SPI1_BASE + SZ_4K - 1,
954 		.flags	= IORESOURCE_MEM,
955 	},
956 	[1] = {
957 		.start	= IRQ_DA8XX_SPINT1,
958 		.end	= IRQ_DA8XX_SPINT1,
959 		.flags	= IORESOURCE_IRQ,
960 	},
961 	[2] = {
962 		.start	= DA8XX_DMA_SPI1_RX,
963 		.end	= DA8XX_DMA_SPI1_RX,
964 		.flags	= IORESOURCE_DMA,
965 	},
966 	[3] = {
967 		.start	= DA8XX_DMA_SPI1_TX,
968 		.end	= DA8XX_DMA_SPI1_TX,
969 		.flags	= IORESOURCE_DMA,
970 	},
971 };
972 
973 static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
974 	[0] = {
975 		.version	= SPI_VERSION_2,
976 		.intr_line	= 1,
977 		.dma_event_q	= EVENTQ_0,
978 	},
979 	[1] = {
980 		.version	= SPI_VERSION_2,
981 		.intr_line	= 1,
982 		.dma_event_q	= EVENTQ_0,
983 	},
984 };
985 
986 static struct platform_device da8xx_spi_device[] = {
987 	[0] = {
988 		.name		= "spi_davinci",
989 		.id		= 0,
990 		.num_resources	= ARRAY_SIZE(da8xx_spi0_resources),
991 		.resource	= da8xx_spi0_resources,
992 		.dev		= {
993 			.platform_data = &da8xx_spi_pdata[0],
994 		},
995 	},
996 	[1] = {
997 		.name		= "spi_davinci",
998 		.id		= 1,
999 		.num_resources	= ARRAY_SIZE(da8xx_spi1_resources),
1000 		.resource	= da8xx_spi1_resources,
1001 		.dev		= {
1002 			.platform_data = &da8xx_spi_pdata[1],
1003 		},
1004 	},
1005 };
1006 
1007 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
1008 {
1009 	if (instance < 0 || instance > 1)
1010 		return -EINVAL;
1011 
1012 	da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
1013 
1014 	if (instance == 1 && cpu_is_davinci_da850()) {
1015 		da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
1016 		da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
1017 	}
1018 
1019 	return platform_device_register(&da8xx_spi_device[instance]);
1020 }
1021 
1022 #ifdef CONFIG_ARCH_DAVINCI_DA850
1023 
1024 static struct resource da850_sata_resources[] = {
1025 	{
1026 		.start	= DA850_SATA_BASE,
1027 		.end	= DA850_SATA_BASE + 0x1fff,
1028 		.flags	= IORESOURCE_MEM,
1029 	},
1030 	{
1031 		.start	= IRQ_DA850_SATAINT,
1032 		.flags	= IORESOURCE_IRQ,
1033 	},
1034 };
1035 
1036 /* SATA PHY Control Register offset from AHCI base */
1037 #define SATA_P0PHYCR_REG	0x178
1038 
1039 #define SATA_PHY_MPY(x)		((x) << 0)
1040 #define SATA_PHY_LOS(x)		((x) << 6)
1041 #define SATA_PHY_RXCDR(x)	((x) << 10)
1042 #define SATA_PHY_RXEQ(x)	((x) << 13)
1043 #define SATA_PHY_TXSWING(x)	((x) << 19)
1044 #define SATA_PHY_ENPLL(x)	((x) << 31)
1045 
1046 static struct clk *da850_sata_clk;
1047 static unsigned long da850_sata_refclkpn;
1048 
1049 /* Supported DA850 SATA crystal frequencies */
1050 #define KHZ_TO_HZ(freq) ((freq) * 1000)
1051 static unsigned long da850_sata_xtal[] = {
1052 	KHZ_TO_HZ(300000),
1053 	KHZ_TO_HZ(250000),
1054 	0,			/* Reserved */
1055 	KHZ_TO_HZ(187500),
1056 	KHZ_TO_HZ(150000),
1057 	KHZ_TO_HZ(125000),
1058 	KHZ_TO_HZ(120000),
1059 	KHZ_TO_HZ(100000),
1060 	KHZ_TO_HZ(75000),
1061 	KHZ_TO_HZ(60000),
1062 };
1063 
1064 static int da850_sata_init(struct device *dev, void __iomem *addr)
1065 {
1066 	int i, ret;
1067 	unsigned int val;
1068 
1069 	da850_sata_clk = clk_get(dev, NULL);
1070 	if (IS_ERR(da850_sata_clk))
1071 		return PTR_ERR(da850_sata_clk);
1072 
1073 	ret = clk_prepare_enable(da850_sata_clk);
1074 	if (ret)
1075 		goto err0;
1076 
1077 	/* Enable SATA clock receiver */
1078 	val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
1079 	val &= ~BIT(0);
1080 	__raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
1081 
1082 	/* Get the multiplier needed for 1.5GHz PLL output */
1083 	for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++)
1084 		if (da850_sata_xtal[i] == da850_sata_refclkpn)
1085 			break;
1086 
1087 	if (i == ARRAY_SIZE(da850_sata_xtal)) {
1088 		ret = -EINVAL;
1089 		goto err1;
1090 	}
1091 
1092 	val = SATA_PHY_MPY(i + 1) |
1093 		SATA_PHY_LOS(1) |
1094 		SATA_PHY_RXCDR(4) |
1095 		SATA_PHY_RXEQ(1) |
1096 		SATA_PHY_TXSWING(3) |
1097 		SATA_PHY_ENPLL(1);
1098 
1099 	__raw_writel(val, addr + SATA_P0PHYCR_REG);
1100 
1101 	return 0;
1102 
1103 err1:
1104 	clk_disable_unprepare(da850_sata_clk);
1105 err0:
1106 	clk_put(da850_sata_clk);
1107 	return ret;
1108 }
1109 
1110 static void da850_sata_exit(struct device *dev)
1111 {
1112 	clk_disable_unprepare(da850_sata_clk);
1113 	clk_put(da850_sata_clk);
1114 }
1115 
1116 static struct ahci_platform_data da850_sata_pdata = {
1117 	.init	= da850_sata_init,
1118 	.exit	= da850_sata_exit,
1119 };
1120 
1121 static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1122 
1123 static struct platform_device da850_sata_device = {
1124 	.name	= "ahci",
1125 	.id	= -1,
1126 	.dev	= {
1127 		.platform_data		= &da850_sata_pdata,
1128 		.dma_mask		= &da850_sata_dmamask,
1129 		.coherent_dma_mask	= DMA_BIT_MASK(32),
1130 	},
1131 	.num_resources	= ARRAY_SIZE(da850_sata_resources),
1132 	.resource	= da850_sata_resources,
1133 };
1134 
1135 int __init da850_register_sata(unsigned long refclkpn)
1136 {
1137 	da850_sata_refclkpn = refclkpn;
1138 	if (!da850_sata_refclkpn)
1139 		return -EINVAL;
1140 
1141 	return platform_device_register(&da850_sata_device);
1142 }
1143 #endif
1144