1 /* 2 * DA8XX/OMAP L1XX platform device data 3 * 4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> 5 * Derived from code that was: 6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 #include <linux/ahci_platform.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clk.h> 16 #include <linux/clkdev.h> 17 #include <linux/dma-contiguous.h> 18 #include <linux/dmaengine.h> 19 #include <linux/init.h> 20 #include <linux/platform_device.h> 21 #include <linux/reboot.h> 22 #include <linux/serial_8250.h> 23 24 #include <mach/common.h> 25 #include <mach/cputype.h> 26 #include <mach/da8xx.h> 27 #include <mach/time.h> 28 29 #include "asp.h" 30 #include "cpuidle.h" 31 #include "irqs.h" 32 #include "sram.h" 33 34 #define DA8XX_TPCC_BASE 0x01c00000 35 #define DA8XX_TPTC0_BASE 0x01c08000 36 #define DA8XX_TPTC1_BASE 0x01c08400 37 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ 38 #define DA8XX_I2C0_BASE 0x01c22000 39 #define DA8XX_RTC_BASE 0x01c23000 40 #define DA8XX_PRUSS_MEM_BASE 0x01c30000 41 #define DA8XX_MMCSD0_BASE 0x01c40000 42 #define DA8XX_SPI0_BASE 0x01c41000 43 #define DA830_SPI1_BASE 0x01e12000 44 #define DA8XX_LCD_CNTRL_BASE 0x01e13000 45 #define DA850_SATA_BASE 0x01e18000 46 #define DA850_MMCSD1_BASE 0x01e1b000 47 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 48 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 49 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 50 #define DA8XX_EMAC_MDIO_BASE 0x01e24000 51 #define DA8XX_I2C1_BASE 0x01e28000 52 #define DA850_TPCC1_BASE 0x01e30000 53 #define DA850_TPTC2_BASE 0x01e38000 54 #define DA850_SPI1_BASE 0x01f0e000 55 #define DA8XX_DDR2_CTL_BASE 0xb0000000 56 57 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 58 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 59 #define DA8XX_EMAC_RAM_OFFSET 0x0000 60 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K 61 62 void __iomem *da8xx_syscfg0_base; 63 void __iomem *da8xx_syscfg1_base; 64 65 static struct plat_serial8250_port da8xx_serial0_pdata[] = { 66 { 67 .mapbase = DA8XX_UART0_BASE, 68 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0), 69 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 70 UPF_IOREMAP, 71 .iotype = UPIO_MEM, 72 .regshift = 2, 73 }, 74 { 75 .flags = 0, 76 } 77 }; 78 static struct plat_serial8250_port da8xx_serial1_pdata[] = { 79 { 80 .mapbase = DA8XX_UART1_BASE, 81 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1), 82 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 83 UPF_IOREMAP, 84 .iotype = UPIO_MEM, 85 .regshift = 2, 86 }, 87 { 88 .flags = 0, 89 } 90 }; 91 static struct plat_serial8250_port da8xx_serial2_pdata[] = { 92 { 93 .mapbase = DA8XX_UART2_BASE, 94 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2), 95 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 96 UPF_IOREMAP, 97 .iotype = UPIO_MEM, 98 .regshift = 2, 99 }, 100 { 101 .flags = 0, 102 } 103 }; 104 105 struct platform_device da8xx_serial_device[] = { 106 { 107 .name = "serial8250", 108 .id = PLAT8250_DEV_PLATFORM, 109 .dev = { 110 .platform_data = da8xx_serial0_pdata, 111 } 112 }, 113 { 114 .name = "serial8250", 115 .id = PLAT8250_DEV_PLATFORM1, 116 .dev = { 117 .platform_data = da8xx_serial1_pdata, 118 } 119 }, 120 { 121 .name = "serial8250", 122 .id = PLAT8250_DEV_PLATFORM2, 123 .dev = { 124 .platform_data = da8xx_serial2_pdata, 125 } 126 }, 127 { 128 } 129 }; 130 131 static s8 da8xx_queue_priority_mapping[][2] = { 132 /* {event queue no, Priority} */ 133 {0, 3}, 134 {1, 7}, 135 {-1, -1} 136 }; 137 138 static s8 da850_queue_priority_mapping[][2] = { 139 /* {event queue no, Priority} */ 140 {0, 3}, 141 {-1, -1} 142 }; 143 144 static struct edma_soc_info da8xx_edma0_pdata = { 145 .queue_priority_mapping = da8xx_queue_priority_mapping, 146 .default_queue = EVENTQ_1, 147 }; 148 149 static struct edma_soc_info da850_edma1_pdata = { 150 .queue_priority_mapping = da850_queue_priority_mapping, 151 .default_queue = EVENTQ_0, 152 }; 153 154 static struct resource da8xx_edma0_resources[] = { 155 { 156 .name = "edma3_cc", 157 .start = DA8XX_TPCC_BASE, 158 .end = DA8XX_TPCC_BASE + SZ_32K - 1, 159 .flags = IORESOURCE_MEM, 160 }, 161 { 162 .name = "edma3_tc0", 163 .start = DA8XX_TPTC0_BASE, 164 .end = DA8XX_TPTC0_BASE + SZ_1K - 1, 165 .flags = IORESOURCE_MEM, 166 }, 167 { 168 .name = "edma3_tc1", 169 .start = DA8XX_TPTC1_BASE, 170 .end = DA8XX_TPTC1_BASE + SZ_1K - 1, 171 .flags = IORESOURCE_MEM, 172 }, 173 { 174 .name = "edma3_ccint", 175 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0), 176 .flags = IORESOURCE_IRQ, 177 }, 178 { 179 .name = "edma3_ccerrint", 180 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT), 181 .flags = IORESOURCE_IRQ, 182 }, 183 }; 184 185 static struct resource da850_edma1_resources[] = { 186 { 187 .name = "edma3_cc", 188 .start = DA850_TPCC1_BASE, 189 .end = DA850_TPCC1_BASE + SZ_32K - 1, 190 .flags = IORESOURCE_MEM, 191 }, 192 { 193 .name = "edma3_tc0", 194 .start = DA850_TPTC2_BASE, 195 .end = DA850_TPTC2_BASE + SZ_1K - 1, 196 .flags = IORESOURCE_MEM, 197 }, 198 { 199 .name = "edma3_ccint", 200 .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1), 201 .flags = IORESOURCE_IRQ, 202 }, 203 { 204 .name = "edma3_ccerrint", 205 .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1), 206 .flags = IORESOURCE_IRQ, 207 }, 208 }; 209 210 static const struct platform_device_info da8xx_edma0_device __initconst = { 211 .name = "edma", 212 .id = 0, 213 .dma_mask = DMA_BIT_MASK(32), 214 .res = da8xx_edma0_resources, 215 .num_res = ARRAY_SIZE(da8xx_edma0_resources), 216 .data = &da8xx_edma0_pdata, 217 .size_data = sizeof(da8xx_edma0_pdata), 218 }; 219 220 static const struct platform_device_info da850_edma1_device __initconst = { 221 .name = "edma", 222 .id = 1, 223 .dma_mask = DMA_BIT_MASK(32), 224 .res = da850_edma1_resources, 225 .num_res = ARRAY_SIZE(da850_edma1_resources), 226 .data = &da850_edma1_pdata, 227 .size_data = sizeof(da850_edma1_pdata), 228 }; 229 230 static const struct dma_slave_map da830_edma_map[] = { 231 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) }, 232 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) }, 233 { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) }, 234 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) }, 235 { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) }, 236 { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) }, 237 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) }, 238 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) }, 239 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) }, 240 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) }, 241 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) }, 242 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) }, 243 }; 244 245 int __init da830_register_edma(struct edma_rsv_info *rsv) 246 { 247 struct platform_device *edma_pdev; 248 249 da8xx_edma0_pdata.rsv = rsv; 250 251 da8xx_edma0_pdata.slave_map = da830_edma_map; 252 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map); 253 254 edma_pdev = platform_device_register_full(&da8xx_edma0_device); 255 return PTR_ERR_OR_ZERO(edma_pdev); 256 } 257 258 static const struct dma_slave_map da850_edma0_map[] = { 259 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) }, 260 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) }, 261 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) }, 262 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) }, 263 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) }, 264 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) }, 265 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) }, 266 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) }, 267 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) }, 268 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) }, 269 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) }, 270 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) }, 271 }; 272 273 static const struct dma_slave_map da850_edma1_map[] = { 274 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) }, 275 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) }, 276 }; 277 278 int __init da850_register_edma(struct edma_rsv_info *rsv[2]) 279 { 280 struct platform_device *edma_pdev; 281 282 if (rsv) { 283 da8xx_edma0_pdata.rsv = rsv[0]; 284 da850_edma1_pdata.rsv = rsv[1]; 285 } 286 287 da8xx_edma0_pdata.slave_map = da850_edma0_map; 288 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map); 289 290 edma_pdev = platform_device_register_full(&da8xx_edma0_device); 291 if (IS_ERR(edma_pdev)) { 292 pr_warn("%s: Failed to register eDMA0\n", __func__); 293 return PTR_ERR(edma_pdev); 294 } 295 296 da850_edma1_pdata.slave_map = da850_edma1_map; 297 da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map); 298 299 edma_pdev = platform_device_register_full(&da850_edma1_device); 300 return PTR_ERR_OR_ZERO(edma_pdev); 301 } 302 303 static struct resource da8xx_i2c_resources0[] = { 304 { 305 .start = DA8XX_I2C0_BASE, 306 .end = DA8XX_I2C0_BASE + SZ_4K - 1, 307 .flags = IORESOURCE_MEM, 308 }, 309 { 310 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0), 311 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0), 312 .flags = IORESOURCE_IRQ, 313 }, 314 }; 315 316 static struct platform_device da8xx_i2c_device0 = { 317 .name = "i2c_davinci", 318 .id = 1, 319 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), 320 .resource = da8xx_i2c_resources0, 321 }; 322 323 static struct resource da8xx_i2c_resources1[] = { 324 { 325 .start = DA8XX_I2C1_BASE, 326 .end = DA8XX_I2C1_BASE + SZ_4K - 1, 327 .flags = IORESOURCE_MEM, 328 }, 329 { 330 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1), 331 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1), 332 .flags = IORESOURCE_IRQ, 333 }, 334 }; 335 336 static struct platform_device da8xx_i2c_device1 = { 337 .name = "i2c_davinci", 338 .id = 2, 339 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), 340 .resource = da8xx_i2c_resources1, 341 }; 342 343 int __init da8xx_register_i2c(int instance, 344 struct davinci_i2c_platform_data *pdata) 345 { 346 struct platform_device *pdev; 347 348 if (instance == 0) 349 pdev = &da8xx_i2c_device0; 350 else if (instance == 1) 351 pdev = &da8xx_i2c_device1; 352 else 353 return -EINVAL; 354 355 pdev->dev.platform_data = pdata; 356 return platform_device_register(pdev); 357 } 358 359 static struct resource da8xx_watchdog_resources[] = { 360 { 361 .start = DA8XX_WDOG_BASE, 362 .end = DA8XX_WDOG_BASE + SZ_4K - 1, 363 .flags = IORESOURCE_MEM, 364 }, 365 }; 366 367 static struct platform_device da8xx_wdt_device = { 368 .name = "davinci-wdt", 369 .id = -1, 370 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), 371 .resource = da8xx_watchdog_resources, 372 }; 373 374 int __init da8xx_register_watchdog(void) 375 { 376 return platform_device_register(&da8xx_wdt_device); 377 } 378 379 static struct resource da8xx_emac_resources[] = { 380 { 381 .start = DA8XX_EMAC_CPPI_PORT_BASE, 382 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1, 383 .flags = IORESOURCE_MEM, 384 }, 385 { 386 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE), 387 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE), 388 .flags = IORESOURCE_IRQ, 389 }, 390 { 391 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE), 392 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE), 393 .flags = IORESOURCE_IRQ, 394 }, 395 { 396 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE), 397 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE), 398 .flags = IORESOURCE_IRQ, 399 }, 400 { 401 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE), 402 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE), 403 .flags = IORESOURCE_IRQ, 404 }, 405 }; 406 407 struct emac_platform_data da8xx_emac_pdata = { 408 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, 409 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, 410 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, 411 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, 412 .version = EMAC_VERSION_2, 413 }; 414 415 static struct platform_device da8xx_emac_device = { 416 .name = "davinci_emac", 417 .id = 1, 418 .dev = { 419 .platform_data = &da8xx_emac_pdata, 420 }, 421 .num_resources = ARRAY_SIZE(da8xx_emac_resources), 422 .resource = da8xx_emac_resources, 423 }; 424 425 static struct resource da8xx_mdio_resources[] = { 426 { 427 .start = DA8XX_EMAC_MDIO_BASE, 428 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1, 429 .flags = IORESOURCE_MEM, 430 }, 431 }; 432 433 static struct platform_device da8xx_mdio_device = { 434 .name = "davinci_mdio", 435 .id = 0, 436 .num_resources = ARRAY_SIZE(da8xx_mdio_resources), 437 .resource = da8xx_mdio_resources, 438 }; 439 440 int __init da8xx_register_emac(void) 441 { 442 int ret; 443 444 ret = platform_device_register(&da8xx_mdio_device); 445 if (ret < 0) 446 return ret; 447 448 return platform_device_register(&da8xx_emac_device); 449 } 450 451 static struct resource da830_mcasp1_resources[] = { 452 { 453 .name = "mpu", 454 .start = DAVINCI_DA830_MCASP1_REG_BASE, 455 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, 456 .flags = IORESOURCE_MEM, 457 }, 458 /* TX event */ 459 { 460 .name = "tx", 461 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, 462 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, 463 .flags = IORESOURCE_DMA, 464 }, 465 /* RX event */ 466 { 467 .name = "rx", 468 .start = DAVINCI_DA830_DMA_MCASP1_AREVT, 469 .end = DAVINCI_DA830_DMA_MCASP1_AREVT, 470 .flags = IORESOURCE_DMA, 471 }, 472 { 473 .name = "common", 474 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT), 475 .flags = IORESOURCE_IRQ, 476 }, 477 }; 478 479 static struct platform_device da830_mcasp1_device = { 480 .name = "davinci-mcasp", 481 .id = 1, 482 .num_resources = ARRAY_SIZE(da830_mcasp1_resources), 483 .resource = da830_mcasp1_resources, 484 }; 485 486 static struct resource da830_mcasp2_resources[] = { 487 { 488 .name = "mpu", 489 .start = DAVINCI_DA830_MCASP2_REG_BASE, 490 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1, 491 .flags = IORESOURCE_MEM, 492 }, 493 /* TX event */ 494 { 495 .name = "tx", 496 .start = DAVINCI_DA830_DMA_MCASP2_AXEVT, 497 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT, 498 .flags = IORESOURCE_DMA, 499 }, 500 /* RX event */ 501 { 502 .name = "rx", 503 .start = DAVINCI_DA830_DMA_MCASP2_AREVT, 504 .end = DAVINCI_DA830_DMA_MCASP2_AREVT, 505 .flags = IORESOURCE_DMA, 506 }, 507 { 508 .name = "common", 509 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT), 510 .flags = IORESOURCE_IRQ, 511 }, 512 }; 513 514 static struct platform_device da830_mcasp2_device = { 515 .name = "davinci-mcasp", 516 .id = 2, 517 .num_resources = ARRAY_SIZE(da830_mcasp2_resources), 518 .resource = da830_mcasp2_resources, 519 }; 520 521 static struct resource da850_mcasp_resources[] = { 522 { 523 .name = "mpu", 524 .start = DAVINCI_DA8XX_MCASP0_REG_BASE, 525 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, 526 .flags = IORESOURCE_MEM, 527 }, 528 /* TX event */ 529 { 530 .name = "tx", 531 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 532 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 533 .flags = IORESOURCE_DMA, 534 }, 535 /* RX event */ 536 { 537 .name = "rx", 538 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 539 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 540 .flags = IORESOURCE_DMA, 541 }, 542 { 543 .name = "common", 544 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT), 545 .flags = IORESOURCE_IRQ, 546 }, 547 }; 548 549 static struct platform_device da850_mcasp_device = { 550 .name = "davinci-mcasp", 551 .id = 0, 552 .num_resources = ARRAY_SIZE(da850_mcasp_resources), 553 .resource = da850_mcasp_resources, 554 }; 555 556 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) 557 { 558 struct platform_device *pdev; 559 560 switch (id) { 561 case 0: 562 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */ 563 pdev = &da850_mcasp_device; 564 break; 565 case 1: 566 /* Valid for DA830/OMAP-L137 only */ 567 if (!cpu_is_davinci_da830()) 568 return; 569 pdev = &da830_mcasp1_device; 570 break; 571 case 2: 572 /* Valid for DA830/OMAP-L137 only */ 573 if (!cpu_is_davinci_da830()) 574 return; 575 pdev = &da830_mcasp2_device; 576 break; 577 default: 578 return; 579 } 580 581 pdev->dev.platform_data = pdata; 582 platform_device_register(pdev); 583 } 584 585 static struct resource da8xx_pruss_resources[] = { 586 { 587 .start = DA8XX_PRUSS_MEM_BASE, 588 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF, 589 .flags = IORESOURCE_MEM, 590 }, 591 { 592 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0), 593 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0), 594 .flags = IORESOURCE_IRQ, 595 }, 596 { 597 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1), 598 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1), 599 .flags = IORESOURCE_IRQ, 600 }, 601 { 602 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2), 603 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2), 604 .flags = IORESOURCE_IRQ, 605 }, 606 { 607 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3), 608 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3), 609 .flags = IORESOURCE_IRQ, 610 }, 611 { 612 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4), 613 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4), 614 .flags = IORESOURCE_IRQ, 615 }, 616 { 617 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5), 618 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5), 619 .flags = IORESOURCE_IRQ, 620 }, 621 { 622 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6), 623 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6), 624 .flags = IORESOURCE_IRQ, 625 }, 626 { 627 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7), 628 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7), 629 .flags = IORESOURCE_IRQ, 630 }, 631 }; 632 633 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = { 634 .pintc_base = 0x4000, 635 }; 636 637 static struct platform_device da8xx_uio_pruss_dev = { 638 .name = "pruss_uio", 639 .id = -1, 640 .num_resources = ARRAY_SIZE(da8xx_pruss_resources), 641 .resource = da8xx_pruss_resources, 642 .dev = { 643 .coherent_dma_mask = DMA_BIT_MASK(32), 644 .platform_data = &da8xx_uio_pruss_pdata, 645 } 646 }; 647 648 int __init da8xx_register_uio_pruss(void) 649 { 650 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool(); 651 return platform_device_register(&da8xx_uio_pruss_dev); 652 } 653 654 static struct lcd_ctrl_config lcd_cfg = { 655 .panel_shade = COLOR_ACTIVE, 656 .bpp = 16, 657 }; 658 659 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = { 660 .manu_name = "sharp", 661 .controller_data = &lcd_cfg, 662 .type = "Sharp_LCD035Q3DG01", 663 }; 664 665 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = { 666 .manu_name = "sharp", 667 .controller_data = &lcd_cfg, 668 .type = "Sharp_LK043T1DG01", 669 }; 670 671 static struct resource da8xx_lcdc_resources[] = { 672 [0] = { /* registers */ 673 .start = DA8XX_LCD_CNTRL_BASE, 674 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, 675 .flags = IORESOURCE_MEM, 676 }, 677 [1] = { /* interrupt */ 678 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT), 679 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT), 680 .flags = IORESOURCE_IRQ, 681 }, 682 }; 683 684 static struct platform_device da8xx_lcdc_device = { 685 .name = "da8xx_lcdc", 686 .id = 0, 687 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), 688 .resource = da8xx_lcdc_resources, 689 }; 690 691 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) 692 { 693 da8xx_lcdc_device.dev.platform_data = pdata; 694 return platform_device_register(&da8xx_lcdc_device); 695 } 696 697 static struct resource da8xx_gpio_resources[] = { 698 { /* registers */ 699 .start = DA8XX_GPIO_BASE, 700 .end = DA8XX_GPIO_BASE + SZ_4K - 1, 701 .flags = IORESOURCE_MEM, 702 }, 703 { /* interrupt */ 704 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0), 705 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0), 706 .flags = IORESOURCE_IRQ, 707 }, 708 { 709 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1), 710 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1), 711 .flags = IORESOURCE_IRQ, 712 }, 713 { 714 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2), 715 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2), 716 .flags = IORESOURCE_IRQ, 717 }, 718 { 719 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3), 720 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3), 721 .flags = IORESOURCE_IRQ, 722 }, 723 { 724 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4), 725 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4), 726 .flags = IORESOURCE_IRQ, 727 }, 728 { 729 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5), 730 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5), 731 .flags = IORESOURCE_IRQ, 732 }, 733 { 734 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6), 735 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6), 736 .flags = IORESOURCE_IRQ, 737 }, 738 { 739 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7), 740 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7), 741 .flags = IORESOURCE_IRQ, 742 }, 743 { 744 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8), 745 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8), 746 .flags = IORESOURCE_IRQ, 747 }, 748 }; 749 750 static struct platform_device da8xx_gpio_device = { 751 .name = "davinci_gpio", 752 .id = -1, 753 .num_resources = ARRAY_SIZE(da8xx_gpio_resources), 754 .resource = da8xx_gpio_resources, 755 }; 756 757 int __init da8xx_register_gpio(void *pdata) 758 { 759 da8xx_gpio_device.dev.platform_data = pdata; 760 return platform_device_register(&da8xx_gpio_device); 761 } 762 763 static struct resource da8xx_mmcsd0_resources[] = { 764 { /* registers */ 765 .start = DA8XX_MMCSD0_BASE, 766 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, 767 .flags = IORESOURCE_MEM, 768 }, 769 { /* interrupt */ 770 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0), 771 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0), 772 .flags = IORESOURCE_IRQ, 773 }, 774 }; 775 776 static struct platform_device da8xx_mmcsd0_device = { 777 .name = "da830-mmc", 778 .id = 0, 779 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), 780 .resource = da8xx_mmcsd0_resources, 781 }; 782 783 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) 784 { 785 da8xx_mmcsd0_device.dev.platform_data = config; 786 return platform_device_register(&da8xx_mmcsd0_device); 787 } 788 789 #ifdef CONFIG_ARCH_DAVINCI_DA850 790 static struct resource da850_mmcsd1_resources[] = { 791 { /* registers */ 792 .start = DA850_MMCSD1_BASE, 793 .end = DA850_MMCSD1_BASE + SZ_4K - 1, 794 .flags = IORESOURCE_MEM, 795 }, 796 { /* interrupt */ 797 .start = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1), 798 .end = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1), 799 .flags = IORESOURCE_IRQ, 800 }, 801 }; 802 803 static struct platform_device da850_mmcsd1_device = { 804 .name = "da830-mmc", 805 .id = 1, 806 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), 807 .resource = da850_mmcsd1_resources, 808 }; 809 810 int __init da850_register_mmcsd1(struct davinci_mmc_config *config) 811 { 812 da850_mmcsd1_device.dev.platform_data = config; 813 return platform_device_register(&da850_mmcsd1_device); 814 } 815 #endif 816 817 static struct resource da8xx_rproc_resources[] = { 818 { /* DSP boot address */ 819 .name = "host1cfg", 820 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG, 821 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3, 822 .flags = IORESOURCE_MEM, 823 }, 824 { /* DSP interrupt registers */ 825 .name = "chipsig", 826 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG, 827 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7, 828 .flags = IORESOURCE_MEM, 829 }, 830 { /* DSP L2 RAM */ 831 .name = "l2sram", 832 .start = DA8XX_DSP_L2_RAM_BASE, 833 .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1, 834 .flags = IORESOURCE_MEM, 835 }, 836 { /* DSP L1P RAM */ 837 .name = "l1pram", 838 .start = DA8XX_DSP_L1P_RAM_BASE, 839 .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1, 840 .flags = IORESOURCE_MEM, 841 }, 842 { /* DSP L1D RAM */ 843 .name = "l1dram", 844 .start = DA8XX_DSP_L1D_RAM_BASE, 845 .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1, 846 .flags = IORESOURCE_MEM, 847 }, 848 { /* dsp irq */ 849 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0), 850 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0), 851 .flags = IORESOURCE_IRQ, 852 }, 853 }; 854 855 static struct platform_device da8xx_dsp = { 856 .name = "davinci-rproc", 857 .dev = { 858 .coherent_dma_mask = DMA_BIT_MASK(32), 859 }, 860 .num_resources = ARRAY_SIZE(da8xx_rproc_resources), 861 .resource = da8xx_rproc_resources, 862 }; 863 864 static bool rproc_mem_inited __initdata; 865 866 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC) 867 868 static phys_addr_t rproc_base __initdata; 869 static unsigned long rproc_size __initdata; 870 871 static int __init early_rproc_mem(char *p) 872 { 873 char *endp; 874 875 if (p == NULL) 876 return 0; 877 878 rproc_size = memparse(p, &endp); 879 if (*endp == '@') 880 rproc_base = memparse(endp + 1, NULL); 881 882 return 0; 883 } 884 early_param("rproc_mem", early_rproc_mem); 885 886 void __init da8xx_rproc_reserve_cma(void) 887 { 888 int ret; 889 890 if (!rproc_base || !rproc_size) { 891 pr_err("%s: 'rproc_mem=nn@address' badly specified\n" 892 " 'nn' and 'address' must both be non-zero\n", 893 __func__); 894 895 return; 896 } 897 898 pr_info("%s: reserving 0x%lx @ 0x%lx...\n", 899 __func__, rproc_size, (unsigned long)rproc_base); 900 901 ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0); 902 if (ret) 903 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret); 904 else 905 rproc_mem_inited = true; 906 } 907 908 #else 909 910 void __init da8xx_rproc_reserve_cma(void) 911 { 912 } 913 914 #endif 915 916 int __init da8xx_register_rproc(void) 917 { 918 int ret; 919 920 if (!rproc_mem_inited) { 921 pr_warn("%s: memory not reserved for DSP, not registering DSP device\n", 922 __func__); 923 return -ENOMEM; 924 } 925 926 ret = platform_device_register(&da8xx_dsp); 927 if (ret) 928 pr_err("%s: can't register DSP device: %d\n", __func__, ret); 929 930 return ret; 931 }; 932 933 static struct resource da8xx_rtc_resources[] = { 934 { 935 .start = DA8XX_RTC_BASE, 936 .end = DA8XX_RTC_BASE + SZ_4K - 1, 937 .flags = IORESOURCE_MEM, 938 }, 939 { /* timer irq */ 940 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), 941 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), 942 .flags = IORESOURCE_IRQ, 943 }, 944 { /* alarm irq */ 945 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), 946 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), 947 .flags = IORESOURCE_IRQ, 948 }, 949 }; 950 951 static struct platform_device da8xx_rtc_device = { 952 .name = "da830-rtc", 953 .id = -1, 954 .num_resources = ARRAY_SIZE(da8xx_rtc_resources), 955 .resource = da8xx_rtc_resources, 956 }; 957 958 int da8xx_register_rtc(void) 959 { 960 return platform_device_register(&da8xx_rtc_device); 961 } 962 963 static void __iomem *da8xx_ddr2_ctlr_base; 964 void __iomem * __init da8xx_get_mem_ctlr(void) 965 { 966 if (da8xx_ddr2_ctlr_base) 967 return da8xx_ddr2_ctlr_base; 968 969 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K); 970 if (!da8xx_ddr2_ctlr_base) 971 pr_warn("%s: Unable to map DDR2 controller", __func__); 972 973 return da8xx_ddr2_ctlr_base; 974 } 975 976 static struct resource da8xx_cpuidle_resources[] = { 977 { 978 .start = DA8XX_DDR2_CTL_BASE, 979 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1, 980 .flags = IORESOURCE_MEM, 981 }, 982 }; 983 984 /* DA8XX devices support DDR2 power down */ 985 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = { 986 .ddr2_pdown = 1, 987 }; 988 989 990 static struct platform_device da8xx_cpuidle_device = { 991 .name = "cpuidle-davinci", 992 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources), 993 .resource = da8xx_cpuidle_resources, 994 .dev = { 995 .platform_data = &da8xx_cpuidle_pdata, 996 }, 997 }; 998 999 int __init da8xx_register_cpuidle(void) 1000 { 1001 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr(); 1002 1003 return platform_device_register(&da8xx_cpuidle_device); 1004 } 1005 1006 static struct resource da8xx_spi0_resources[] = { 1007 [0] = { 1008 .start = DA8XX_SPI0_BASE, 1009 .end = DA8XX_SPI0_BASE + SZ_4K - 1, 1010 .flags = IORESOURCE_MEM, 1011 }, 1012 [1] = { 1013 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0), 1014 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0), 1015 .flags = IORESOURCE_IRQ, 1016 }, 1017 }; 1018 1019 static struct resource da8xx_spi1_resources[] = { 1020 [0] = { 1021 .start = DA830_SPI1_BASE, 1022 .end = DA830_SPI1_BASE + SZ_4K - 1, 1023 .flags = IORESOURCE_MEM, 1024 }, 1025 [1] = { 1026 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1), 1027 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1), 1028 .flags = IORESOURCE_IRQ, 1029 }, 1030 }; 1031 1032 static struct davinci_spi_platform_data da8xx_spi_pdata[] = { 1033 [0] = { 1034 .version = SPI_VERSION_2, 1035 .intr_line = 1, 1036 .dma_event_q = EVENTQ_0, 1037 .prescaler_limit = 2, 1038 }, 1039 [1] = { 1040 .version = SPI_VERSION_2, 1041 .intr_line = 1, 1042 .dma_event_q = EVENTQ_0, 1043 .prescaler_limit = 2, 1044 }, 1045 }; 1046 1047 static struct platform_device da8xx_spi_device[] = { 1048 [0] = { 1049 .name = "spi_davinci", 1050 .id = 0, 1051 .num_resources = ARRAY_SIZE(da8xx_spi0_resources), 1052 .resource = da8xx_spi0_resources, 1053 .dev = { 1054 .platform_data = &da8xx_spi_pdata[0], 1055 }, 1056 }, 1057 [1] = { 1058 .name = "spi_davinci", 1059 .id = 1, 1060 .num_resources = ARRAY_SIZE(da8xx_spi1_resources), 1061 .resource = da8xx_spi1_resources, 1062 .dev = { 1063 .platform_data = &da8xx_spi_pdata[1], 1064 }, 1065 }, 1066 }; 1067 1068 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect) 1069 { 1070 if (instance < 0 || instance > 1) 1071 return -EINVAL; 1072 1073 da8xx_spi_pdata[instance].num_chipselect = num_chipselect; 1074 1075 if (instance == 1 && cpu_is_davinci_da850()) { 1076 da8xx_spi1_resources[0].start = DA850_SPI1_BASE; 1077 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; 1078 } 1079 1080 return platform_device_register(&da8xx_spi_device[instance]); 1081 } 1082 1083 #ifdef CONFIG_ARCH_DAVINCI_DA850 1084 int __init da850_register_sata_refclk(int rate) 1085 { 1086 struct clk *clk; 1087 1088 clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate); 1089 if (IS_ERR(clk)) 1090 return PTR_ERR(clk); 1091 1092 return clk_register_clkdev(clk, "refclk", "ahci_da850"); 1093 } 1094 1095 static struct resource da850_sata_resources[] = { 1096 { 1097 .start = DA850_SATA_BASE, 1098 .end = DA850_SATA_BASE + 0x1fff, 1099 .flags = IORESOURCE_MEM, 1100 }, 1101 { 1102 .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG, 1103 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3, 1104 .flags = IORESOURCE_MEM, 1105 }, 1106 { 1107 .start = DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT), 1108 .flags = IORESOURCE_IRQ, 1109 }, 1110 }; 1111 1112 static u64 da850_sata_dmamask = DMA_BIT_MASK(32); 1113 1114 static struct platform_device da850_sata_device = { 1115 .name = "ahci_da850", 1116 .id = -1, 1117 .dev = { 1118 .dma_mask = &da850_sata_dmamask, 1119 .coherent_dma_mask = DMA_BIT_MASK(32), 1120 }, 1121 .num_resources = ARRAY_SIZE(da850_sata_resources), 1122 .resource = da850_sata_resources, 1123 }; 1124 1125 int __init da850_register_sata(unsigned long refclkpn) 1126 { 1127 int ret; 1128 1129 ret = da850_register_sata_refclk(refclkpn); 1130 if (ret) 1131 return ret; 1132 1133 return platform_device_register(&da850_sata_device); 1134 } 1135 #endif 1136 1137 static struct regmap *da8xx_cfgchip; 1138 1139 static const struct regmap_config da8xx_cfgchip_config __initconst = { 1140 .name = "cfgchip", 1141 .reg_bits = 32, 1142 .val_bits = 32, 1143 .reg_stride = 4, 1144 .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG, 1145 }; 1146 1147 /** 1148 * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap 1149 * 1150 * This is for use on non-DT boards only. For DT boards, use 1151 * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip") 1152 * 1153 * Returns: Pointer to the CFGCHIP regmap or negative error code. 1154 */ 1155 struct regmap * __init da8xx_get_cfgchip(void) 1156 { 1157 if (IS_ERR_OR_NULL(da8xx_cfgchip)) 1158 da8xx_cfgchip = regmap_init_mmio(NULL, 1159 DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG), 1160 &da8xx_cfgchip_config); 1161 1162 return da8xx_cfgchip; 1163 } 1164