1 /* 2 * TI DA850/OMAP-L138 chip specific setup 3 * 4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * Derived from: arch/arm/mach-davinci/da830.c 7 * Original Copyrights follow: 8 * 9 * 2009 (c) MontaVista Software, Inc. This file is licensed under 10 * the terms of the GNU General Public License version 2. This program 11 * is licensed "as is" without any warranty of any kind, whether express 12 * or implied. 13 */ 14 #include <linux/init.h> 15 #include <linux/clk.h> 16 #include <linux/platform_device.h> 17 #include <linux/cpufreq.h> 18 #include <linux/regulator/consumer.h> 19 20 #include <asm/mach/map.h> 21 22 #include <mach/psc.h> 23 #include <mach/irqs.h> 24 #include <mach/cputype.h> 25 #include <mach/common.h> 26 #include <mach/time.h> 27 #include <mach/da8xx.h> 28 #include <mach/cpufreq.h> 29 #include <mach/pm.h> 30 #include <mach/gpio.h> 31 32 #include "clock.h" 33 #include "mux.h" 34 35 /* SoC specific clock flags */ 36 #define DA850_CLK_ASYNC3 BIT(16) 37 38 #define DA850_PLL1_BASE 0x01e1a000 39 #define DA850_TIMER64P2_BASE 0x01f0c000 40 #define DA850_TIMER64P3_BASE 0x01f0d000 41 42 #define DA850_REF_FREQ 24000000 43 44 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4) 45 #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5) 46 #define CFGCHIP0_PLL_MASTER_LOCK BIT(4) 47 48 static int da850_set_armrate(struct clk *clk, unsigned long rate); 49 static int da850_round_armrate(struct clk *clk, unsigned long rate); 50 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate); 51 52 static struct pll_data pll0_data = { 53 .num = 1, 54 .phys_base = DA8XX_PLL0_BASE, 55 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, 56 }; 57 58 static struct clk ref_clk = { 59 .name = "ref_clk", 60 .rate = DA850_REF_FREQ, 61 }; 62 63 static struct clk pll0_clk = { 64 .name = "pll0", 65 .parent = &ref_clk, 66 .pll_data = &pll0_data, 67 .flags = CLK_PLL, 68 .set_rate = da850_set_pll0rate, 69 }; 70 71 static struct clk pll0_aux_clk = { 72 .name = "pll0_aux_clk", 73 .parent = &pll0_clk, 74 .flags = CLK_PLL | PRE_PLL, 75 }; 76 77 static struct clk pll0_sysclk2 = { 78 .name = "pll0_sysclk2", 79 .parent = &pll0_clk, 80 .flags = CLK_PLL, 81 .div_reg = PLLDIV2, 82 }; 83 84 static struct clk pll0_sysclk3 = { 85 .name = "pll0_sysclk3", 86 .parent = &pll0_clk, 87 .flags = CLK_PLL, 88 .div_reg = PLLDIV3, 89 .set_rate = davinci_set_sysclk_rate, 90 .maxrate = 100000000, 91 }; 92 93 static struct clk pll0_sysclk4 = { 94 .name = "pll0_sysclk4", 95 .parent = &pll0_clk, 96 .flags = CLK_PLL, 97 .div_reg = PLLDIV4, 98 }; 99 100 static struct clk pll0_sysclk5 = { 101 .name = "pll0_sysclk5", 102 .parent = &pll0_clk, 103 .flags = CLK_PLL, 104 .div_reg = PLLDIV5, 105 }; 106 107 static struct clk pll0_sysclk6 = { 108 .name = "pll0_sysclk6", 109 .parent = &pll0_clk, 110 .flags = CLK_PLL, 111 .div_reg = PLLDIV6, 112 }; 113 114 static struct clk pll0_sysclk7 = { 115 .name = "pll0_sysclk7", 116 .parent = &pll0_clk, 117 .flags = CLK_PLL, 118 .div_reg = PLLDIV7, 119 }; 120 121 static struct pll_data pll1_data = { 122 .num = 2, 123 .phys_base = DA850_PLL1_BASE, 124 .flags = PLL_HAS_POSTDIV, 125 }; 126 127 static struct clk pll1_clk = { 128 .name = "pll1", 129 .parent = &ref_clk, 130 .pll_data = &pll1_data, 131 .flags = CLK_PLL, 132 }; 133 134 static struct clk pll1_aux_clk = { 135 .name = "pll1_aux_clk", 136 .parent = &pll1_clk, 137 .flags = CLK_PLL | PRE_PLL, 138 }; 139 140 static struct clk pll1_sysclk2 = { 141 .name = "pll1_sysclk2", 142 .parent = &pll1_clk, 143 .flags = CLK_PLL, 144 .div_reg = PLLDIV2, 145 }; 146 147 static struct clk pll1_sysclk3 = { 148 .name = "pll1_sysclk3", 149 .parent = &pll1_clk, 150 .flags = CLK_PLL, 151 .div_reg = PLLDIV3, 152 }; 153 154 static struct clk pll1_sysclk4 = { 155 .name = "pll1_sysclk4", 156 .parent = &pll1_clk, 157 .flags = CLK_PLL, 158 .div_reg = PLLDIV4, 159 }; 160 161 static struct clk pll1_sysclk5 = { 162 .name = "pll1_sysclk5", 163 .parent = &pll1_clk, 164 .flags = CLK_PLL, 165 .div_reg = PLLDIV5, 166 }; 167 168 static struct clk pll1_sysclk6 = { 169 .name = "pll0_sysclk6", 170 .parent = &pll0_clk, 171 .flags = CLK_PLL, 172 .div_reg = PLLDIV6, 173 }; 174 175 static struct clk pll1_sysclk7 = { 176 .name = "pll1_sysclk7", 177 .parent = &pll1_clk, 178 .flags = CLK_PLL, 179 .div_reg = PLLDIV7, 180 }; 181 182 static struct clk i2c0_clk = { 183 .name = "i2c0", 184 .parent = &pll0_aux_clk, 185 }; 186 187 static struct clk timerp64_0_clk = { 188 .name = "timer0", 189 .parent = &pll0_aux_clk, 190 }; 191 192 static struct clk timerp64_1_clk = { 193 .name = "timer1", 194 .parent = &pll0_aux_clk, 195 }; 196 197 static struct clk arm_rom_clk = { 198 .name = "arm_rom", 199 .parent = &pll0_sysclk2, 200 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, 201 .flags = ALWAYS_ENABLED, 202 }; 203 204 static struct clk tpcc0_clk = { 205 .name = "tpcc0", 206 .parent = &pll0_sysclk2, 207 .lpsc = DA8XX_LPSC0_TPCC, 208 .flags = ALWAYS_ENABLED | CLK_PSC, 209 }; 210 211 static struct clk tptc0_clk = { 212 .name = "tptc0", 213 .parent = &pll0_sysclk2, 214 .lpsc = DA8XX_LPSC0_TPTC0, 215 .flags = ALWAYS_ENABLED, 216 }; 217 218 static struct clk tptc1_clk = { 219 .name = "tptc1", 220 .parent = &pll0_sysclk2, 221 .lpsc = DA8XX_LPSC0_TPTC1, 222 .flags = ALWAYS_ENABLED, 223 }; 224 225 static struct clk tpcc1_clk = { 226 .name = "tpcc1", 227 .parent = &pll0_sysclk2, 228 .lpsc = DA850_LPSC1_TPCC1, 229 .gpsc = 1, 230 .flags = CLK_PSC | ALWAYS_ENABLED, 231 }; 232 233 static struct clk tptc2_clk = { 234 .name = "tptc2", 235 .parent = &pll0_sysclk2, 236 .lpsc = DA850_LPSC1_TPTC2, 237 .gpsc = 1, 238 .flags = ALWAYS_ENABLED, 239 }; 240 241 static struct clk uart0_clk = { 242 .name = "uart0", 243 .parent = &pll0_sysclk2, 244 .lpsc = DA8XX_LPSC0_UART0, 245 }; 246 247 static struct clk uart1_clk = { 248 .name = "uart1", 249 .parent = &pll0_sysclk2, 250 .lpsc = DA8XX_LPSC1_UART1, 251 .gpsc = 1, 252 .flags = DA850_CLK_ASYNC3, 253 }; 254 255 static struct clk uart2_clk = { 256 .name = "uart2", 257 .parent = &pll0_sysclk2, 258 .lpsc = DA8XX_LPSC1_UART2, 259 .gpsc = 1, 260 .flags = DA850_CLK_ASYNC3, 261 }; 262 263 static struct clk aintc_clk = { 264 .name = "aintc", 265 .parent = &pll0_sysclk4, 266 .lpsc = DA8XX_LPSC0_AINTC, 267 .flags = ALWAYS_ENABLED, 268 }; 269 270 static struct clk gpio_clk = { 271 .name = "gpio", 272 .parent = &pll0_sysclk4, 273 .lpsc = DA8XX_LPSC1_GPIO, 274 .gpsc = 1, 275 }; 276 277 static struct clk i2c1_clk = { 278 .name = "i2c1", 279 .parent = &pll0_sysclk4, 280 .lpsc = DA8XX_LPSC1_I2C, 281 .gpsc = 1, 282 }; 283 284 static struct clk emif3_clk = { 285 .name = "emif3", 286 .parent = &pll0_sysclk5, 287 .lpsc = DA8XX_LPSC1_EMIF3C, 288 .gpsc = 1, 289 .flags = ALWAYS_ENABLED, 290 }; 291 292 static struct clk arm_clk = { 293 .name = "arm", 294 .parent = &pll0_sysclk6, 295 .lpsc = DA8XX_LPSC0_ARM, 296 .flags = ALWAYS_ENABLED, 297 .set_rate = da850_set_armrate, 298 .round_rate = da850_round_armrate, 299 }; 300 301 static struct clk rmii_clk = { 302 .name = "rmii", 303 .parent = &pll0_sysclk7, 304 }; 305 306 static struct clk emac_clk = { 307 .name = "emac", 308 .parent = &pll0_sysclk4, 309 .lpsc = DA8XX_LPSC1_CPGMAC, 310 .gpsc = 1, 311 }; 312 313 static struct clk mcasp_clk = { 314 .name = "mcasp", 315 .parent = &pll0_sysclk2, 316 .lpsc = DA8XX_LPSC1_McASP0, 317 .gpsc = 1, 318 .flags = DA850_CLK_ASYNC3, 319 }; 320 321 static struct clk lcdc_clk = { 322 .name = "lcdc", 323 .parent = &pll0_sysclk2, 324 .lpsc = DA8XX_LPSC1_LCDC, 325 .gpsc = 1, 326 }; 327 328 static struct clk mmcsd_clk = { 329 .name = "mmcsd", 330 .parent = &pll0_sysclk2, 331 .lpsc = DA8XX_LPSC0_MMC_SD, 332 }; 333 334 static struct clk aemif_clk = { 335 .name = "aemif", 336 .parent = &pll0_sysclk3, 337 .lpsc = DA8XX_LPSC0_EMIF25, 338 .flags = ALWAYS_ENABLED, 339 }; 340 341 static struct clk_lookup da850_clks[] = { 342 CLK(NULL, "ref", &ref_clk), 343 CLK(NULL, "pll0", &pll0_clk), 344 CLK(NULL, "pll0_aux", &pll0_aux_clk), 345 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), 346 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), 347 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), 348 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), 349 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), 350 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), 351 CLK(NULL, "pll1", &pll1_clk), 352 CLK(NULL, "pll1_aux", &pll1_aux_clk), 353 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), 354 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), 355 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), 356 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), 357 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6), 358 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), 359 CLK("i2c_davinci.1", NULL, &i2c0_clk), 360 CLK(NULL, "timer0", &timerp64_0_clk), 361 CLK("watchdog", NULL, &timerp64_1_clk), 362 CLK(NULL, "arm_rom", &arm_rom_clk), 363 CLK(NULL, "tpcc0", &tpcc0_clk), 364 CLK(NULL, "tptc0", &tptc0_clk), 365 CLK(NULL, "tptc1", &tptc1_clk), 366 CLK(NULL, "tpcc1", &tpcc1_clk), 367 CLK(NULL, "tptc2", &tptc2_clk), 368 CLK(NULL, "uart0", &uart0_clk), 369 CLK(NULL, "uart1", &uart1_clk), 370 CLK(NULL, "uart2", &uart2_clk), 371 CLK(NULL, "aintc", &aintc_clk), 372 CLK(NULL, "gpio", &gpio_clk), 373 CLK("i2c_davinci.2", NULL, &i2c1_clk), 374 CLK(NULL, "emif3", &emif3_clk), 375 CLK(NULL, "arm", &arm_clk), 376 CLK(NULL, "rmii", &rmii_clk), 377 CLK("davinci_emac.1", NULL, &emac_clk), 378 CLK("davinci-mcasp.0", NULL, &mcasp_clk), 379 CLK("da8xx_lcdc.0", NULL, &lcdc_clk), 380 CLK("davinci_mmc.0", NULL, &mmcsd_clk), 381 CLK(NULL, "aemif", &aemif_clk), 382 CLK(NULL, NULL, NULL), 383 }; 384 385 /* 386 * Device specific mux setup 387 * 388 * soc description mux mode mode mux dbg 389 * reg offset mask mode 390 */ 391 static const struct mux_config da850_pins[] = { 392 #ifdef CONFIG_DAVINCI_MUX 393 /* UART0 function */ 394 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false) 395 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false) 396 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false) 397 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false) 398 /* UART1 function */ 399 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false) 400 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false) 401 /* UART2 function */ 402 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false) 403 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false) 404 /* I2C1 function */ 405 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false) 406 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false) 407 /* I2C0 function */ 408 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) 409 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) 410 /* EMAC function */ 411 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false) 412 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false) 413 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false) 414 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false) 415 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false) 416 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false) 417 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false) 418 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false) 419 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false) 420 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false) 421 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false) 422 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false) 423 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false) 424 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false) 425 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) 426 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) 427 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) 428 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false) 429 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false) 430 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false) 431 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false) 432 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false) 433 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false) 434 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false) 435 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false) 436 /* McASP function */ 437 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false) 438 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false) 439 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false) 440 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false) 441 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false) 442 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false) 443 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false) 444 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false) 445 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false) 446 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false) 447 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false) 448 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false) 449 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false) 450 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false) 451 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false) 452 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false) 453 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false) 454 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false) 455 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false) 456 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false) 457 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false) 458 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false) 459 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false) 460 /* LCD function */ 461 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false) 462 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false) 463 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false) 464 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false) 465 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false) 466 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false) 467 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false) 468 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false) 469 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false) 470 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false) 471 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false) 472 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false) 473 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false) 474 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false) 475 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false) 476 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false) 477 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false) 478 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false) 479 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false) 480 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false) 481 /* MMC/SD0 function */ 482 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false) 483 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false) 484 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false) 485 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false) 486 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false) 487 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false) 488 /* EMIF2.5/EMIFA function */ 489 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false) 490 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false) 491 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false) 492 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false) 493 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false) 494 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false) 495 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false) 496 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false) 497 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false) 498 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false) 499 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false) 500 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false) 501 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false) 502 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false) 503 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false) 504 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false) 505 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false) 506 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false) 507 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false) 508 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false) 509 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false) 510 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false) 511 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false) 512 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false) 513 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false) 514 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false) 515 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false) 516 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false) 517 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false) 518 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false) 519 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false) 520 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false) 521 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false) 522 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false) 523 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false) 524 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false) 525 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false) 526 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false) 527 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false) 528 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false) 529 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false) 530 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false) 531 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false) 532 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false) 533 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false) 534 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false) 535 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false) 536 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false) 537 /* GPIO function */ 538 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false) 539 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false) 540 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) 541 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) 542 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) 543 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false) 544 #endif 545 }; 546 547 const short da850_uart0_pins[] __initdata = { 548 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD, 549 -1 550 }; 551 552 const short da850_uart1_pins[] __initdata = { 553 DA850_UART1_RXD, DA850_UART1_TXD, 554 -1 555 }; 556 557 const short da850_uart2_pins[] __initdata = { 558 DA850_UART2_RXD, DA850_UART2_TXD, 559 -1 560 }; 561 562 const short da850_i2c0_pins[] __initdata = { 563 DA850_I2C0_SDA, DA850_I2C0_SCL, 564 -1 565 }; 566 567 const short da850_i2c1_pins[] __initdata = { 568 DA850_I2C1_SCL, DA850_I2C1_SDA, 569 -1 570 }; 571 572 const short da850_cpgmac_pins[] __initdata = { 573 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, 574 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, 575 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, 576 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, 577 DA850_MDIO_D, 578 -1 579 }; 580 581 const short da850_rmii_pins[] __initdata = { 582 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, 583 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, 584 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, 585 DA850_MDIO_D, 586 -1 587 }; 588 589 const short da850_mcasp_pins[] __initdata = { 590 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, 591 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE, 592 DA850_AXR_11, DA850_AXR_12, 593 -1 594 }; 595 596 const short da850_lcdcntl_pins[] __initdata = { 597 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, 598 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, 599 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, 600 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, 601 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, 602 -1 603 }; 604 605 const short da850_mmcsd0_pins[] __initdata = { 606 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2, 607 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD, 608 DA850_GPIO4_0, DA850_GPIO4_1, 609 -1 610 }; 611 612 const short da850_emif25_pins[] __initdata = { 613 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2, 614 DA850_NEMA_CS_3, DA850_NEMA_CS_4, DA850_NEMA_WE, DA850_NEMA_OE, 615 DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, 616 DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7, 617 DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11, 618 DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15, 619 DA850_EMA_A_0, DA850_EMA_A_1, DA850_EMA_A_2, DA850_EMA_A_3, 620 DA850_EMA_A_4, DA850_EMA_A_5, DA850_EMA_A_6, DA850_EMA_A_7, 621 DA850_EMA_A_8, DA850_EMA_A_9, DA850_EMA_A_10, DA850_EMA_A_11, 622 DA850_EMA_A_12, DA850_EMA_A_13, DA850_EMA_A_14, DA850_EMA_A_15, 623 DA850_EMA_A_16, DA850_EMA_A_17, DA850_EMA_A_18, DA850_EMA_A_19, 624 DA850_EMA_A_20, DA850_EMA_A_21, DA850_EMA_A_22, DA850_EMA_A_23, 625 -1 626 }; 627 628 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ 629 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { 630 [IRQ_DA8XX_COMMTX] = 7, 631 [IRQ_DA8XX_COMMRX] = 7, 632 [IRQ_DA8XX_NINT] = 7, 633 [IRQ_DA8XX_EVTOUT0] = 7, 634 [IRQ_DA8XX_EVTOUT1] = 7, 635 [IRQ_DA8XX_EVTOUT2] = 7, 636 [IRQ_DA8XX_EVTOUT3] = 7, 637 [IRQ_DA8XX_EVTOUT4] = 7, 638 [IRQ_DA8XX_EVTOUT5] = 7, 639 [IRQ_DA8XX_EVTOUT6] = 7, 640 [IRQ_DA8XX_EVTOUT7] = 7, 641 [IRQ_DA8XX_CCINT0] = 7, 642 [IRQ_DA8XX_CCERRINT] = 7, 643 [IRQ_DA8XX_TCERRINT0] = 7, 644 [IRQ_DA8XX_AEMIFINT] = 7, 645 [IRQ_DA8XX_I2CINT0] = 7, 646 [IRQ_DA8XX_MMCSDINT0] = 7, 647 [IRQ_DA8XX_MMCSDINT1] = 7, 648 [IRQ_DA8XX_ALLINT0] = 7, 649 [IRQ_DA8XX_RTC] = 7, 650 [IRQ_DA8XX_SPINT0] = 7, 651 [IRQ_DA8XX_TINT12_0] = 7, 652 [IRQ_DA8XX_TINT34_0] = 7, 653 [IRQ_DA8XX_TINT12_1] = 7, 654 [IRQ_DA8XX_TINT34_1] = 7, 655 [IRQ_DA8XX_UARTINT0] = 7, 656 [IRQ_DA8XX_KEYMGRINT] = 7, 657 [IRQ_DA850_MPUADDRERR0] = 7, 658 [IRQ_DA8XX_CHIPINT0] = 7, 659 [IRQ_DA8XX_CHIPINT1] = 7, 660 [IRQ_DA8XX_CHIPINT2] = 7, 661 [IRQ_DA8XX_CHIPINT3] = 7, 662 [IRQ_DA8XX_TCERRINT1] = 7, 663 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, 664 [IRQ_DA8XX_C0_RX_PULSE] = 7, 665 [IRQ_DA8XX_C0_TX_PULSE] = 7, 666 [IRQ_DA8XX_C0_MISC_PULSE] = 7, 667 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, 668 [IRQ_DA8XX_C1_RX_PULSE] = 7, 669 [IRQ_DA8XX_C1_TX_PULSE] = 7, 670 [IRQ_DA8XX_C1_MISC_PULSE] = 7, 671 [IRQ_DA8XX_MEMERR] = 7, 672 [IRQ_DA8XX_GPIO0] = 7, 673 [IRQ_DA8XX_GPIO1] = 7, 674 [IRQ_DA8XX_GPIO2] = 7, 675 [IRQ_DA8XX_GPIO3] = 7, 676 [IRQ_DA8XX_GPIO4] = 7, 677 [IRQ_DA8XX_GPIO5] = 7, 678 [IRQ_DA8XX_GPIO6] = 7, 679 [IRQ_DA8XX_GPIO7] = 7, 680 [IRQ_DA8XX_GPIO8] = 7, 681 [IRQ_DA8XX_I2CINT1] = 7, 682 [IRQ_DA8XX_LCDINT] = 7, 683 [IRQ_DA8XX_UARTINT1] = 7, 684 [IRQ_DA8XX_MCASPINT] = 7, 685 [IRQ_DA8XX_ALLINT1] = 7, 686 [IRQ_DA8XX_SPINT1] = 7, 687 [IRQ_DA8XX_UHPI_INT1] = 7, 688 [IRQ_DA8XX_USB_INT] = 7, 689 [IRQ_DA8XX_IRQN] = 7, 690 [IRQ_DA8XX_RWAKEUP] = 7, 691 [IRQ_DA8XX_UARTINT2] = 7, 692 [IRQ_DA8XX_DFTSSINT] = 7, 693 [IRQ_DA8XX_EHRPWM0] = 7, 694 [IRQ_DA8XX_EHRPWM0TZ] = 7, 695 [IRQ_DA8XX_EHRPWM1] = 7, 696 [IRQ_DA8XX_EHRPWM1TZ] = 7, 697 [IRQ_DA850_SATAINT] = 7, 698 [IRQ_DA850_TINTALL_2] = 7, 699 [IRQ_DA8XX_ECAP0] = 7, 700 [IRQ_DA8XX_ECAP1] = 7, 701 [IRQ_DA8XX_ECAP2] = 7, 702 [IRQ_DA850_MMCSDINT0_1] = 7, 703 [IRQ_DA850_MMCSDINT1_1] = 7, 704 [IRQ_DA850_T12CMPINT0_2] = 7, 705 [IRQ_DA850_T12CMPINT1_2] = 7, 706 [IRQ_DA850_T12CMPINT2_2] = 7, 707 [IRQ_DA850_T12CMPINT3_2] = 7, 708 [IRQ_DA850_T12CMPINT4_2] = 7, 709 [IRQ_DA850_T12CMPINT5_2] = 7, 710 [IRQ_DA850_T12CMPINT6_2] = 7, 711 [IRQ_DA850_T12CMPINT7_2] = 7, 712 [IRQ_DA850_T12CMPINT0_3] = 7, 713 [IRQ_DA850_T12CMPINT1_3] = 7, 714 [IRQ_DA850_T12CMPINT2_3] = 7, 715 [IRQ_DA850_T12CMPINT3_3] = 7, 716 [IRQ_DA850_T12CMPINT4_3] = 7, 717 [IRQ_DA850_T12CMPINT5_3] = 7, 718 [IRQ_DA850_T12CMPINT6_3] = 7, 719 [IRQ_DA850_T12CMPINT7_3] = 7, 720 [IRQ_DA850_RPIINT] = 7, 721 [IRQ_DA850_VPIFINT] = 7, 722 [IRQ_DA850_CCINT1] = 7, 723 [IRQ_DA850_CCERRINT1] = 7, 724 [IRQ_DA850_TCERRINT2] = 7, 725 [IRQ_DA850_TINTALL_3] = 7, 726 [IRQ_DA850_MCBSP0RINT] = 7, 727 [IRQ_DA850_MCBSP0XINT] = 7, 728 [IRQ_DA850_MCBSP1RINT] = 7, 729 [IRQ_DA850_MCBSP1XINT] = 7, 730 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, 731 }; 732 733 static struct map_desc da850_io_desc[] = { 734 { 735 .virtual = IO_VIRT, 736 .pfn = __phys_to_pfn(IO_PHYS), 737 .length = IO_SIZE, 738 .type = MT_DEVICE 739 }, 740 { 741 .virtual = DA8XX_CP_INTC_VIRT, 742 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), 743 .length = DA8XX_CP_INTC_SIZE, 744 .type = MT_DEVICE 745 }, 746 { 747 .virtual = SRAM_VIRT, 748 .pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE), 749 .length = SZ_8K, 750 .type = MT_DEVICE 751 }, 752 }; 753 754 static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE }; 755 756 /* Contents of JTAG ID register used to identify exact cpu type */ 757 static struct davinci_id da850_ids[] = { 758 { 759 .variant = 0x0, 760 .part_no = 0xb7d1, 761 .manufacturer = 0x017, /* 0x02f >> 1 */ 762 .cpu_id = DAVINCI_CPU_ID_DA850, 763 .name = "da850/omap-l138", 764 }, 765 }; 766 767 static struct davinci_timer_instance da850_timer_instance[4] = { 768 { 769 .base = DA8XX_TIMER64P0_BASE, 770 .bottom_irq = IRQ_DA8XX_TINT12_0, 771 .top_irq = IRQ_DA8XX_TINT34_0, 772 }, 773 { 774 .base = DA8XX_TIMER64P1_BASE, 775 .bottom_irq = IRQ_DA8XX_TINT12_1, 776 .top_irq = IRQ_DA8XX_TINT34_1, 777 }, 778 { 779 .base = DA850_TIMER64P2_BASE, 780 .bottom_irq = IRQ_DA850_TINT12_2, 781 .top_irq = IRQ_DA850_TINT34_2, 782 }, 783 { 784 .base = DA850_TIMER64P3_BASE, 785 .bottom_irq = IRQ_DA850_TINT12_3, 786 .top_irq = IRQ_DA850_TINT34_3, 787 }, 788 }; 789 790 /* 791 * T0_BOT: Timer 0, bottom : Used for clock_event 792 * T0_TOP: Timer 0, top : Used for clocksource 793 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer 794 */ 795 static struct davinci_timer_info da850_timer_info = { 796 .timers = da850_timer_instance, 797 .clockevent_id = T0_BOT, 798 .clocksource_id = T0_TOP, 799 }; 800 801 static void da850_set_async3_src(int pllnum) 802 { 803 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2; 804 struct clk_lookup *c; 805 unsigned int v; 806 int ret; 807 808 for (c = da850_clks; c->clk; c++) { 809 clk = c->clk; 810 if (clk->flags & DA850_CLK_ASYNC3) { 811 ret = clk_set_parent(clk, newparent); 812 WARN(ret, "DA850: unable to re-parent clock %s", 813 clk->name); 814 } 815 } 816 817 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); 818 if (pllnum) 819 v |= CFGCHIP3_ASYNC3_CLKSRC; 820 else 821 v &= ~CFGCHIP3_ASYNC3_CLKSRC; 822 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); 823 } 824 825 #ifdef CONFIG_CPU_FREQ 826 /* 827 * Notes: 828 * According to the TRM, minimum PLLM results in maximum power savings. 829 * The OPP definitions below should keep the PLLM as low as possible. 830 * 831 * The output of the PLLM must be between 400 to 600 MHz. 832 * This rules out prediv of anything but divide-by-one for 24Mhz OSC input. 833 */ 834 struct da850_opp { 835 unsigned int freq; /* in KHz */ 836 unsigned int prediv; 837 unsigned int mult; 838 unsigned int postdiv; 839 unsigned int cvdd_min; /* in uV */ 840 unsigned int cvdd_max; /* in uV */ 841 }; 842 843 static const struct da850_opp da850_opp_300 = { 844 .freq = 300000, 845 .prediv = 1, 846 .mult = 25, 847 .postdiv = 2, 848 .cvdd_min = 1200000, 849 .cvdd_max = 1320000, 850 }; 851 852 static const struct da850_opp da850_opp_200 = { 853 .freq = 200000, 854 .prediv = 1, 855 .mult = 25, 856 .postdiv = 3, 857 .cvdd_min = 1100000, 858 .cvdd_max = 1160000, 859 }; 860 861 static const struct da850_opp da850_opp_96 = { 862 .freq = 96000, 863 .prediv = 1, 864 .mult = 20, 865 .postdiv = 5, 866 .cvdd_min = 1000000, 867 .cvdd_max = 1050000, 868 }; 869 870 #define OPP(freq) \ 871 { \ 872 .index = (unsigned int) &da850_opp_##freq, \ 873 .frequency = freq * 1000, \ 874 } 875 876 static struct cpufreq_frequency_table da850_freq_table[] = { 877 OPP(300), 878 OPP(200), 879 OPP(96), 880 { 881 .index = 0, 882 .frequency = CPUFREQ_TABLE_END, 883 }, 884 }; 885 886 #ifdef CONFIG_REGULATOR 887 static struct regulator *cvdd; 888 889 static int da850_set_voltage(unsigned int index) 890 { 891 struct da850_opp *opp; 892 893 if (!cvdd) 894 return -ENODEV; 895 896 opp = (struct da850_opp *) da850_freq_table[index].index; 897 898 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); 899 } 900 901 static int da850_regulator_init(void) 902 { 903 cvdd = regulator_get(NULL, "cvdd"); 904 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;" 905 " voltage scaling unsupported\n")) { 906 return PTR_ERR(cvdd); 907 } 908 909 return 0; 910 } 911 #endif 912 913 static struct davinci_cpufreq_config cpufreq_info = { 914 .freq_table = &da850_freq_table[0], 915 #ifdef CONFIG_REGULATOR 916 .init = da850_regulator_init, 917 .set_voltage = da850_set_voltage, 918 #endif 919 }; 920 921 static struct platform_device da850_cpufreq_device = { 922 .name = "cpufreq-davinci", 923 .dev = { 924 .platform_data = &cpufreq_info, 925 }, 926 .id = -1, 927 }; 928 929 int __init da850_register_cpufreq(char *async_clk) 930 { 931 /* cpufreq driver can help keep an "async" clock constant */ 932 if (async_clk) 933 clk_add_alias("async", da850_cpufreq_device.name, 934 async_clk, NULL); 935 936 return platform_device_register(&da850_cpufreq_device); 937 } 938 939 static int da850_round_armrate(struct clk *clk, unsigned long rate) 940 { 941 int i, ret = 0, diff; 942 unsigned int best = (unsigned int) -1; 943 944 rate /= 1000; /* convert to kHz */ 945 946 for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { 947 diff = da850_freq_table[i].frequency - rate; 948 if (diff < 0) 949 diff = -diff; 950 951 if (diff < best) { 952 best = diff; 953 ret = da850_freq_table[i].frequency; 954 } 955 } 956 957 return ret * 1000; 958 } 959 960 static int da850_set_armrate(struct clk *clk, unsigned long index) 961 { 962 struct clk *pllclk = &pll0_clk; 963 964 return clk_set_rate(pllclk, index); 965 } 966 967 static int da850_set_pll0rate(struct clk *clk, unsigned long index) 968 { 969 unsigned int prediv, mult, postdiv; 970 struct da850_opp *opp; 971 struct pll_data *pll = clk->pll_data; 972 int ret; 973 974 opp = (struct da850_opp *) da850_freq_table[index].index; 975 prediv = opp->prediv; 976 mult = opp->mult; 977 postdiv = opp->postdiv; 978 979 ret = davinci_set_pllrate(pll, prediv, mult, postdiv); 980 if (WARN_ON(ret)) 981 return ret; 982 983 return 0; 984 } 985 #else 986 int __init da850_register_cpufreq(char *async_clk) 987 { 988 return 0; 989 } 990 991 static int da850_set_armrate(struct clk *clk, unsigned long rate) 992 { 993 return -EINVAL; 994 } 995 996 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate) 997 { 998 return -EINVAL; 999 } 1000 1001 static int da850_round_armrate(struct clk *clk, unsigned long rate) 1002 { 1003 return clk->rate; 1004 } 1005 #endif 1006 1007 int da850_register_pm(struct platform_device *pdev) 1008 { 1009 int ret; 1010 struct davinci_pm_config *pdata = pdev->dev.platform_data; 1011 1012 ret = davinci_cfg_reg(DA850_RTC_ALARM); 1013 if (ret) 1014 return ret; 1015 1016 pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr(); 1017 pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG); 1018 pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C; 1019 1020 pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K); 1021 if (!pdata->cpupll_reg_base) 1022 return -ENOMEM; 1023 1024 pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K); 1025 if (!pdata->ddrpll_reg_base) { 1026 ret = -ENOMEM; 1027 goto no_ddrpll_mem; 1028 } 1029 1030 pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K); 1031 if (!pdata->ddrpsc_reg_base) { 1032 ret = -ENOMEM; 1033 goto no_ddrpsc_mem; 1034 } 1035 1036 return platform_device_register(pdev); 1037 1038 no_ddrpsc_mem: 1039 iounmap(pdata->ddrpll_reg_base); 1040 no_ddrpll_mem: 1041 iounmap(pdata->cpupll_reg_base); 1042 return ret; 1043 } 1044 1045 static struct davinci_soc_info davinci_soc_info_da850 = { 1046 .io_desc = da850_io_desc, 1047 .io_desc_num = ARRAY_SIZE(da850_io_desc), 1048 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, 1049 .ids = da850_ids, 1050 .ids_num = ARRAY_SIZE(da850_ids), 1051 .cpu_clks = da850_clks, 1052 .psc_bases = da850_psc_bases, 1053 .psc_bases_num = ARRAY_SIZE(da850_psc_bases), 1054 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, 1055 .pinmux_pins = da850_pins, 1056 .pinmux_pins_num = ARRAY_SIZE(da850_pins), 1057 .intc_base = DA8XX_CP_INTC_BASE, 1058 .intc_type = DAVINCI_INTC_TYPE_CP_INTC, 1059 .intc_irq_prios = da850_default_priorities, 1060 .intc_irq_num = DA850_N_CP_INTC_IRQ, 1061 .timer_info = &da850_timer_info, 1062 .gpio_type = GPIO_TYPE_DAVINCI, 1063 .gpio_base = DA8XX_GPIO_BASE, 1064 .gpio_num = 144, 1065 .gpio_irq = IRQ_DA8XX_GPIO0, 1066 .serial_dev = &da8xx_serial_device, 1067 .emac_pdata = &da8xx_emac_pdata, 1068 .sram_dma = DA8XX_ARM_RAM_BASE, 1069 .sram_len = SZ_8K, 1070 .reset_device = &da8xx_wdt_device, 1071 }; 1072 1073 void __init da850_init(void) 1074 { 1075 unsigned int v; 1076 1077 davinci_common_init(&davinci_soc_info_da850); 1078 1079 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); 1080 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module")) 1081 return; 1082 1083 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K); 1084 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module")) 1085 return; 1086 1087 /* 1088 * Move the clock source of Async3 domain to PLL1 SYSCLK2. 1089 * This helps keeping the peripherals on this domain insulated 1090 * from CPU frequency changes caused by DVFS. The firmware sets 1091 * both PLL0 and PLL1 to the same frequency so, there should not 1092 * be any noticible change even in non-DVFS use cases. 1093 */ 1094 da850_set_async3_src(1); 1095 1096 /* Unlock writing to PLL0 registers */ 1097 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG)); 1098 v &= ~CFGCHIP0_PLL_MASTER_LOCK; 1099 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG)); 1100 1101 /* Unlock writing to PLL1 registers */ 1102 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); 1103 v &= ~CFGCHIP3_PLL1_MASTER_LOCK; 1104 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); 1105 } 1106