xref: /openbmc/linux/arch/arm/mach-davinci/da850.c (revision de2bdb3d)
1 /*
2  * TI DA850/OMAP-L138 chip specific setup
3  *
4  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5  *
6  * Derived from: arch/arm/mach-davinci/da830.c
7  * Original Copyrights follow:
8  *
9  * 2009 (c) MontaVista Software, Inc. This file is licensed under
10  * the terms of the GNU General Public License version 2. This program
11  * is licensed "as is" without any warranty of any kind, whether express
12  * or implied.
13  */
14 #include <linux/clkdev.h>
15 #include <linux/gpio.h>
16 #include <linux/init.h>
17 #include <linux/clk.h>
18 #include <linux/platform_device.h>
19 #include <linux/cpufreq.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/platform_data/gpio-davinci.h>
22 
23 #include <asm/mach/map.h>
24 
25 #include "psc.h"
26 #include <mach/irqs.h>
27 #include <mach/cputype.h>
28 #include <mach/common.h>
29 #include <mach/time.h>
30 #include <mach/da8xx.h>
31 #include <mach/cpufreq.h>
32 #include <mach/pm.h>
33 
34 #include "clock.h"
35 #include "mux.h"
36 
37 #define DA850_PLL1_BASE		0x01e1a000
38 #define DA850_TIMER64P2_BASE	0x01f0c000
39 #define DA850_TIMER64P3_BASE	0x01f0d000
40 
41 #define DA850_REF_FREQ		24000000
42 
43 #define CFGCHIP3_ASYNC3_CLKSRC	BIT(4)
44 #define CFGCHIP3_PLL1_MASTER_LOCK	BIT(5)
45 #define CFGCHIP0_PLL_MASTER_LOCK	BIT(4)
46 
47 static int da850_set_armrate(struct clk *clk, unsigned long rate);
48 static int da850_round_armrate(struct clk *clk, unsigned long rate);
49 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
50 
51 static struct pll_data pll0_data = {
52 	.num		= 1,
53 	.phys_base	= DA8XX_PLL0_BASE,
54 	.flags		= PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
55 };
56 
57 static struct clk ref_clk = {
58 	.name		= "ref_clk",
59 	.rate		= DA850_REF_FREQ,
60 	.set_rate	= davinci_simple_set_rate,
61 };
62 
63 static struct clk pll0_clk = {
64 	.name		= "pll0",
65 	.parent		= &ref_clk,
66 	.pll_data	= &pll0_data,
67 	.flags		= CLK_PLL,
68 	.set_rate	= da850_set_pll0rate,
69 };
70 
71 static struct clk pll0_aux_clk = {
72 	.name		= "pll0_aux_clk",
73 	.parent		= &pll0_clk,
74 	.flags		= CLK_PLL | PRE_PLL,
75 };
76 
77 static struct clk pll0_sysclk1 = {
78 	.name		= "pll0_sysclk1",
79 	.parent		= &pll0_clk,
80 	.flags		= CLK_PLL,
81 	.div_reg	= PLLDIV1,
82 };
83 
84 static struct clk pll0_sysclk2 = {
85 	.name		= "pll0_sysclk2",
86 	.parent		= &pll0_clk,
87 	.flags		= CLK_PLL,
88 	.div_reg	= PLLDIV2,
89 };
90 
91 static struct clk pll0_sysclk3 = {
92 	.name		= "pll0_sysclk3",
93 	.parent		= &pll0_clk,
94 	.flags		= CLK_PLL,
95 	.div_reg	= PLLDIV3,
96 	.set_rate	= davinci_set_sysclk_rate,
97 	.maxrate	= 100000000,
98 };
99 
100 static struct clk pll0_sysclk4 = {
101 	.name		= "pll0_sysclk4",
102 	.parent		= &pll0_clk,
103 	.flags		= CLK_PLL,
104 	.div_reg	= PLLDIV4,
105 };
106 
107 static struct clk pll0_sysclk5 = {
108 	.name		= "pll0_sysclk5",
109 	.parent		= &pll0_clk,
110 	.flags		= CLK_PLL,
111 	.div_reg	= PLLDIV5,
112 };
113 
114 static struct clk pll0_sysclk6 = {
115 	.name		= "pll0_sysclk6",
116 	.parent		= &pll0_clk,
117 	.flags		= CLK_PLL,
118 	.div_reg	= PLLDIV6,
119 };
120 
121 static struct clk pll0_sysclk7 = {
122 	.name		= "pll0_sysclk7",
123 	.parent		= &pll0_clk,
124 	.flags		= CLK_PLL,
125 	.div_reg	= PLLDIV7,
126 };
127 
128 static struct pll_data pll1_data = {
129 	.num		= 2,
130 	.phys_base	= DA850_PLL1_BASE,
131 	.flags		= PLL_HAS_POSTDIV,
132 };
133 
134 static struct clk pll1_clk = {
135 	.name		= "pll1",
136 	.parent		= &ref_clk,
137 	.pll_data	= &pll1_data,
138 	.flags		= CLK_PLL,
139 };
140 
141 static struct clk pll1_aux_clk = {
142 	.name		= "pll1_aux_clk",
143 	.parent		= &pll1_clk,
144 	.flags		= CLK_PLL | PRE_PLL,
145 };
146 
147 static struct clk pll1_sysclk2 = {
148 	.name		= "pll1_sysclk2",
149 	.parent		= &pll1_clk,
150 	.flags		= CLK_PLL,
151 	.div_reg	= PLLDIV2,
152 };
153 
154 static struct clk pll1_sysclk3 = {
155 	.name		= "pll1_sysclk3",
156 	.parent		= &pll1_clk,
157 	.flags		= CLK_PLL,
158 	.div_reg	= PLLDIV3,
159 };
160 
161 static int da850_async3_set_parent(struct clk *clk, struct clk *parent)
162 {
163 	u32 val;
164 
165 	val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
166 
167 	if (parent == &pll0_sysclk2) {
168 		val &= ~CFGCHIP3_ASYNC3_CLKSRC;
169 	} else if (parent == &pll1_sysclk2) {
170 		val |= CFGCHIP3_ASYNC3_CLKSRC;
171 	} else {
172 		pr_err("Bad parent on async3 clock mux\n");
173 		return -EINVAL;
174 	}
175 
176 	writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
177 
178 	return 0;
179 }
180 
181 static struct clk async3_clk = {
182 	.name		= "async3",
183 	.parent		= &pll1_sysclk2,
184 	.set_parent	= da850_async3_set_parent,
185 };
186 
187 static struct clk i2c0_clk = {
188 	.name		= "i2c0",
189 	.parent		= &pll0_aux_clk,
190 };
191 
192 static struct clk timerp64_0_clk = {
193 	.name		= "timer0",
194 	.parent		= &pll0_aux_clk,
195 };
196 
197 static struct clk timerp64_1_clk = {
198 	.name		= "timer1",
199 	.parent		= &pll0_aux_clk,
200 };
201 
202 static struct clk arm_rom_clk = {
203 	.name		= "arm_rom",
204 	.parent		= &pll0_sysclk2,
205 	.lpsc		= DA8XX_LPSC0_ARM_RAM_ROM,
206 	.flags		= ALWAYS_ENABLED,
207 };
208 
209 static struct clk tpcc0_clk = {
210 	.name		= "tpcc0",
211 	.parent		= &pll0_sysclk2,
212 	.lpsc		= DA8XX_LPSC0_TPCC,
213 	.flags		= ALWAYS_ENABLED | CLK_PSC,
214 };
215 
216 static struct clk tptc0_clk = {
217 	.name		= "tptc0",
218 	.parent		= &pll0_sysclk2,
219 	.lpsc		= DA8XX_LPSC0_TPTC0,
220 	.flags		= ALWAYS_ENABLED,
221 };
222 
223 static struct clk tptc1_clk = {
224 	.name		= "tptc1",
225 	.parent		= &pll0_sysclk2,
226 	.lpsc		= DA8XX_LPSC0_TPTC1,
227 	.flags		= ALWAYS_ENABLED,
228 };
229 
230 static struct clk tpcc1_clk = {
231 	.name		= "tpcc1",
232 	.parent		= &pll0_sysclk2,
233 	.lpsc		= DA850_LPSC1_TPCC1,
234 	.gpsc		= 1,
235 	.flags		= CLK_PSC | ALWAYS_ENABLED,
236 };
237 
238 static struct clk tptc2_clk = {
239 	.name		= "tptc2",
240 	.parent		= &pll0_sysclk2,
241 	.lpsc		= DA850_LPSC1_TPTC2,
242 	.gpsc		= 1,
243 	.flags		= ALWAYS_ENABLED,
244 };
245 
246 static struct clk pruss_clk = {
247 	.name		= "pruss",
248 	.parent		= &pll0_sysclk2,
249 	.lpsc		= DA8XX_LPSC0_PRUSS,
250 };
251 
252 static struct clk uart0_clk = {
253 	.name		= "uart0",
254 	.parent		= &pll0_sysclk2,
255 	.lpsc		= DA8XX_LPSC0_UART0,
256 };
257 
258 static struct clk uart1_clk = {
259 	.name		= "uart1",
260 	.parent		= &async3_clk,
261 	.lpsc		= DA8XX_LPSC1_UART1,
262 	.gpsc		= 1,
263 };
264 
265 static struct clk uart2_clk = {
266 	.name		= "uart2",
267 	.parent		= &async3_clk,
268 	.lpsc		= DA8XX_LPSC1_UART2,
269 	.gpsc		= 1,
270 };
271 
272 static struct clk aintc_clk = {
273 	.name		= "aintc",
274 	.parent		= &pll0_sysclk4,
275 	.lpsc		= DA8XX_LPSC0_AINTC,
276 	.flags		= ALWAYS_ENABLED,
277 };
278 
279 static struct clk gpio_clk = {
280 	.name		= "gpio",
281 	.parent		= &pll0_sysclk4,
282 	.lpsc		= DA8XX_LPSC1_GPIO,
283 	.gpsc		= 1,
284 };
285 
286 static struct clk i2c1_clk = {
287 	.name		= "i2c1",
288 	.parent		= &pll0_sysclk4,
289 	.lpsc		= DA8XX_LPSC1_I2C,
290 	.gpsc		= 1,
291 };
292 
293 static struct clk emif3_clk = {
294 	.name		= "emif3",
295 	.parent		= &pll0_sysclk5,
296 	.lpsc		= DA8XX_LPSC1_EMIF3C,
297 	.gpsc		= 1,
298 	.flags		= ALWAYS_ENABLED,
299 };
300 
301 static struct clk arm_clk = {
302 	.name		= "arm",
303 	.parent		= &pll0_sysclk6,
304 	.lpsc		= DA8XX_LPSC0_ARM,
305 	.flags		= ALWAYS_ENABLED,
306 	.set_rate	= da850_set_armrate,
307 	.round_rate	= da850_round_armrate,
308 };
309 
310 static struct clk rmii_clk = {
311 	.name		= "rmii",
312 	.parent		= &pll0_sysclk7,
313 };
314 
315 static struct clk emac_clk = {
316 	.name		= "emac",
317 	.parent		= &pll0_sysclk4,
318 	.lpsc		= DA8XX_LPSC1_CPGMAC,
319 	.gpsc		= 1,
320 };
321 
322 static struct clk mcasp_clk = {
323 	.name		= "mcasp",
324 	.parent		= &async3_clk,
325 	.lpsc		= DA8XX_LPSC1_McASP0,
326 	.gpsc		= 1,
327 };
328 
329 static struct clk mcbsp0_clk = {
330 	.name		= "mcbsp0",
331 	.parent		= &async3_clk,
332 	.lpsc		= DA850_LPSC1_McBSP0,
333 	.gpsc		= 1,
334 };
335 
336 static struct clk mcbsp1_clk = {
337 	.name		= "mcbsp1",
338 	.parent		= &async3_clk,
339 	.lpsc		= DA850_LPSC1_McBSP1,
340 	.gpsc		= 1,
341 };
342 
343 static struct clk lcdc_clk = {
344 	.name		= "lcdc",
345 	.parent		= &pll0_sysclk2,
346 	.lpsc		= DA8XX_LPSC1_LCDC,
347 	.gpsc		= 1,
348 };
349 
350 static struct clk mmcsd0_clk = {
351 	.name		= "mmcsd0",
352 	.parent		= &pll0_sysclk2,
353 	.lpsc		= DA8XX_LPSC0_MMC_SD,
354 };
355 
356 static struct clk mmcsd1_clk = {
357 	.name		= "mmcsd1",
358 	.parent		= &pll0_sysclk2,
359 	.lpsc		= DA850_LPSC1_MMC_SD1,
360 	.gpsc		= 1,
361 };
362 
363 static struct clk aemif_clk = {
364 	.name		= "aemif",
365 	.parent		= &pll0_sysclk3,
366 	.lpsc		= DA8XX_LPSC0_EMIF25,
367 	.flags		= ALWAYS_ENABLED,
368 };
369 
370 static struct clk usb11_clk = {
371 	.name		= "usb11",
372 	.parent		= &pll0_sysclk4,
373 	.lpsc		= DA8XX_LPSC1_USB11,
374 	.gpsc		= 1,
375 };
376 
377 static struct clk usb20_clk = {
378 	.name		= "usb20",
379 	.parent		= &pll0_sysclk2,
380 	.lpsc		= DA8XX_LPSC1_USB20,
381 	.gpsc		= 1,
382 };
383 
384 static struct clk spi0_clk = {
385 	.name		= "spi0",
386 	.parent		= &pll0_sysclk2,
387 	.lpsc		= DA8XX_LPSC0_SPI0,
388 };
389 
390 static struct clk spi1_clk = {
391 	.name		= "spi1",
392 	.parent		= &async3_clk,
393 	.lpsc		= DA8XX_LPSC1_SPI1,
394 	.gpsc		= 1,
395 };
396 
397 static struct clk vpif_clk = {
398 	.name		= "vpif",
399 	.parent		= &pll0_sysclk2,
400 	.lpsc		= DA850_LPSC1_VPIF,
401 	.gpsc		= 1,
402 };
403 
404 static struct clk sata_clk = {
405 	.name		= "sata",
406 	.parent		= &pll0_sysclk2,
407 	.lpsc		= DA850_LPSC1_SATA,
408 	.gpsc		= 1,
409 	.flags		= PSC_FORCE,
410 };
411 
412 static struct clk dsp_clk = {
413 	.name		= "dsp",
414 	.parent		= &pll0_sysclk1,
415 	.domain		= DAVINCI_GPSC_DSPDOMAIN,
416 	.lpsc		= DA8XX_LPSC0_GEM,
417 	.flags		= PSC_LRST | PSC_FORCE,
418 };
419 
420 static struct clk ehrpwm_clk = {
421 	.name		= "ehrpwm",
422 	.parent		= &async3_clk,
423 	.lpsc		= DA8XX_LPSC1_PWM,
424 	.gpsc		= 1,
425 };
426 
427 #define DA8XX_EHRPWM_TBCLKSYNC	BIT(12)
428 
429 static void ehrpwm_tblck_enable(struct clk *clk)
430 {
431 	u32 val;
432 
433 	val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
434 	val |= DA8XX_EHRPWM_TBCLKSYNC;
435 	writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
436 }
437 
438 static void ehrpwm_tblck_disable(struct clk *clk)
439 {
440 	u32 val;
441 
442 	val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
443 	val &= ~DA8XX_EHRPWM_TBCLKSYNC;
444 	writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
445 }
446 
447 static struct clk ehrpwm_tbclk = {
448 	.name		= "ehrpwm_tbclk",
449 	.parent		= &ehrpwm_clk,
450 	.clk_enable	= ehrpwm_tblck_enable,
451 	.clk_disable	= ehrpwm_tblck_disable,
452 };
453 
454 static struct clk ecap_clk = {
455 	.name		= "ecap",
456 	.parent		= &async3_clk,
457 	.lpsc		= DA8XX_LPSC1_ECAP,
458 	.gpsc		= 1,
459 };
460 
461 static struct clk_lookup da850_clks[] = {
462 	CLK(NULL,		"ref",		&ref_clk),
463 	CLK(NULL,		"pll0",		&pll0_clk),
464 	CLK(NULL,		"pll0_aux",	&pll0_aux_clk),
465 	CLK(NULL,		"pll0_sysclk1",	&pll0_sysclk1),
466 	CLK(NULL,		"pll0_sysclk2",	&pll0_sysclk2),
467 	CLK(NULL,		"pll0_sysclk3",	&pll0_sysclk3),
468 	CLK(NULL,		"pll0_sysclk4",	&pll0_sysclk4),
469 	CLK(NULL,		"pll0_sysclk5",	&pll0_sysclk5),
470 	CLK(NULL,		"pll0_sysclk6",	&pll0_sysclk6),
471 	CLK(NULL,		"pll0_sysclk7",	&pll0_sysclk7),
472 	CLK(NULL,		"pll1",		&pll1_clk),
473 	CLK(NULL,		"pll1_aux",	&pll1_aux_clk),
474 	CLK(NULL,		"pll1_sysclk2",	&pll1_sysclk2),
475 	CLK(NULL,		"pll1_sysclk3",	&pll1_sysclk3),
476 	CLK(NULL,		"async3",	&async3_clk),
477 	CLK("i2c_davinci.1",	NULL,		&i2c0_clk),
478 	CLK(NULL,		"timer0",	&timerp64_0_clk),
479 	CLK("davinci-wdt",	NULL,		&timerp64_1_clk),
480 	CLK(NULL,		"arm_rom",	&arm_rom_clk),
481 	CLK(NULL,		"tpcc0",	&tpcc0_clk),
482 	CLK(NULL,		"tptc0",	&tptc0_clk),
483 	CLK(NULL,		"tptc1",	&tptc1_clk),
484 	CLK(NULL,		"tpcc1",	&tpcc1_clk),
485 	CLK(NULL,		"tptc2",	&tptc2_clk),
486 	CLK("pruss_uio",	"pruss",	&pruss_clk),
487 	CLK("serial8250.0",	NULL,		&uart0_clk),
488 	CLK("serial8250.1",	NULL,		&uart1_clk),
489 	CLK("serial8250.2",	NULL,		&uart2_clk),
490 	CLK(NULL,		"aintc",	&aintc_clk),
491 	CLK(NULL,		"gpio",		&gpio_clk),
492 	CLK("i2c_davinci.2",	NULL,		&i2c1_clk),
493 	CLK(NULL,		"emif3",	&emif3_clk),
494 	CLK(NULL,		"arm",		&arm_clk),
495 	CLK(NULL,		"rmii",		&rmii_clk),
496 	CLK("davinci_emac.1",	NULL,		&emac_clk),
497 	CLK("davinci_mdio.0",	"fck",		&emac_clk),
498 	CLK("davinci-mcasp.0",	NULL,		&mcasp_clk),
499 	CLK("davinci-mcbsp.0",	NULL,		&mcbsp0_clk),
500 	CLK("davinci-mcbsp.1",	NULL,		&mcbsp1_clk),
501 	CLK("da8xx_lcdc.0",	"fck",		&lcdc_clk),
502 	CLK("da830-mmc.0",	NULL,		&mmcsd0_clk),
503 	CLK("da830-mmc.1",	NULL,		&mmcsd1_clk),
504 	CLK("ti-aemif",		NULL,		&aemif_clk),
505 	CLK(NULL,		"aemif",	&aemif_clk),
506 	CLK(NULL,		"usb11",	&usb11_clk),
507 	CLK(NULL,		"usb20",	&usb20_clk),
508 	CLK("spi_davinci.0",	NULL,		&spi0_clk),
509 	CLK("spi_davinci.1",	NULL,		&spi1_clk),
510 	CLK("vpif",		NULL,		&vpif_clk),
511 	CLK("ahci_da850",		NULL,		&sata_clk),
512 	CLK("davinci-rproc.0",	NULL,		&dsp_clk),
513 	CLK("ehrpwm",		"fck",		&ehrpwm_clk),
514 	CLK("ehrpwm",		"tbclk",	&ehrpwm_tbclk),
515 	CLK("ecap",		"fck",		&ecap_clk),
516 	CLK(NULL,		NULL,		NULL),
517 };
518 
519 /*
520  * Device specific mux setup
521  *
522  *		soc	description	mux	mode	mode	mux	dbg
523  *					reg	offset	mask	mode
524  */
525 static const struct mux_config da850_pins[] = {
526 #ifdef CONFIG_DAVINCI_MUX
527 	/* UART0 function */
528 	MUX_CFG(DA850, NUART0_CTS,	3,	24,	15,	2,	false)
529 	MUX_CFG(DA850, NUART0_RTS,	3,	28,	15,	2,	false)
530 	MUX_CFG(DA850, UART0_RXD,	3,	16,	15,	2,	false)
531 	MUX_CFG(DA850, UART0_TXD,	3,	20,	15,	2,	false)
532 	/* UART1 function */
533 	MUX_CFG(DA850, UART1_RXD,	4,	24,	15,	2,	false)
534 	MUX_CFG(DA850, UART1_TXD,	4,	28,	15,	2,	false)
535 	/* UART2 function */
536 	MUX_CFG(DA850, UART2_RXD,	4,	16,	15,	2,	false)
537 	MUX_CFG(DA850, UART2_TXD,	4,	20,	15,	2,	false)
538 	/* I2C1 function */
539 	MUX_CFG(DA850, I2C1_SCL,	4,	16,	15,	4,	false)
540 	MUX_CFG(DA850, I2C1_SDA,	4,	20,	15,	4,	false)
541 	/* I2C0 function */
542 	MUX_CFG(DA850, I2C0_SDA,	4,	12,	15,	2,	false)
543 	MUX_CFG(DA850, I2C0_SCL,	4,	8,	15,	2,	false)
544 	/* EMAC function */
545 	MUX_CFG(DA850, MII_TXEN,	2,	4,	15,	8,	false)
546 	MUX_CFG(DA850, MII_TXCLK,	2,	8,	15,	8,	false)
547 	MUX_CFG(DA850, MII_COL,		2,	12,	15,	8,	false)
548 	MUX_CFG(DA850, MII_TXD_3,	2,	16,	15,	8,	false)
549 	MUX_CFG(DA850, MII_TXD_2,	2,	20,	15,	8,	false)
550 	MUX_CFG(DA850, MII_TXD_1,	2,	24,	15,	8,	false)
551 	MUX_CFG(DA850, MII_TXD_0,	2,	28,	15,	8,	false)
552 	MUX_CFG(DA850, MII_RXCLK,	3,	0,	15,	8,	false)
553 	MUX_CFG(DA850, MII_RXDV,	3,	4,	15,	8,	false)
554 	MUX_CFG(DA850, MII_RXER,	3,	8,	15,	8,	false)
555 	MUX_CFG(DA850, MII_CRS,		3,	12,	15,	8,	false)
556 	MUX_CFG(DA850, MII_RXD_3,	3,	16,	15,	8,	false)
557 	MUX_CFG(DA850, MII_RXD_2,	3,	20,	15,	8,	false)
558 	MUX_CFG(DA850, MII_RXD_1,	3,	24,	15,	8,	false)
559 	MUX_CFG(DA850, MII_RXD_0,	3,	28,	15,	8,	false)
560 	MUX_CFG(DA850, MDIO_CLK,	4,	0,	15,	8,	false)
561 	MUX_CFG(DA850, MDIO_D,		4,	4,	15,	8,	false)
562 	MUX_CFG(DA850, RMII_TXD_0,	14,	12,	15,	8,	false)
563 	MUX_CFG(DA850, RMII_TXD_1,	14,	8,	15,	8,	false)
564 	MUX_CFG(DA850, RMII_TXEN,	14,	16,	15,	8,	false)
565 	MUX_CFG(DA850, RMII_CRS_DV,	15,	4,	15,	8,	false)
566 	MUX_CFG(DA850, RMII_RXD_0,	14,	24,	15,	8,	false)
567 	MUX_CFG(DA850, RMII_RXD_1,	14,	20,	15,	8,	false)
568 	MUX_CFG(DA850, RMII_RXER,	14,	28,	15,	8,	false)
569 	MUX_CFG(DA850, RMII_MHZ_50_CLK,	15,	0,	15,	0,	false)
570 	/* McASP function */
571 	MUX_CFG(DA850,	ACLKR,		0,	0,	15,	1,	false)
572 	MUX_CFG(DA850,	ACLKX,		0,	4,	15,	1,	false)
573 	MUX_CFG(DA850,	AFSR,		0,	8,	15,	1,	false)
574 	MUX_CFG(DA850,	AFSX,		0,	12,	15,	1,	false)
575 	MUX_CFG(DA850,	AHCLKR,		0,	16,	15,	1,	false)
576 	MUX_CFG(DA850,	AHCLKX,		0,	20,	15,	1,	false)
577 	MUX_CFG(DA850,	AMUTE,		0,	24,	15,	1,	false)
578 	MUX_CFG(DA850,	AXR_15,		1,	0,	15,	1,	false)
579 	MUX_CFG(DA850,	AXR_14,		1,	4,	15,	1,	false)
580 	MUX_CFG(DA850,	AXR_13,		1,	8,	15,	1,	false)
581 	MUX_CFG(DA850,	AXR_12,		1,	12,	15,	1,	false)
582 	MUX_CFG(DA850,	AXR_11,		1,	16,	15,	1,	false)
583 	MUX_CFG(DA850,	AXR_10,		1,	20,	15,	1,	false)
584 	MUX_CFG(DA850,	AXR_9,		1,	24,	15,	1,	false)
585 	MUX_CFG(DA850,	AXR_8,		1,	28,	15,	1,	false)
586 	MUX_CFG(DA850,	AXR_7,		2,	0,	15,	1,	false)
587 	MUX_CFG(DA850,	AXR_6,		2,	4,	15,	1,	false)
588 	MUX_CFG(DA850,	AXR_5,		2,	8,	15,	1,	false)
589 	MUX_CFG(DA850,	AXR_4,		2,	12,	15,	1,	false)
590 	MUX_CFG(DA850,	AXR_3,		2,	16,	15,	1,	false)
591 	MUX_CFG(DA850,	AXR_2,		2,	20,	15,	1,	false)
592 	MUX_CFG(DA850,	AXR_1,		2,	24,	15,	1,	false)
593 	MUX_CFG(DA850,	AXR_0,		2,	28,	15,	1,	false)
594 	/* LCD function */
595 	MUX_CFG(DA850, LCD_D_7,		16,	8,	15,	2,	false)
596 	MUX_CFG(DA850, LCD_D_6,		16,	12,	15,	2,	false)
597 	MUX_CFG(DA850, LCD_D_5,		16,	16,	15,	2,	false)
598 	MUX_CFG(DA850, LCD_D_4,		16,	20,	15,	2,	false)
599 	MUX_CFG(DA850, LCD_D_3,		16,	24,	15,	2,	false)
600 	MUX_CFG(DA850, LCD_D_2,		16,	28,	15,	2,	false)
601 	MUX_CFG(DA850, LCD_D_1,		17,	0,	15,	2,	false)
602 	MUX_CFG(DA850, LCD_D_0,		17,	4,	15,	2,	false)
603 	MUX_CFG(DA850, LCD_D_15,	17,	8,	15,	2,	false)
604 	MUX_CFG(DA850, LCD_D_14,	17,	12,	15,	2,	false)
605 	MUX_CFG(DA850, LCD_D_13,	17,	16,	15,	2,	false)
606 	MUX_CFG(DA850, LCD_D_12,	17,	20,	15,	2,	false)
607 	MUX_CFG(DA850, LCD_D_11,	17,	24,	15,	2,	false)
608 	MUX_CFG(DA850, LCD_D_10,	17,	28,	15,	2,	false)
609 	MUX_CFG(DA850, LCD_D_9,		18,	0,	15,	2,	false)
610 	MUX_CFG(DA850, LCD_D_8,		18,	4,	15,	2,	false)
611 	MUX_CFG(DA850, LCD_PCLK,	18,	24,	15,	2,	false)
612 	MUX_CFG(DA850, LCD_HSYNC,	19,	0,	15,	2,	false)
613 	MUX_CFG(DA850, LCD_VSYNC,	19,	4,	15,	2,	false)
614 	MUX_CFG(DA850, NLCD_AC_ENB_CS,	19,	24,	15,	2,	false)
615 	/* MMC/SD0 function */
616 	MUX_CFG(DA850, MMCSD0_DAT_0,	10,	8,	15,	2,	false)
617 	MUX_CFG(DA850, MMCSD0_DAT_1,	10,	12,	15,	2,	false)
618 	MUX_CFG(DA850, MMCSD0_DAT_2,	10,	16,	15,	2,	false)
619 	MUX_CFG(DA850, MMCSD0_DAT_3,	10,	20,	15,	2,	false)
620 	MUX_CFG(DA850, MMCSD0_CLK,	10,	0,	15,	2,	false)
621 	MUX_CFG(DA850, MMCSD0_CMD,	10,	4,	15,	2,	false)
622 	/* MMC/SD1 function */
623 	MUX_CFG(DA850, MMCSD1_DAT_0,	18,	8,	15,	2,	false)
624 	MUX_CFG(DA850, MMCSD1_DAT_1,	19,	16,	15,	2,	false)
625 	MUX_CFG(DA850, MMCSD1_DAT_2,	19,	12,	15,	2,	false)
626 	MUX_CFG(DA850, MMCSD1_DAT_3,	19,	8,	15,	2,	false)
627 	MUX_CFG(DA850, MMCSD1_CLK,	18,	12,	15,	2,	false)
628 	MUX_CFG(DA850, MMCSD1_CMD,	18,	16,	15,	2,	false)
629 	/* EMIF2.5/EMIFA function */
630 	MUX_CFG(DA850, EMA_D_7,		9,	0,	15,	1,	false)
631 	MUX_CFG(DA850, EMA_D_6,		9,	4,	15,	1,	false)
632 	MUX_CFG(DA850, EMA_D_5,		9,	8,	15,	1,	false)
633 	MUX_CFG(DA850, EMA_D_4,		9,	12,	15,	1,	false)
634 	MUX_CFG(DA850, EMA_D_3,		9,	16,	15,	1,	false)
635 	MUX_CFG(DA850, EMA_D_2,		9,	20,	15,	1,	false)
636 	MUX_CFG(DA850, EMA_D_1,		9,	24,	15,	1,	false)
637 	MUX_CFG(DA850, EMA_D_0,		9,	28,	15,	1,	false)
638 	MUX_CFG(DA850, EMA_A_1,		12,	24,	15,	1,	false)
639 	MUX_CFG(DA850, EMA_A_2,		12,	20,	15,	1,	false)
640 	MUX_CFG(DA850, NEMA_CS_3,	7,	4,	15,	1,	false)
641 	MUX_CFG(DA850, NEMA_CS_4,	7,	8,	15,	1,	false)
642 	MUX_CFG(DA850, NEMA_WE,		7,	16,	15,	1,	false)
643 	MUX_CFG(DA850, NEMA_OE,		7,	20,	15,	1,	false)
644 	MUX_CFG(DA850, EMA_A_0,		12,	28,	15,	1,	false)
645 	MUX_CFG(DA850, EMA_A_3,		12,	16,	15,	1,	false)
646 	MUX_CFG(DA850, EMA_A_4,		12,	12,	15,	1,	false)
647 	MUX_CFG(DA850, EMA_A_5,		12,	8,	15,	1,	false)
648 	MUX_CFG(DA850, EMA_A_6,		12,	4,	15,	1,	false)
649 	MUX_CFG(DA850, EMA_A_7,		12,	0,	15,	1,	false)
650 	MUX_CFG(DA850, EMA_A_8,		11,	28,	15,	1,	false)
651 	MUX_CFG(DA850, EMA_A_9,		11,	24,	15,	1,	false)
652 	MUX_CFG(DA850, EMA_A_10,	11,	20,	15,	1,	false)
653 	MUX_CFG(DA850, EMA_A_11,	11,	16,	15,	1,	false)
654 	MUX_CFG(DA850, EMA_A_12,	11,	12,	15,	1,	false)
655 	MUX_CFG(DA850, EMA_A_13,	11,	8,	15,	1,	false)
656 	MUX_CFG(DA850, EMA_A_14,	11,	4,	15,	1,	false)
657 	MUX_CFG(DA850, EMA_A_15,	11,	0,	15,	1,	false)
658 	MUX_CFG(DA850, EMA_A_16,	10,	28,	15,	1,	false)
659 	MUX_CFG(DA850, EMA_A_17,	10,	24,	15,	1,	false)
660 	MUX_CFG(DA850, EMA_A_18,	10,	20,	15,	1,	false)
661 	MUX_CFG(DA850, EMA_A_19,	10,	16,	15,	1,	false)
662 	MUX_CFG(DA850, EMA_A_20,	10,	12,	15,	1,	false)
663 	MUX_CFG(DA850, EMA_A_21,	10,	8,	15,	1,	false)
664 	MUX_CFG(DA850, EMA_A_22,	10,	4,	15,	1,	false)
665 	MUX_CFG(DA850, EMA_A_23,	10,	0,	15,	1,	false)
666 	MUX_CFG(DA850, EMA_D_8,		8,	28,	15,	1,	false)
667 	MUX_CFG(DA850, EMA_D_9,		8,	24,	15,	1,	false)
668 	MUX_CFG(DA850, EMA_D_10,	8,	20,	15,	1,	false)
669 	MUX_CFG(DA850, EMA_D_11,	8,	16,	15,	1,	false)
670 	MUX_CFG(DA850, EMA_D_12,	8,	12,	15,	1,	false)
671 	MUX_CFG(DA850, EMA_D_13,	8,	8,	15,	1,	false)
672 	MUX_CFG(DA850, EMA_D_14,	8,	4,	15,	1,	false)
673 	MUX_CFG(DA850, EMA_D_15,	8,	0,	15,	1,	false)
674 	MUX_CFG(DA850, EMA_BA_1,	5,	24,	15,	1,	false)
675 	MUX_CFG(DA850, EMA_CLK,		6,	0,	15,	1,	false)
676 	MUX_CFG(DA850, EMA_WAIT_1,	6,	24,	15,	1,	false)
677 	MUX_CFG(DA850, NEMA_CS_2,	7,	0,	15,	1,	false)
678 	/* GPIO function */
679 	MUX_CFG(DA850, GPIO2_4,		6,	12,	15,	8,	false)
680 	MUX_CFG(DA850, GPIO2_6,		6,	4,	15,	8,	false)
681 	MUX_CFG(DA850, GPIO2_8,		5,	28,	15,	8,	false)
682 	MUX_CFG(DA850, GPIO2_15,	5,	0,	15,	8,	false)
683 	MUX_CFG(DA850, GPIO3_12,	7,	12,	15,	8,	false)
684 	MUX_CFG(DA850, GPIO3_13,	7,	8,	15,	8,	false)
685 	MUX_CFG(DA850, GPIO4_0,		10,	28,	15,	8,	false)
686 	MUX_CFG(DA850, GPIO4_1,		10,	24,	15,	8,	false)
687 	MUX_CFG(DA850, GPIO6_9,		13,	24,	15,	8,	false)
688 	MUX_CFG(DA850, GPIO6_10,	13,	20,	15,	8,	false)
689 	MUX_CFG(DA850, GPIO6_13,	13,	8,	15,	8,	false)
690 	MUX_CFG(DA850, RTC_ALARM,	0,	28,	15,	2,	false)
691 	/* VPIF Capture */
692 	MUX_CFG(DA850, VPIF_DIN0,	15,	4,	15,	1,	false)
693 	MUX_CFG(DA850, VPIF_DIN1,	15,	0,	15,	1,	false)
694 	MUX_CFG(DA850, VPIF_DIN2,	14,	28,	15,	1,	false)
695 	MUX_CFG(DA850, VPIF_DIN3,	14,	24,	15,	1,	false)
696 	MUX_CFG(DA850, VPIF_DIN4,	14,	20,	15,	1,	false)
697 	MUX_CFG(DA850, VPIF_DIN5,	14,	16,	15,	1,	false)
698 	MUX_CFG(DA850, VPIF_DIN6,	14,	12,	15,	1,	false)
699 	MUX_CFG(DA850, VPIF_DIN7,	14,	8,	15,	1,	false)
700 	MUX_CFG(DA850, VPIF_DIN8,	16,	4,	15,	1,	false)
701 	MUX_CFG(DA850, VPIF_DIN9,	16,	0,	15,	1,	false)
702 	MUX_CFG(DA850, VPIF_DIN10,	15,	28,	15,	1,	false)
703 	MUX_CFG(DA850, VPIF_DIN11,	15,	24,	15,	1,	false)
704 	MUX_CFG(DA850, VPIF_DIN12,	15,	20,	15,	1,	false)
705 	MUX_CFG(DA850, VPIF_DIN13,	15,	16,	15,	1,	false)
706 	MUX_CFG(DA850, VPIF_DIN14,	15,	12,	15,	1,	false)
707 	MUX_CFG(DA850, VPIF_DIN15,	15,	8,	15,	1,	false)
708 	MUX_CFG(DA850, VPIF_CLKIN0,	14,	0,	15,	1,	false)
709 	MUX_CFG(DA850, VPIF_CLKIN1,	14,	4,	15,	1,	false)
710 	MUX_CFG(DA850, VPIF_CLKIN2,	19,	8,	15,	1,	false)
711 	MUX_CFG(DA850, VPIF_CLKIN3,	19,	16,	15,	1,	false)
712 	/* VPIF Display */
713 	MUX_CFG(DA850, VPIF_DOUT0,	17,	4,	15,	1,	false)
714 	MUX_CFG(DA850, VPIF_DOUT1,	17,	0,	15,	1,	false)
715 	MUX_CFG(DA850, VPIF_DOUT2,	16,	28,	15,	1,	false)
716 	MUX_CFG(DA850, VPIF_DOUT3,	16,	24,	15,	1,	false)
717 	MUX_CFG(DA850, VPIF_DOUT4,	16,	20,	15,	1,	false)
718 	MUX_CFG(DA850, VPIF_DOUT5,	16,	16,	15,	1,	false)
719 	MUX_CFG(DA850, VPIF_DOUT6,	16,	12,	15,	1,	false)
720 	MUX_CFG(DA850, VPIF_DOUT7,	16,	8,	15,	1,	false)
721 	MUX_CFG(DA850, VPIF_DOUT8,	18,	4,	15,	1,	false)
722 	MUX_CFG(DA850, VPIF_DOUT9,	18,	0,	15,	1,	false)
723 	MUX_CFG(DA850, VPIF_DOUT10,	17,	28,	15,	1,	false)
724 	MUX_CFG(DA850, VPIF_DOUT11,	17,	24,	15,	1,	false)
725 	MUX_CFG(DA850, VPIF_DOUT12,	17,	20,	15,	1,	false)
726 	MUX_CFG(DA850, VPIF_DOUT13,	17,	16,	15,	1,	false)
727 	MUX_CFG(DA850, VPIF_DOUT14,	17,	12,	15,	1,	false)
728 	MUX_CFG(DA850, VPIF_DOUT15,	17,	8,	15,	1,	false)
729 	MUX_CFG(DA850, VPIF_CLKO2,	19,	12,	15,	1,	false)
730 	MUX_CFG(DA850, VPIF_CLKO3,	19,	20,	15,	1,	false)
731 #endif
732 };
733 
734 const short da850_i2c0_pins[] __initconst = {
735 	DA850_I2C0_SDA, DA850_I2C0_SCL,
736 	-1
737 };
738 
739 const short da850_i2c1_pins[] __initconst = {
740 	DA850_I2C1_SCL, DA850_I2C1_SDA,
741 	-1
742 };
743 
744 const short da850_lcdcntl_pins[] __initconst = {
745 	DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
746 	DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
747 	DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
748 	DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
749 	DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
750 	-1
751 };
752 
753 const short da850_vpif_capture_pins[] __initconst = {
754 	DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
755 	DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
756 	DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
757 	DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
758 	DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
759 	DA850_VPIF_CLKIN3,
760 	-1
761 };
762 
763 const short da850_vpif_display_pins[] __initconst = {
764 	DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
765 	DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
766 	DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
767 	DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
768 	DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
769 	DA850_VPIF_CLKO3,
770 	-1
771 };
772 
773 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
774 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
775 	[IRQ_DA8XX_COMMTX]		= 7,
776 	[IRQ_DA8XX_COMMRX]		= 7,
777 	[IRQ_DA8XX_NINT]		= 7,
778 	[IRQ_DA8XX_EVTOUT0]		= 7,
779 	[IRQ_DA8XX_EVTOUT1]		= 7,
780 	[IRQ_DA8XX_EVTOUT2]		= 7,
781 	[IRQ_DA8XX_EVTOUT3]		= 7,
782 	[IRQ_DA8XX_EVTOUT4]		= 7,
783 	[IRQ_DA8XX_EVTOUT5]		= 7,
784 	[IRQ_DA8XX_EVTOUT6]		= 7,
785 	[IRQ_DA8XX_EVTOUT7]		= 7,
786 	[IRQ_DA8XX_CCINT0]		= 7,
787 	[IRQ_DA8XX_CCERRINT]		= 7,
788 	[IRQ_DA8XX_TCERRINT0]		= 7,
789 	[IRQ_DA8XX_AEMIFINT]		= 7,
790 	[IRQ_DA8XX_I2CINT0]		= 7,
791 	[IRQ_DA8XX_MMCSDINT0]		= 7,
792 	[IRQ_DA8XX_MMCSDINT1]		= 7,
793 	[IRQ_DA8XX_ALLINT0]		= 7,
794 	[IRQ_DA8XX_RTC]			= 7,
795 	[IRQ_DA8XX_SPINT0]		= 7,
796 	[IRQ_DA8XX_TINT12_0]		= 7,
797 	[IRQ_DA8XX_TINT34_0]		= 7,
798 	[IRQ_DA8XX_TINT12_1]		= 7,
799 	[IRQ_DA8XX_TINT34_1]		= 7,
800 	[IRQ_DA8XX_UARTINT0]		= 7,
801 	[IRQ_DA8XX_KEYMGRINT]		= 7,
802 	[IRQ_DA850_MPUADDRERR0]		= 7,
803 	[IRQ_DA8XX_CHIPINT0]		= 7,
804 	[IRQ_DA8XX_CHIPINT1]		= 7,
805 	[IRQ_DA8XX_CHIPINT2]		= 7,
806 	[IRQ_DA8XX_CHIPINT3]		= 7,
807 	[IRQ_DA8XX_TCERRINT1]		= 7,
808 	[IRQ_DA8XX_C0_RX_THRESH_PULSE]	= 7,
809 	[IRQ_DA8XX_C0_RX_PULSE]		= 7,
810 	[IRQ_DA8XX_C0_TX_PULSE]		= 7,
811 	[IRQ_DA8XX_C0_MISC_PULSE]	= 7,
812 	[IRQ_DA8XX_C1_RX_THRESH_PULSE]	= 7,
813 	[IRQ_DA8XX_C1_RX_PULSE]		= 7,
814 	[IRQ_DA8XX_C1_TX_PULSE]		= 7,
815 	[IRQ_DA8XX_C1_MISC_PULSE]	= 7,
816 	[IRQ_DA8XX_MEMERR]		= 7,
817 	[IRQ_DA8XX_GPIO0]		= 7,
818 	[IRQ_DA8XX_GPIO1]		= 7,
819 	[IRQ_DA8XX_GPIO2]		= 7,
820 	[IRQ_DA8XX_GPIO3]		= 7,
821 	[IRQ_DA8XX_GPIO4]		= 7,
822 	[IRQ_DA8XX_GPIO5]		= 7,
823 	[IRQ_DA8XX_GPIO6]		= 7,
824 	[IRQ_DA8XX_GPIO7]		= 7,
825 	[IRQ_DA8XX_GPIO8]		= 7,
826 	[IRQ_DA8XX_I2CINT1]		= 7,
827 	[IRQ_DA8XX_LCDINT]		= 7,
828 	[IRQ_DA8XX_UARTINT1]		= 7,
829 	[IRQ_DA8XX_MCASPINT]		= 7,
830 	[IRQ_DA8XX_ALLINT1]		= 7,
831 	[IRQ_DA8XX_SPINT1]		= 7,
832 	[IRQ_DA8XX_UHPI_INT1]		= 7,
833 	[IRQ_DA8XX_USB_INT]		= 7,
834 	[IRQ_DA8XX_IRQN]		= 7,
835 	[IRQ_DA8XX_RWAKEUP]		= 7,
836 	[IRQ_DA8XX_UARTINT2]		= 7,
837 	[IRQ_DA8XX_DFTSSINT]		= 7,
838 	[IRQ_DA8XX_EHRPWM0]		= 7,
839 	[IRQ_DA8XX_EHRPWM0TZ]		= 7,
840 	[IRQ_DA8XX_EHRPWM1]		= 7,
841 	[IRQ_DA8XX_EHRPWM1TZ]		= 7,
842 	[IRQ_DA850_SATAINT]		= 7,
843 	[IRQ_DA850_TINTALL_2]		= 7,
844 	[IRQ_DA8XX_ECAP0]		= 7,
845 	[IRQ_DA8XX_ECAP1]		= 7,
846 	[IRQ_DA8XX_ECAP2]		= 7,
847 	[IRQ_DA850_MMCSDINT0_1]		= 7,
848 	[IRQ_DA850_MMCSDINT1_1]		= 7,
849 	[IRQ_DA850_T12CMPINT0_2]	= 7,
850 	[IRQ_DA850_T12CMPINT1_2]	= 7,
851 	[IRQ_DA850_T12CMPINT2_2]	= 7,
852 	[IRQ_DA850_T12CMPINT3_2]	= 7,
853 	[IRQ_DA850_T12CMPINT4_2]	= 7,
854 	[IRQ_DA850_T12CMPINT5_2]	= 7,
855 	[IRQ_DA850_T12CMPINT6_2]	= 7,
856 	[IRQ_DA850_T12CMPINT7_2]	= 7,
857 	[IRQ_DA850_T12CMPINT0_3]	= 7,
858 	[IRQ_DA850_T12CMPINT1_3]	= 7,
859 	[IRQ_DA850_T12CMPINT2_3]	= 7,
860 	[IRQ_DA850_T12CMPINT3_3]	= 7,
861 	[IRQ_DA850_T12CMPINT4_3]	= 7,
862 	[IRQ_DA850_T12CMPINT5_3]	= 7,
863 	[IRQ_DA850_T12CMPINT6_3]	= 7,
864 	[IRQ_DA850_T12CMPINT7_3]	= 7,
865 	[IRQ_DA850_RPIINT]		= 7,
866 	[IRQ_DA850_VPIFINT]		= 7,
867 	[IRQ_DA850_CCINT1]		= 7,
868 	[IRQ_DA850_CCERRINT1]		= 7,
869 	[IRQ_DA850_TCERRINT2]		= 7,
870 	[IRQ_DA850_TINTALL_3]		= 7,
871 	[IRQ_DA850_MCBSP0RINT]		= 7,
872 	[IRQ_DA850_MCBSP0XINT]		= 7,
873 	[IRQ_DA850_MCBSP1RINT]		= 7,
874 	[IRQ_DA850_MCBSP1XINT]		= 7,
875 	[IRQ_DA8XX_ARMCLKSTOPREQ]	= 7,
876 };
877 
878 static struct map_desc da850_io_desc[] = {
879 	{
880 		.virtual	= IO_VIRT,
881 		.pfn		= __phys_to_pfn(IO_PHYS),
882 		.length		= IO_SIZE,
883 		.type		= MT_DEVICE
884 	},
885 	{
886 		.virtual	= DA8XX_CP_INTC_VIRT,
887 		.pfn		= __phys_to_pfn(DA8XX_CP_INTC_BASE),
888 		.length		= DA8XX_CP_INTC_SIZE,
889 		.type		= MT_DEVICE
890 	},
891 };
892 
893 static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
894 
895 /* Contents of JTAG ID register used to identify exact cpu type */
896 static struct davinci_id da850_ids[] = {
897 	{
898 		.variant	= 0x0,
899 		.part_no	= 0xb7d1,
900 		.manufacturer	= 0x017,	/* 0x02f >> 1 */
901 		.cpu_id		= DAVINCI_CPU_ID_DA850,
902 		.name		= "da850/omap-l138",
903 	},
904 	{
905 		.variant	= 0x1,
906 		.part_no	= 0xb7d1,
907 		.manufacturer	= 0x017,	/* 0x02f >> 1 */
908 		.cpu_id		= DAVINCI_CPU_ID_DA850,
909 		.name		= "da850/omap-l138/am18x",
910 	},
911 };
912 
913 static struct davinci_timer_instance da850_timer_instance[4] = {
914 	{
915 		.base		= DA8XX_TIMER64P0_BASE,
916 		.bottom_irq	= IRQ_DA8XX_TINT12_0,
917 		.top_irq	= IRQ_DA8XX_TINT34_0,
918 	},
919 	{
920 		.base		= DA8XX_TIMER64P1_BASE,
921 		.bottom_irq	= IRQ_DA8XX_TINT12_1,
922 		.top_irq	= IRQ_DA8XX_TINT34_1,
923 	},
924 	{
925 		.base		= DA850_TIMER64P2_BASE,
926 		.bottom_irq	= IRQ_DA850_TINT12_2,
927 		.top_irq	= IRQ_DA850_TINT34_2,
928 	},
929 	{
930 		.base		= DA850_TIMER64P3_BASE,
931 		.bottom_irq	= IRQ_DA850_TINT12_3,
932 		.top_irq	= IRQ_DA850_TINT34_3,
933 	},
934 };
935 
936 /*
937  * T0_BOT: Timer 0, bottom		: Used for clock_event
938  * T0_TOP: Timer 0, top			: Used for clocksource
939  * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
940  */
941 static struct davinci_timer_info da850_timer_info = {
942 	.timers		= da850_timer_instance,
943 	.clockevent_id	= T0_BOT,
944 	.clocksource_id	= T0_TOP,
945 };
946 
947 #ifdef CONFIG_CPU_FREQ
948 /*
949  * Notes:
950  * According to the TRM, minimum PLLM results in maximum power savings.
951  * The OPP definitions below should keep the PLLM as low as possible.
952  *
953  * The output of the PLLM must be between 300 to 600 MHz.
954  */
955 struct da850_opp {
956 	unsigned int	freq;	/* in KHz */
957 	unsigned int	prediv;
958 	unsigned int	mult;
959 	unsigned int	postdiv;
960 	unsigned int	cvdd_min; /* in uV */
961 	unsigned int	cvdd_max; /* in uV */
962 };
963 
964 static const struct da850_opp da850_opp_456 = {
965 	.freq		= 456000,
966 	.prediv		= 1,
967 	.mult		= 19,
968 	.postdiv	= 1,
969 	.cvdd_min	= 1300000,
970 	.cvdd_max	= 1350000,
971 };
972 
973 static const struct da850_opp da850_opp_408 = {
974 	.freq		= 408000,
975 	.prediv		= 1,
976 	.mult		= 17,
977 	.postdiv	= 1,
978 	.cvdd_min	= 1300000,
979 	.cvdd_max	= 1350000,
980 };
981 
982 static const struct da850_opp da850_opp_372 = {
983 	.freq		= 372000,
984 	.prediv		= 2,
985 	.mult		= 31,
986 	.postdiv	= 1,
987 	.cvdd_min	= 1200000,
988 	.cvdd_max	= 1320000,
989 };
990 
991 static const struct da850_opp da850_opp_300 = {
992 	.freq		= 300000,
993 	.prediv		= 1,
994 	.mult		= 25,
995 	.postdiv	= 2,
996 	.cvdd_min	= 1200000,
997 	.cvdd_max	= 1320000,
998 };
999 
1000 static const struct da850_opp da850_opp_200 = {
1001 	.freq		= 200000,
1002 	.prediv		= 1,
1003 	.mult		= 25,
1004 	.postdiv	= 3,
1005 	.cvdd_min	= 1100000,
1006 	.cvdd_max	= 1160000,
1007 };
1008 
1009 static const struct da850_opp da850_opp_96 = {
1010 	.freq		= 96000,
1011 	.prediv		= 1,
1012 	.mult		= 20,
1013 	.postdiv	= 5,
1014 	.cvdd_min	= 1000000,
1015 	.cvdd_max	= 1050000,
1016 };
1017 
1018 #define OPP(freq) 		\
1019 	{				\
1020 		.driver_data = (unsigned int) &da850_opp_##freq,	\
1021 		.frequency = freq * 1000, \
1022 	}
1023 
1024 static struct cpufreq_frequency_table da850_freq_table[] = {
1025 	OPP(456),
1026 	OPP(408),
1027 	OPP(372),
1028 	OPP(300),
1029 	OPP(200),
1030 	OPP(96),
1031 	{
1032 		.driver_data		= 0,
1033 		.frequency	= CPUFREQ_TABLE_END,
1034 	},
1035 };
1036 
1037 #ifdef CONFIG_REGULATOR
1038 static int da850_set_voltage(unsigned int index);
1039 static int da850_regulator_init(void);
1040 #endif
1041 
1042 static struct davinci_cpufreq_config cpufreq_info = {
1043 	.freq_table = da850_freq_table,
1044 #ifdef CONFIG_REGULATOR
1045 	.init = da850_regulator_init,
1046 	.set_voltage = da850_set_voltage,
1047 #endif
1048 };
1049 
1050 #ifdef CONFIG_REGULATOR
1051 static struct regulator *cvdd;
1052 
1053 static int da850_set_voltage(unsigned int index)
1054 {
1055 	struct da850_opp *opp;
1056 
1057 	if (!cvdd)
1058 		return -ENODEV;
1059 
1060 	opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
1061 
1062 	return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
1063 }
1064 
1065 static int da850_regulator_init(void)
1066 {
1067 	cvdd = regulator_get(NULL, "cvdd");
1068 	if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
1069 					" voltage scaling unsupported\n")) {
1070 		return PTR_ERR(cvdd);
1071 	}
1072 
1073 	return 0;
1074 }
1075 #endif
1076 
1077 static struct platform_device da850_cpufreq_device = {
1078 	.name			= "cpufreq-davinci",
1079 	.dev = {
1080 		.platform_data	= &cpufreq_info,
1081 	},
1082 	.id = -1,
1083 };
1084 
1085 unsigned int da850_max_speed = 300000;
1086 
1087 int da850_register_cpufreq(char *async_clk)
1088 {
1089 	int i;
1090 
1091 	/* cpufreq driver can help keep an "async" clock constant */
1092 	if (async_clk)
1093 		clk_add_alias("async", da850_cpufreq_device.name,
1094 							async_clk, NULL);
1095 	for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
1096 		if (da850_freq_table[i].frequency <= da850_max_speed) {
1097 			cpufreq_info.freq_table = &da850_freq_table[i];
1098 			break;
1099 		}
1100 	}
1101 
1102 	return platform_device_register(&da850_cpufreq_device);
1103 }
1104 
1105 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1106 {
1107 	int ret = 0, diff;
1108 	unsigned int best = (unsigned int) -1;
1109 	struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
1110 	struct cpufreq_frequency_table *pos;
1111 
1112 	rate /= 1000; /* convert to kHz */
1113 
1114 	cpufreq_for_each_entry(pos, table) {
1115 		diff = pos->frequency - rate;
1116 		if (diff < 0)
1117 			diff = -diff;
1118 
1119 		if (diff < best) {
1120 			best = diff;
1121 			ret = pos->frequency;
1122 		}
1123 	}
1124 
1125 	return ret * 1000;
1126 }
1127 
1128 static int da850_set_armrate(struct clk *clk, unsigned long index)
1129 {
1130 	struct clk *pllclk = &pll0_clk;
1131 
1132 	return clk_set_rate(pllclk, index);
1133 }
1134 
1135 static int da850_set_pll0rate(struct clk *clk, unsigned long index)
1136 {
1137 	unsigned int prediv, mult, postdiv;
1138 	struct da850_opp *opp;
1139 	struct pll_data *pll = clk->pll_data;
1140 	int ret;
1141 
1142 	opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
1143 	prediv = opp->prediv;
1144 	mult = opp->mult;
1145 	postdiv = opp->postdiv;
1146 
1147 	ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1148 	if (WARN_ON(ret))
1149 		return ret;
1150 
1151 	return 0;
1152 }
1153 #else
1154 int __init da850_register_cpufreq(char *async_clk)
1155 {
1156 	return 0;
1157 }
1158 
1159 static int da850_set_armrate(struct clk *clk, unsigned long rate)
1160 {
1161 	return -EINVAL;
1162 }
1163 
1164 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1165 {
1166 	return -EINVAL;
1167 }
1168 
1169 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1170 {
1171 	return clk->rate;
1172 }
1173 #endif
1174 
1175 int __init da850_register_pm(struct platform_device *pdev)
1176 {
1177 	int ret;
1178 	struct davinci_pm_config *pdata = pdev->dev.platform_data;
1179 
1180 	ret = davinci_cfg_reg(DA850_RTC_ALARM);
1181 	if (ret)
1182 		return ret;
1183 
1184 	pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
1185 	pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
1186 	pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
1187 
1188 	pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1189 	if (!pdata->cpupll_reg_base)
1190 		return -ENOMEM;
1191 
1192 	pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
1193 	if (!pdata->ddrpll_reg_base) {
1194 		ret = -ENOMEM;
1195 		goto no_ddrpll_mem;
1196 	}
1197 
1198 	pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1199 	if (!pdata->ddrpsc_reg_base) {
1200 		ret = -ENOMEM;
1201 		goto no_ddrpsc_mem;
1202 	}
1203 
1204 	return platform_device_register(pdev);
1205 
1206 no_ddrpsc_mem:
1207 	iounmap(pdata->ddrpll_reg_base);
1208 no_ddrpll_mem:
1209 	iounmap(pdata->cpupll_reg_base);
1210 	return ret;
1211 }
1212 
1213 /* VPIF resource, platform data */
1214 static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
1215 
1216 static struct resource da850_vpif_resource[] = {
1217 	{
1218 		.start = DA8XX_VPIF_BASE,
1219 		.end   = DA8XX_VPIF_BASE + 0xfff,
1220 		.flags = IORESOURCE_MEM,
1221 	}
1222 };
1223 
1224 static struct platform_device da850_vpif_dev = {
1225 	.name		= "vpif",
1226 	.id		= -1,
1227 	.dev		= {
1228 		.dma_mask		= &da850_vpif_dma_mask,
1229 		.coherent_dma_mask	= DMA_BIT_MASK(32),
1230 	},
1231 	.resource	= da850_vpif_resource,
1232 	.num_resources	= ARRAY_SIZE(da850_vpif_resource),
1233 };
1234 
1235 static struct resource da850_vpif_display_resource[] = {
1236 	{
1237 		.start = IRQ_DA850_VPIFINT,
1238 		.end   = IRQ_DA850_VPIFINT,
1239 		.flags = IORESOURCE_IRQ,
1240 	},
1241 };
1242 
1243 static struct platform_device da850_vpif_display_dev = {
1244 	.name		= "vpif_display",
1245 	.id		= -1,
1246 	.dev		= {
1247 		.dma_mask		= &da850_vpif_dma_mask,
1248 		.coherent_dma_mask	= DMA_BIT_MASK(32),
1249 	},
1250 	.resource       = da850_vpif_display_resource,
1251 	.num_resources  = ARRAY_SIZE(da850_vpif_display_resource),
1252 };
1253 
1254 static struct resource da850_vpif_capture_resource[] = {
1255 	{
1256 		.start = IRQ_DA850_VPIFINT,
1257 		.end   = IRQ_DA850_VPIFINT,
1258 		.flags = IORESOURCE_IRQ,
1259 	},
1260 	{
1261 		.start = IRQ_DA850_VPIFINT,
1262 		.end   = IRQ_DA850_VPIFINT,
1263 		.flags = IORESOURCE_IRQ,
1264 	},
1265 };
1266 
1267 static struct platform_device da850_vpif_capture_dev = {
1268 	.name		= "vpif_capture",
1269 	.id		= -1,
1270 	.dev		= {
1271 		.dma_mask		= &da850_vpif_dma_mask,
1272 		.coherent_dma_mask	= DMA_BIT_MASK(32),
1273 	},
1274 	.resource       = da850_vpif_capture_resource,
1275 	.num_resources  = ARRAY_SIZE(da850_vpif_capture_resource),
1276 };
1277 
1278 int __init da850_register_vpif(void)
1279 {
1280 	return platform_device_register(&da850_vpif_dev);
1281 }
1282 
1283 int __init da850_register_vpif_display(struct vpif_display_config
1284 						*display_config)
1285 {
1286 	da850_vpif_display_dev.dev.platform_data = display_config;
1287 	return platform_device_register(&da850_vpif_display_dev);
1288 }
1289 
1290 int __init da850_register_vpif_capture(struct vpif_capture_config
1291 							*capture_config)
1292 {
1293 	da850_vpif_capture_dev.dev.platform_data = capture_config;
1294 	return platform_device_register(&da850_vpif_capture_dev);
1295 }
1296 
1297 static struct davinci_gpio_platform_data da850_gpio_platform_data = {
1298 	.ngpio = 144,
1299 };
1300 
1301 int __init da850_register_gpio(void)
1302 {
1303 	return da8xx_register_gpio(&da850_gpio_platform_data);
1304 }
1305 
1306 static struct davinci_soc_info davinci_soc_info_da850 = {
1307 	.io_desc		= da850_io_desc,
1308 	.io_desc_num		= ARRAY_SIZE(da850_io_desc),
1309 	.jtag_id_reg		= DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
1310 	.ids			= da850_ids,
1311 	.ids_num		= ARRAY_SIZE(da850_ids),
1312 	.cpu_clks		= da850_clks,
1313 	.psc_bases		= da850_psc_bases,
1314 	.psc_bases_num		= ARRAY_SIZE(da850_psc_bases),
1315 	.pinmux_base		= DA8XX_SYSCFG0_BASE + 0x120,
1316 	.pinmux_pins		= da850_pins,
1317 	.pinmux_pins_num	= ARRAY_SIZE(da850_pins),
1318 	.intc_base		= DA8XX_CP_INTC_BASE,
1319 	.intc_type		= DAVINCI_INTC_TYPE_CP_INTC,
1320 	.intc_irq_prios		= da850_default_priorities,
1321 	.intc_irq_num		= DA850_N_CP_INTC_IRQ,
1322 	.timer_info		= &da850_timer_info,
1323 	.emac_pdata		= &da8xx_emac_pdata,
1324 	.sram_dma		= DA8XX_SHARED_RAM_BASE,
1325 	.sram_len		= SZ_128K,
1326 };
1327 
1328 void __init da850_init(void)
1329 {
1330 	unsigned int v;
1331 
1332 	davinci_common_init(&davinci_soc_info_da850);
1333 
1334 	da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1335 	if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1336 		return;
1337 
1338 	da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1339 	if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
1340 		return;
1341 
1342 	/* Unlock writing to PLL0 registers */
1343 	v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1344 	v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1345 	__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1346 
1347 	/* Unlock writing to PLL1 registers */
1348 	v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1349 	v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1350 	__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1351 
1352 	davinci_clk_init(davinci_soc_info_da850.cpu_clks);
1353 }
1354