1 /* 2 * TI DA850/OMAP-L138 chip specific setup 3 * 4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * Derived from: arch/arm/mach-davinci/da830.c 7 * Original Copyrights follow: 8 * 9 * 2009 (c) MontaVista Software, Inc. This file is licensed under 10 * the terms of the GNU General Public License version 2. This program 11 * is licensed "as is" without any warranty of any kind, whether express 12 * or implied. 13 */ 14 #include <linux/gpio.h> 15 #include <linux/init.h> 16 #include <linux/clk.h> 17 #include <linux/platform_device.h> 18 #include <linux/cpufreq.h> 19 #include <linux/regulator/consumer.h> 20 21 #include <asm/mach/map.h> 22 23 #include <mach/psc.h> 24 #include <mach/irqs.h> 25 #include <mach/cputype.h> 26 #include <mach/common.h> 27 #include <mach/time.h> 28 #include <mach/da8xx.h> 29 #include <mach/cpufreq.h> 30 #include <mach/pm.h> 31 #include <mach/gpio-davinci.h> 32 33 #include "clock.h" 34 #include "mux.h" 35 36 /* SoC specific clock flags */ 37 #define DA850_CLK_ASYNC3 BIT(16) 38 39 #define DA850_PLL1_BASE 0x01e1a000 40 #define DA850_TIMER64P2_BASE 0x01f0c000 41 #define DA850_TIMER64P3_BASE 0x01f0d000 42 43 #define DA850_REF_FREQ 24000000 44 45 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4) 46 #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5) 47 #define CFGCHIP0_PLL_MASTER_LOCK BIT(4) 48 49 static int da850_set_armrate(struct clk *clk, unsigned long rate); 50 static int da850_round_armrate(struct clk *clk, unsigned long rate); 51 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate); 52 53 static struct pll_data pll0_data = { 54 .num = 1, 55 .phys_base = DA8XX_PLL0_BASE, 56 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, 57 }; 58 59 static struct clk ref_clk = { 60 .name = "ref_clk", 61 .rate = DA850_REF_FREQ, 62 .set_rate = davinci_simple_set_rate, 63 }; 64 65 static struct clk pll0_clk = { 66 .name = "pll0", 67 .parent = &ref_clk, 68 .pll_data = &pll0_data, 69 .flags = CLK_PLL, 70 .set_rate = da850_set_pll0rate, 71 }; 72 73 static struct clk pll0_aux_clk = { 74 .name = "pll0_aux_clk", 75 .parent = &pll0_clk, 76 .flags = CLK_PLL | PRE_PLL, 77 }; 78 79 static struct clk pll0_sysclk2 = { 80 .name = "pll0_sysclk2", 81 .parent = &pll0_clk, 82 .flags = CLK_PLL, 83 .div_reg = PLLDIV2, 84 }; 85 86 static struct clk pll0_sysclk3 = { 87 .name = "pll0_sysclk3", 88 .parent = &pll0_clk, 89 .flags = CLK_PLL, 90 .div_reg = PLLDIV3, 91 .set_rate = davinci_set_sysclk_rate, 92 .maxrate = 100000000, 93 }; 94 95 static struct clk pll0_sysclk4 = { 96 .name = "pll0_sysclk4", 97 .parent = &pll0_clk, 98 .flags = CLK_PLL, 99 .div_reg = PLLDIV4, 100 }; 101 102 static struct clk pll0_sysclk5 = { 103 .name = "pll0_sysclk5", 104 .parent = &pll0_clk, 105 .flags = CLK_PLL, 106 .div_reg = PLLDIV5, 107 }; 108 109 static struct clk pll0_sysclk6 = { 110 .name = "pll0_sysclk6", 111 .parent = &pll0_clk, 112 .flags = CLK_PLL, 113 .div_reg = PLLDIV6, 114 }; 115 116 static struct clk pll0_sysclk7 = { 117 .name = "pll0_sysclk7", 118 .parent = &pll0_clk, 119 .flags = CLK_PLL, 120 .div_reg = PLLDIV7, 121 }; 122 123 static struct pll_data pll1_data = { 124 .num = 2, 125 .phys_base = DA850_PLL1_BASE, 126 .flags = PLL_HAS_POSTDIV, 127 }; 128 129 static struct clk pll1_clk = { 130 .name = "pll1", 131 .parent = &ref_clk, 132 .pll_data = &pll1_data, 133 .flags = CLK_PLL, 134 }; 135 136 static struct clk pll1_aux_clk = { 137 .name = "pll1_aux_clk", 138 .parent = &pll1_clk, 139 .flags = CLK_PLL | PRE_PLL, 140 }; 141 142 static struct clk pll1_sysclk2 = { 143 .name = "pll1_sysclk2", 144 .parent = &pll1_clk, 145 .flags = CLK_PLL, 146 .div_reg = PLLDIV2, 147 }; 148 149 static struct clk pll1_sysclk3 = { 150 .name = "pll1_sysclk3", 151 .parent = &pll1_clk, 152 .flags = CLK_PLL, 153 .div_reg = PLLDIV3, 154 }; 155 156 static struct clk i2c0_clk = { 157 .name = "i2c0", 158 .parent = &pll0_aux_clk, 159 }; 160 161 static struct clk timerp64_0_clk = { 162 .name = "timer0", 163 .parent = &pll0_aux_clk, 164 }; 165 166 static struct clk timerp64_1_clk = { 167 .name = "timer1", 168 .parent = &pll0_aux_clk, 169 }; 170 171 static struct clk arm_rom_clk = { 172 .name = "arm_rom", 173 .parent = &pll0_sysclk2, 174 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, 175 .flags = ALWAYS_ENABLED, 176 }; 177 178 static struct clk tpcc0_clk = { 179 .name = "tpcc0", 180 .parent = &pll0_sysclk2, 181 .lpsc = DA8XX_LPSC0_TPCC, 182 .flags = ALWAYS_ENABLED | CLK_PSC, 183 }; 184 185 static struct clk tptc0_clk = { 186 .name = "tptc0", 187 .parent = &pll0_sysclk2, 188 .lpsc = DA8XX_LPSC0_TPTC0, 189 .flags = ALWAYS_ENABLED, 190 }; 191 192 static struct clk tptc1_clk = { 193 .name = "tptc1", 194 .parent = &pll0_sysclk2, 195 .lpsc = DA8XX_LPSC0_TPTC1, 196 .flags = ALWAYS_ENABLED, 197 }; 198 199 static struct clk tpcc1_clk = { 200 .name = "tpcc1", 201 .parent = &pll0_sysclk2, 202 .lpsc = DA850_LPSC1_TPCC1, 203 .gpsc = 1, 204 .flags = CLK_PSC | ALWAYS_ENABLED, 205 }; 206 207 static struct clk tptc2_clk = { 208 .name = "tptc2", 209 .parent = &pll0_sysclk2, 210 .lpsc = DA850_LPSC1_TPTC2, 211 .gpsc = 1, 212 .flags = ALWAYS_ENABLED, 213 }; 214 215 static struct clk uart0_clk = { 216 .name = "uart0", 217 .parent = &pll0_sysclk2, 218 .lpsc = DA8XX_LPSC0_UART0, 219 }; 220 221 static struct clk uart1_clk = { 222 .name = "uart1", 223 .parent = &pll0_sysclk2, 224 .lpsc = DA8XX_LPSC1_UART1, 225 .gpsc = 1, 226 .flags = DA850_CLK_ASYNC3, 227 }; 228 229 static struct clk uart2_clk = { 230 .name = "uart2", 231 .parent = &pll0_sysclk2, 232 .lpsc = DA8XX_LPSC1_UART2, 233 .gpsc = 1, 234 .flags = DA850_CLK_ASYNC3, 235 }; 236 237 static struct clk aintc_clk = { 238 .name = "aintc", 239 .parent = &pll0_sysclk4, 240 .lpsc = DA8XX_LPSC0_AINTC, 241 .flags = ALWAYS_ENABLED, 242 }; 243 244 static struct clk gpio_clk = { 245 .name = "gpio", 246 .parent = &pll0_sysclk4, 247 .lpsc = DA8XX_LPSC1_GPIO, 248 .gpsc = 1, 249 }; 250 251 static struct clk i2c1_clk = { 252 .name = "i2c1", 253 .parent = &pll0_sysclk4, 254 .lpsc = DA8XX_LPSC1_I2C, 255 .gpsc = 1, 256 }; 257 258 static struct clk emif3_clk = { 259 .name = "emif3", 260 .parent = &pll0_sysclk5, 261 .lpsc = DA8XX_LPSC1_EMIF3C, 262 .gpsc = 1, 263 .flags = ALWAYS_ENABLED, 264 }; 265 266 static struct clk arm_clk = { 267 .name = "arm", 268 .parent = &pll0_sysclk6, 269 .lpsc = DA8XX_LPSC0_ARM, 270 .flags = ALWAYS_ENABLED, 271 .set_rate = da850_set_armrate, 272 .round_rate = da850_round_armrate, 273 }; 274 275 static struct clk rmii_clk = { 276 .name = "rmii", 277 .parent = &pll0_sysclk7, 278 }; 279 280 static struct clk emac_clk = { 281 .name = "emac", 282 .parent = &pll0_sysclk4, 283 .lpsc = DA8XX_LPSC1_CPGMAC, 284 .gpsc = 1, 285 }; 286 287 static struct clk mcasp_clk = { 288 .name = "mcasp", 289 .parent = &pll0_sysclk2, 290 .lpsc = DA8XX_LPSC1_McASP0, 291 .gpsc = 1, 292 .flags = DA850_CLK_ASYNC3, 293 }; 294 295 static struct clk lcdc_clk = { 296 .name = "lcdc", 297 .parent = &pll0_sysclk2, 298 .lpsc = DA8XX_LPSC1_LCDC, 299 .gpsc = 1, 300 }; 301 302 static struct clk mmcsd0_clk = { 303 .name = "mmcsd0", 304 .parent = &pll0_sysclk2, 305 .lpsc = DA8XX_LPSC0_MMC_SD, 306 }; 307 308 static struct clk mmcsd1_clk = { 309 .name = "mmcsd1", 310 .parent = &pll0_sysclk2, 311 .lpsc = DA850_LPSC1_MMC_SD1, 312 .gpsc = 1, 313 }; 314 315 static struct clk aemif_clk = { 316 .name = "aemif", 317 .parent = &pll0_sysclk3, 318 .lpsc = DA8XX_LPSC0_EMIF25, 319 .flags = ALWAYS_ENABLED, 320 }; 321 322 static struct clk usb11_clk = { 323 .name = "usb11", 324 .parent = &pll0_sysclk4, 325 .lpsc = DA8XX_LPSC1_USB11, 326 .gpsc = 1, 327 }; 328 329 static struct clk usb20_clk = { 330 .name = "usb20", 331 .parent = &pll0_sysclk2, 332 .lpsc = DA8XX_LPSC1_USB20, 333 .gpsc = 1, 334 }; 335 336 static struct clk spi0_clk = { 337 .name = "spi0", 338 .parent = &pll0_sysclk2, 339 .lpsc = DA8XX_LPSC0_SPI0, 340 }; 341 342 static struct clk spi1_clk = { 343 .name = "spi1", 344 .parent = &pll0_sysclk2, 345 .lpsc = DA8XX_LPSC1_SPI1, 346 .gpsc = 1, 347 .flags = DA850_CLK_ASYNC3, 348 }; 349 350 static struct clk vpif_clk = { 351 .name = "vpif", 352 .parent = &pll0_sysclk2, 353 .lpsc = DA850_LPSC1_VPIF, 354 .gpsc = 1, 355 }; 356 357 static struct clk sata_clk = { 358 .name = "sata", 359 .parent = &pll0_sysclk2, 360 .lpsc = DA850_LPSC1_SATA, 361 .gpsc = 1, 362 .flags = PSC_FORCE, 363 }; 364 365 static struct clk_lookup da850_clks[] = { 366 CLK(NULL, "ref", &ref_clk), 367 CLK(NULL, "pll0", &pll0_clk), 368 CLK(NULL, "pll0_aux", &pll0_aux_clk), 369 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), 370 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), 371 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), 372 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), 373 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), 374 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), 375 CLK(NULL, "pll1", &pll1_clk), 376 CLK(NULL, "pll1_aux", &pll1_aux_clk), 377 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), 378 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), 379 CLK("i2c_davinci.1", NULL, &i2c0_clk), 380 CLK(NULL, "timer0", &timerp64_0_clk), 381 CLK("watchdog", NULL, &timerp64_1_clk), 382 CLK(NULL, "arm_rom", &arm_rom_clk), 383 CLK(NULL, "tpcc0", &tpcc0_clk), 384 CLK(NULL, "tptc0", &tptc0_clk), 385 CLK(NULL, "tptc1", &tptc1_clk), 386 CLK(NULL, "tpcc1", &tpcc1_clk), 387 CLK(NULL, "tptc2", &tptc2_clk), 388 CLK(NULL, "uart0", &uart0_clk), 389 CLK(NULL, "uart1", &uart1_clk), 390 CLK(NULL, "uart2", &uart2_clk), 391 CLK(NULL, "aintc", &aintc_clk), 392 CLK(NULL, "gpio", &gpio_clk), 393 CLK("i2c_davinci.2", NULL, &i2c1_clk), 394 CLK(NULL, "emif3", &emif3_clk), 395 CLK(NULL, "arm", &arm_clk), 396 CLK(NULL, "rmii", &rmii_clk), 397 CLK("davinci_emac.1", NULL, &emac_clk), 398 CLK("davinci-mcasp.0", NULL, &mcasp_clk), 399 CLK("da8xx_lcdc.0", "fck", &lcdc_clk), 400 CLK("davinci_mmc.0", NULL, &mmcsd0_clk), 401 CLK("davinci_mmc.1", NULL, &mmcsd1_clk), 402 CLK(NULL, "aemif", &aemif_clk), 403 CLK(NULL, "usb11", &usb11_clk), 404 CLK(NULL, "usb20", &usb20_clk), 405 CLK("spi_davinci.0", NULL, &spi0_clk), 406 CLK("spi_davinci.1", NULL, &spi1_clk), 407 CLK("vpif", NULL, &vpif_clk), 408 CLK("ahci", NULL, &sata_clk), 409 CLK(NULL, NULL, NULL), 410 }; 411 412 /* 413 * Device specific mux setup 414 * 415 * soc description mux mode mode mux dbg 416 * reg offset mask mode 417 */ 418 static const struct mux_config da850_pins[] = { 419 #ifdef CONFIG_DAVINCI_MUX 420 /* UART0 function */ 421 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false) 422 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false) 423 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false) 424 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false) 425 /* UART1 function */ 426 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false) 427 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false) 428 /* UART2 function */ 429 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false) 430 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false) 431 /* I2C1 function */ 432 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false) 433 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false) 434 /* I2C0 function */ 435 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) 436 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) 437 /* EMAC function */ 438 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false) 439 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false) 440 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false) 441 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false) 442 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false) 443 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false) 444 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false) 445 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false) 446 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false) 447 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false) 448 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false) 449 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false) 450 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false) 451 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false) 452 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) 453 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) 454 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) 455 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false) 456 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false) 457 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false) 458 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false) 459 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false) 460 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false) 461 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false) 462 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false) 463 /* McASP function */ 464 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false) 465 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false) 466 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false) 467 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false) 468 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false) 469 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false) 470 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false) 471 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false) 472 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false) 473 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false) 474 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false) 475 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false) 476 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false) 477 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false) 478 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false) 479 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false) 480 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false) 481 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false) 482 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false) 483 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false) 484 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false) 485 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false) 486 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false) 487 /* LCD function */ 488 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false) 489 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false) 490 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false) 491 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false) 492 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false) 493 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false) 494 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false) 495 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false) 496 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false) 497 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false) 498 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false) 499 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false) 500 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false) 501 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false) 502 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false) 503 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false) 504 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false) 505 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false) 506 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false) 507 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false) 508 /* MMC/SD0 function */ 509 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false) 510 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false) 511 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false) 512 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false) 513 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false) 514 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false) 515 /* MMC/SD1 function */ 516 MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false) 517 MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false) 518 MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false) 519 MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false) 520 MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false) 521 MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false) 522 /* EMIF2.5/EMIFA function */ 523 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false) 524 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false) 525 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false) 526 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false) 527 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false) 528 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false) 529 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false) 530 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false) 531 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false) 532 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false) 533 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false) 534 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false) 535 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false) 536 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false) 537 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false) 538 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false) 539 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false) 540 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false) 541 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false) 542 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false) 543 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false) 544 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false) 545 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false) 546 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false) 547 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false) 548 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false) 549 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false) 550 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false) 551 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false) 552 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false) 553 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false) 554 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false) 555 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false) 556 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false) 557 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false) 558 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false) 559 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false) 560 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false) 561 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false) 562 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false) 563 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false) 564 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false) 565 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false) 566 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false) 567 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false) 568 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false) 569 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false) 570 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false) 571 /* GPIO function */ 572 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false) 573 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false) 574 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false) 575 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) 576 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false) 577 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false) 578 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) 579 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) 580 MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false) 581 MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false) 582 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false) 583 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false) 584 /* VPIF Capture */ 585 MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false) 586 MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false) 587 MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false) 588 MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false) 589 MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false) 590 MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false) 591 MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false) 592 MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false) 593 MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false) 594 MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false) 595 MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false) 596 MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false) 597 MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false) 598 MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false) 599 MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false) 600 MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false) 601 MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false) 602 MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false) 603 MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false) 604 MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false) 605 /* VPIF Display */ 606 MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false) 607 MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false) 608 MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false) 609 MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false) 610 MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false) 611 MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false) 612 MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false) 613 MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false) 614 MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false) 615 MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false) 616 MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false) 617 MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false) 618 MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false) 619 MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false) 620 MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false) 621 MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false) 622 MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false) 623 MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false) 624 #endif 625 }; 626 627 const short da850_i2c0_pins[] __initconst = { 628 DA850_I2C0_SDA, DA850_I2C0_SCL, 629 -1 630 }; 631 632 const short da850_i2c1_pins[] __initconst = { 633 DA850_I2C1_SCL, DA850_I2C1_SDA, 634 -1 635 }; 636 637 const short da850_lcdcntl_pins[] __initconst = { 638 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, 639 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, 640 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, 641 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, 642 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, 643 -1 644 }; 645 646 const short da850_vpif_capture_pins[] __initdata = { 647 DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3, 648 DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7, 649 DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11, 650 DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15, 651 DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2, 652 DA850_VPIF_CLKIN3, 653 -1 654 }; 655 656 const short da850_vpif_display_pins[] __initdata = { 657 DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3, 658 DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7, 659 DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10, 660 DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13, 661 DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2, 662 DA850_VPIF_CLKO3, 663 -1 664 }; 665 666 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ 667 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { 668 [IRQ_DA8XX_COMMTX] = 7, 669 [IRQ_DA8XX_COMMRX] = 7, 670 [IRQ_DA8XX_NINT] = 7, 671 [IRQ_DA8XX_EVTOUT0] = 7, 672 [IRQ_DA8XX_EVTOUT1] = 7, 673 [IRQ_DA8XX_EVTOUT2] = 7, 674 [IRQ_DA8XX_EVTOUT3] = 7, 675 [IRQ_DA8XX_EVTOUT4] = 7, 676 [IRQ_DA8XX_EVTOUT5] = 7, 677 [IRQ_DA8XX_EVTOUT6] = 7, 678 [IRQ_DA8XX_EVTOUT7] = 7, 679 [IRQ_DA8XX_CCINT0] = 7, 680 [IRQ_DA8XX_CCERRINT] = 7, 681 [IRQ_DA8XX_TCERRINT0] = 7, 682 [IRQ_DA8XX_AEMIFINT] = 7, 683 [IRQ_DA8XX_I2CINT0] = 7, 684 [IRQ_DA8XX_MMCSDINT0] = 7, 685 [IRQ_DA8XX_MMCSDINT1] = 7, 686 [IRQ_DA8XX_ALLINT0] = 7, 687 [IRQ_DA8XX_RTC] = 7, 688 [IRQ_DA8XX_SPINT0] = 7, 689 [IRQ_DA8XX_TINT12_0] = 7, 690 [IRQ_DA8XX_TINT34_0] = 7, 691 [IRQ_DA8XX_TINT12_1] = 7, 692 [IRQ_DA8XX_TINT34_1] = 7, 693 [IRQ_DA8XX_UARTINT0] = 7, 694 [IRQ_DA8XX_KEYMGRINT] = 7, 695 [IRQ_DA850_MPUADDRERR0] = 7, 696 [IRQ_DA8XX_CHIPINT0] = 7, 697 [IRQ_DA8XX_CHIPINT1] = 7, 698 [IRQ_DA8XX_CHIPINT2] = 7, 699 [IRQ_DA8XX_CHIPINT3] = 7, 700 [IRQ_DA8XX_TCERRINT1] = 7, 701 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, 702 [IRQ_DA8XX_C0_RX_PULSE] = 7, 703 [IRQ_DA8XX_C0_TX_PULSE] = 7, 704 [IRQ_DA8XX_C0_MISC_PULSE] = 7, 705 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, 706 [IRQ_DA8XX_C1_RX_PULSE] = 7, 707 [IRQ_DA8XX_C1_TX_PULSE] = 7, 708 [IRQ_DA8XX_C1_MISC_PULSE] = 7, 709 [IRQ_DA8XX_MEMERR] = 7, 710 [IRQ_DA8XX_GPIO0] = 7, 711 [IRQ_DA8XX_GPIO1] = 7, 712 [IRQ_DA8XX_GPIO2] = 7, 713 [IRQ_DA8XX_GPIO3] = 7, 714 [IRQ_DA8XX_GPIO4] = 7, 715 [IRQ_DA8XX_GPIO5] = 7, 716 [IRQ_DA8XX_GPIO6] = 7, 717 [IRQ_DA8XX_GPIO7] = 7, 718 [IRQ_DA8XX_GPIO8] = 7, 719 [IRQ_DA8XX_I2CINT1] = 7, 720 [IRQ_DA8XX_LCDINT] = 7, 721 [IRQ_DA8XX_UARTINT1] = 7, 722 [IRQ_DA8XX_MCASPINT] = 7, 723 [IRQ_DA8XX_ALLINT1] = 7, 724 [IRQ_DA8XX_SPINT1] = 7, 725 [IRQ_DA8XX_UHPI_INT1] = 7, 726 [IRQ_DA8XX_USB_INT] = 7, 727 [IRQ_DA8XX_IRQN] = 7, 728 [IRQ_DA8XX_RWAKEUP] = 7, 729 [IRQ_DA8XX_UARTINT2] = 7, 730 [IRQ_DA8XX_DFTSSINT] = 7, 731 [IRQ_DA8XX_EHRPWM0] = 7, 732 [IRQ_DA8XX_EHRPWM0TZ] = 7, 733 [IRQ_DA8XX_EHRPWM1] = 7, 734 [IRQ_DA8XX_EHRPWM1TZ] = 7, 735 [IRQ_DA850_SATAINT] = 7, 736 [IRQ_DA850_TINTALL_2] = 7, 737 [IRQ_DA8XX_ECAP0] = 7, 738 [IRQ_DA8XX_ECAP1] = 7, 739 [IRQ_DA8XX_ECAP2] = 7, 740 [IRQ_DA850_MMCSDINT0_1] = 7, 741 [IRQ_DA850_MMCSDINT1_1] = 7, 742 [IRQ_DA850_T12CMPINT0_2] = 7, 743 [IRQ_DA850_T12CMPINT1_2] = 7, 744 [IRQ_DA850_T12CMPINT2_2] = 7, 745 [IRQ_DA850_T12CMPINT3_2] = 7, 746 [IRQ_DA850_T12CMPINT4_2] = 7, 747 [IRQ_DA850_T12CMPINT5_2] = 7, 748 [IRQ_DA850_T12CMPINT6_2] = 7, 749 [IRQ_DA850_T12CMPINT7_2] = 7, 750 [IRQ_DA850_T12CMPINT0_3] = 7, 751 [IRQ_DA850_T12CMPINT1_3] = 7, 752 [IRQ_DA850_T12CMPINT2_3] = 7, 753 [IRQ_DA850_T12CMPINT3_3] = 7, 754 [IRQ_DA850_T12CMPINT4_3] = 7, 755 [IRQ_DA850_T12CMPINT5_3] = 7, 756 [IRQ_DA850_T12CMPINT6_3] = 7, 757 [IRQ_DA850_T12CMPINT7_3] = 7, 758 [IRQ_DA850_RPIINT] = 7, 759 [IRQ_DA850_VPIFINT] = 7, 760 [IRQ_DA850_CCINT1] = 7, 761 [IRQ_DA850_CCERRINT1] = 7, 762 [IRQ_DA850_TCERRINT2] = 7, 763 [IRQ_DA850_TINTALL_3] = 7, 764 [IRQ_DA850_MCBSP0RINT] = 7, 765 [IRQ_DA850_MCBSP0XINT] = 7, 766 [IRQ_DA850_MCBSP1RINT] = 7, 767 [IRQ_DA850_MCBSP1XINT] = 7, 768 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, 769 }; 770 771 static struct map_desc da850_io_desc[] = { 772 { 773 .virtual = IO_VIRT, 774 .pfn = __phys_to_pfn(IO_PHYS), 775 .length = IO_SIZE, 776 .type = MT_DEVICE 777 }, 778 { 779 .virtual = DA8XX_CP_INTC_VIRT, 780 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), 781 .length = DA8XX_CP_INTC_SIZE, 782 .type = MT_DEVICE 783 }, 784 { 785 .virtual = SRAM_VIRT, 786 .pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE), 787 .length = SZ_8K, 788 .type = MT_DEVICE 789 }, 790 }; 791 792 static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE }; 793 794 /* Contents of JTAG ID register used to identify exact cpu type */ 795 static struct davinci_id da850_ids[] = { 796 { 797 .variant = 0x0, 798 .part_no = 0xb7d1, 799 .manufacturer = 0x017, /* 0x02f >> 1 */ 800 .cpu_id = DAVINCI_CPU_ID_DA850, 801 .name = "da850/omap-l138", 802 }, 803 { 804 .variant = 0x1, 805 .part_no = 0xb7d1, 806 .manufacturer = 0x017, /* 0x02f >> 1 */ 807 .cpu_id = DAVINCI_CPU_ID_DA850, 808 .name = "da850/omap-l138/am18x", 809 }, 810 }; 811 812 static struct davinci_timer_instance da850_timer_instance[4] = { 813 { 814 .base = DA8XX_TIMER64P0_BASE, 815 .bottom_irq = IRQ_DA8XX_TINT12_0, 816 .top_irq = IRQ_DA8XX_TINT34_0, 817 }, 818 { 819 .base = DA8XX_TIMER64P1_BASE, 820 .bottom_irq = IRQ_DA8XX_TINT12_1, 821 .top_irq = IRQ_DA8XX_TINT34_1, 822 }, 823 { 824 .base = DA850_TIMER64P2_BASE, 825 .bottom_irq = IRQ_DA850_TINT12_2, 826 .top_irq = IRQ_DA850_TINT34_2, 827 }, 828 { 829 .base = DA850_TIMER64P3_BASE, 830 .bottom_irq = IRQ_DA850_TINT12_3, 831 .top_irq = IRQ_DA850_TINT34_3, 832 }, 833 }; 834 835 /* 836 * T0_BOT: Timer 0, bottom : Used for clock_event 837 * T0_TOP: Timer 0, top : Used for clocksource 838 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer 839 */ 840 static struct davinci_timer_info da850_timer_info = { 841 .timers = da850_timer_instance, 842 .clockevent_id = T0_BOT, 843 .clocksource_id = T0_TOP, 844 }; 845 846 static void da850_set_async3_src(int pllnum) 847 { 848 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2; 849 struct clk_lookup *c; 850 unsigned int v; 851 int ret; 852 853 for (c = da850_clks; c->clk; c++) { 854 clk = c->clk; 855 if (clk->flags & DA850_CLK_ASYNC3) { 856 ret = clk_set_parent(clk, newparent); 857 WARN(ret, "DA850: unable to re-parent clock %s", 858 clk->name); 859 } 860 } 861 862 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); 863 if (pllnum) 864 v |= CFGCHIP3_ASYNC3_CLKSRC; 865 else 866 v &= ~CFGCHIP3_ASYNC3_CLKSRC; 867 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); 868 } 869 870 #ifdef CONFIG_CPU_FREQ 871 /* 872 * Notes: 873 * According to the TRM, minimum PLLM results in maximum power savings. 874 * The OPP definitions below should keep the PLLM as low as possible. 875 * 876 * The output of the PLLM must be between 300 to 600 MHz. 877 */ 878 struct da850_opp { 879 unsigned int freq; /* in KHz */ 880 unsigned int prediv; 881 unsigned int mult; 882 unsigned int postdiv; 883 unsigned int cvdd_min; /* in uV */ 884 unsigned int cvdd_max; /* in uV */ 885 }; 886 887 static const struct da850_opp da850_opp_456 = { 888 .freq = 456000, 889 .prediv = 1, 890 .mult = 19, 891 .postdiv = 1, 892 .cvdd_min = 1300000, 893 .cvdd_max = 1350000, 894 }; 895 896 static const struct da850_opp da850_opp_408 = { 897 .freq = 408000, 898 .prediv = 1, 899 .mult = 17, 900 .postdiv = 1, 901 .cvdd_min = 1300000, 902 .cvdd_max = 1350000, 903 }; 904 905 static const struct da850_opp da850_opp_372 = { 906 .freq = 372000, 907 .prediv = 2, 908 .mult = 31, 909 .postdiv = 1, 910 .cvdd_min = 1200000, 911 .cvdd_max = 1320000, 912 }; 913 914 static const struct da850_opp da850_opp_300 = { 915 .freq = 300000, 916 .prediv = 1, 917 .mult = 25, 918 .postdiv = 2, 919 .cvdd_min = 1200000, 920 .cvdd_max = 1320000, 921 }; 922 923 static const struct da850_opp da850_opp_200 = { 924 .freq = 200000, 925 .prediv = 1, 926 .mult = 25, 927 .postdiv = 3, 928 .cvdd_min = 1100000, 929 .cvdd_max = 1160000, 930 }; 931 932 static const struct da850_opp da850_opp_96 = { 933 .freq = 96000, 934 .prediv = 1, 935 .mult = 20, 936 .postdiv = 5, 937 .cvdd_min = 1000000, 938 .cvdd_max = 1050000, 939 }; 940 941 #define OPP(freq) \ 942 { \ 943 .index = (unsigned int) &da850_opp_##freq, \ 944 .frequency = freq * 1000, \ 945 } 946 947 static struct cpufreq_frequency_table da850_freq_table[] = { 948 OPP(456), 949 OPP(408), 950 OPP(372), 951 OPP(300), 952 OPP(200), 953 OPP(96), 954 { 955 .index = 0, 956 .frequency = CPUFREQ_TABLE_END, 957 }, 958 }; 959 960 #ifdef CONFIG_REGULATOR 961 static int da850_set_voltage(unsigned int index); 962 static int da850_regulator_init(void); 963 #endif 964 965 static struct davinci_cpufreq_config cpufreq_info = { 966 .freq_table = da850_freq_table, 967 #ifdef CONFIG_REGULATOR 968 .init = da850_regulator_init, 969 .set_voltage = da850_set_voltage, 970 #endif 971 }; 972 973 #ifdef CONFIG_REGULATOR 974 static struct regulator *cvdd; 975 976 static int da850_set_voltage(unsigned int index) 977 { 978 struct da850_opp *opp; 979 980 if (!cvdd) 981 return -ENODEV; 982 983 opp = (struct da850_opp *) cpufreq_info.freq_table[index].index; 984 985 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); 986 } 987 988 static int da850_regulator_init(void) 989 { 990 cvdd = regulator_get(NULL, "cvdd"); 991 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;" 992 " voltage scaling unsupported\n")) { 993 return PTR_ERR(cvdd); 994 } 995 996 return 0; 997 } 998 #endif 999 1000 static struct platform_device da850_cpufreq_device = { 1001 .name = "cpufreq-davinci", 1002 .dev = { 1003 .platform_data = &cpufreq_info, 1004 }, 1005 .id = -1, 1006 }; 1007 1008 unsigned int da850_max_speed = 300000; 1009 1010 int da850_register_cpufreq(char *async_clk) 1011 { 1012 int i; 1013 1014 /* cpufreq driver can help keep an "async" clock constant */ 1015 if (async_clk) 1016 clk_add_alias("async", da850_cpufreq_device.name, 1017 async_clk, NULL); 1018 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) { 1019 if (da850_freq_table[i].frequency <= da850_max_speed) { 1020 cpufreq_info.freq_table = &da850_freq_table[i]; 1021 break; 1022 } 1023 } 1024 1025 return platform_device_register(&da850_cpufreq_device); 1026 } 1027 1028 static int da850_round_armrate(struct clk *clk, unsigned long rate) 1029 { 1030 int i, ret = 0, diff; 1031 unsigned int best = (unsigned int) -1; 1032 struct cpufreq_frequency_table *table = cpufreq_info.freq_table; 1033 1034 rate /= 1000; /* convert to kHz */ 1035 1036 for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) { 1037 diff = table[i].frequency - rate; 1038 if (diff < 0) 1039 diff = -diff; 1040 1041 if (diff < best) { 1042 best = diff; 1043 ret = table[i].frequency; 1044 } 1045 } 1046 1047 return ret * 1000; 1048 } 1049 1050 static int da850_set_armrate(struct clk *clk, unsigned long index) 1051 { 1052 struct clk *pllclk = &pll0_clk; 1053 1054 return clk_set_rate(pllclk, index); 1055 } 1056 1057 static int da850_set_pll0rate(struct clk *clk, unsigned long index) 1058 { 1059 unsigned int prediv, mult, postdiv; 1060 struct da850_opp *opp; 1061 struct pll_data *pll = clk->pll_data; 1062 int ret; 1063 1064 opp = (struct da850_opp *) cpufreq_info.freq_table[index].index; 1065 prediv = opp->prediv; 1066 mult = opp->mult; 1067 postdiv = opp->postdiv; 1068 1069 ret = davinci_set_pllrate(pll, prediv, mult, postdiv); 1070 if (WARN_ON(ret)) 1071 return ret; 1072 1073 return 0; 1074 } 1075 #else 1076 int __init da850_register_cpufreq(char *async_clk) 1077 { 1078 return 0; 1079 } 1080 1081 static int da850_set_armrate(struct clk *clk, unsigned long rate) 1082 { 1083 return -EINVAL; 1084 } 1085 1086 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate) 1087 { 1088 return -EINVAL; 1089 } 1090 1091 static int da850_round_armrate(struct clk *clk, unsigned long rate) 1092 { 1093 return clk->rate; 1094 } 1095 #endif 1096 1097 int __init da850_register_pm(struct platform_device *pdev) 1098 { 1099 int ret; 1100 struct davinci_pm_config *pdata = pdev->dev.platform_data; 1101 1102 ret = davinci_cfg_reg(DA850_RTC_ALARM); 1103 if (ret) 1104 return ret; 1105 1106 pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr(); 1107 pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG); 1108 pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C; 1109 1110 pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K); 1111 if (!pdata->cpupll_reg_base) 1112 return -ENOMEM; 1113 1114 pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K); 1115 if (!pdata->ddrpll_reg_base) { 1116 ret = -ENOMEM; 1117 goto no_ddrpll_mem; 1118 } 1119 1120 pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K); 1121 if (!pdata->ddrpsc_reg_base) { 1122 ret = -ENOMEM; 1123 goto no_ddrpsc_mem; 1124 } 1125 1126 return platform_device_register(pdev); 1127 1128 no_ddrpsc_mem: 1129 iounmap(pdata->ddrpll_reg_base); 1130 no_ddrpll_mem: 1131 iounmap(pdata->cpupll_reg_base); 1132 return ret; 1133 } 1134 1135 /* VPIF resource, platform data */ 1136 static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32); 1137 1138 static struct resource da850_vpif_resource[] = { 1139 { 1140 .start = DA8XX_VPIF_BASE, 1141 .end = DA8XX_VPIF_BASE + 0xfff, 1142 .flags = IORESOURCE_MEM, 1143 } 1144 }; 1145 1146 static struct platform_device da850_vpif_dev = { 1147 .name = "vpif", 1148 .id = -1, 1149 .dev = { 1150 .dma_mask = &da850_vpif_dma_mask, 1151 .coherent_dma_mask = DMA_BIT_MASK(32), 1152 }, 1153 .resource = da850_vpif_resource, 1154 .num_resources = ARRAY_SIZE(da850_vpif_resource), 1155 }; 1156 1157 static struct resource da850_vpif_display_resource[] = { 1158 { 1159 .start = IRQ_DA850_VPIFINT, 1160 .end = IRQ_DA850_VPIFINT, 1161 .flags = IORESOURCE_IRQ, 1162 }, 1163 }; 1164 1165 static struct platform_device da850_vpif_display_dev = { 1166 .name = "vpif_display", 1167 .id = -1, 1168 .dev = { 1169 .dma_mask = &da850_vpif_dma_mask, 1170 .coherent_dma_mask = DMA_BIT_MASK(32), 1171 }, 1172 .resource = da850_vpif_display_resource, 1173 .num_resources = ARRAY_SIZE(da850_vpif_display_resource), 1174 }; 1175 1176 static struct resource da850_vpif_capture_resource[] = { 1177 { 1178 .start = IRQ_DA850_VPIFINT, 1179 .end = IRQ_DA850_VPIFINT, 1180 .flags = IORESOURCE_IRQ, 1181 }, 1182 { 1183 .start = IRQ_DA850_VPIFINT, 1184 .end = IRQ_DA850_VPIFINT, 1185 .flags = IORESOURCE_IRQ, 1186 }, 1187 }; 1188 1189 static struct platform_device da850_vpif_capture_dev = { 1190 .name = "vpif_capture", 1191 .id = -1, 1192 .dev = { 1193 .dma_mask = &da850_vpif_dma_mask, 1194 .coherent_dma_mask = DMA_BIT_MASK(32), 1195 }, 1196 .resource = da850_vpif_capture_resource, 1197 .num_resources = ARRAY_SIZE(da850_vpif_capture_resource), 1198 }; 1199 1200 int __init da850_register_vpif(void) 1201 { 1202 return platform_device_register(&da850_vpif_dev); 1203 } 1204 1205 int __init da850_register_vpif_display(struct vpif_display_config 1206 *display_config) 1207 { 1208 da850_vpif_display_dev.dev.platform_data = display_config; 1209 return platform_device_register(&da850_vpif_display_dev); 1210 } 1211 1212 int __init da850_register_vpif_capture(struct vpif_capture_config 1213 *capture_config) 1214 { 1215 da850_vpif_capture_dev.dev.platform_data = capture_config; 1216 return platform_device_register(&da850_vpif_capture_dev); 1217 } 1218 1219 static struct davinci_soc_info davinci_soc_info_da850 = { 1220 .io_desc = da850_io_desc, 1221 .io_desc_num = ARRAY_SIZE(da850_io_desc), 1222 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, 1223 .ids = da850_ids, 1224 .ids_num = ARRAY_SIZE(da850_ids), 1225 .cpu_clks = da850_clks, 1226 .psc_bases = da850_psc_bases, 1227 .psc_bases_num = ARRAY_SIZE(da850_psc_bases), 1228 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, 1229 .pinmux_pins = da850_pins, 1230 .pinmux_pins_num = ARRAY_SIZE(da850_pins), 1231 .intc_base = DA8XX_CP_INTC_BASE, 1232 .intc_type = DAVINCI_INTC_TYPE_CP_INTC, 1233 .intc_irq_prios = da850_default_priorities, 1234 .intc_irq_num = DA850_N_CP_INTC_IRQ, 1235 .timer_info = &da850_timer_info, 1236 .gpio_type = GPIO_TYPE_DAVINCI, 1237 .gpio_base = DA8XX_GPIO_BASE, 1238 .gpio_num = 144, 1239 .gpio_irq = IRQ_DA8XX_GPIO0, 1240 .serial_dev = &da8xx_serial_device, 1241 .emac_pdata = &da8xx_emac_pdata, 1242 .sram_dma = DA8XX_ARM_RAM_BASE, 1243 .sram_len = SZ_8K, 1244 }; 1245 1246 void __init da850_init(void) 1247 { 1248 unsigned int v; 1249 1250 davinci_common_init(&davinci_soc_info_da850); 1251 1252 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); 1253 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module")) 1254 return; 1255 1256 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K); 1257 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module")) 1258 return; 1259 1260 /* 1261 * Move the clock source of Async3 domain to PLL1 SYSCLK2. 1262 * This helps keeping the peripherals on this domain insulated 1263 * from CPU frequency changes caused by DVFS. The firmware sets 1264 * both PLL0 and PLL1 to the same frequency so, there should not 1265 * be any noticeable change even in non-DVFS use cases. 1266 */ 1267 da850_set_async3_src(1); 1268 1269 /* Unlock writing to PLL0 registers */ 1270 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG)); 1271 v &= ~CFGCHIP0_PLL_MASTER_LOCK; 1272 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG)); 1273 1274 /* Unlock writing to PLL1 registers */ 1275 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); 1276 v &= ~CFGCHIP3_PLL1_MASTER_LOCK; 1277 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); 1278 } 1279