1 /* 2 * TI DA850/OMAP-L138 chip specific setup 3 * 4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * Derived from: arch/arm/mach-davinci/da830.c 7 * Original Copyrights follow: 8 * 9 * 2009 (c) MontaVista Software, Inc. This file is licensed under 10 * the terms of the GNU General Public License version 2. This program 11 * is licensed "as is" without any warranty of any kind, whether express 12 * or implied. 13 */ 14 #include <linux/gpio.h> 15 #include <linux/init.h> 16 #include <linux/clk.h> 17 #include <linux/platform_device.h> 18 #include <linux/cpufreq.h> 19 #include <linux/regulator/consumer.h> 20 21 #include <asm/mach/map.h> 22 23 #include <mach/psc.h> 24 #include <mach/irqs.h> 25 #include <mach/cputype.h> 26 #include <mach/common.h> 27 #include <mach/time.h> 28 #include <mach/da8xx.h> 29 #include <mach/cpufreq.h> 30 #include <mach/pm.h> 31 #include <mach/gpio-davinci.h> 32 33 #include "clock.h" 34 #include "mux.h" 35 36 /* SoC specific clock flags */ 37 #define DA850_CLK_ASYNC3 BIT(16) 38 39 #define DA850_PLL1_BASE 0x01e1a000 40 #define DA850_TIMER64P2_BASE 0x01f0c000 41 #define DA850_TIMER64P3_BASE 0x01f0d000 42 43 #define DA850_REF_FREQ 24000000 44 45 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4) 46 #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5) 47 #define CFGCHIP0_PLL_MASTER_LOCK BIT(4) 48 49 static int da850_set_armrate(struct clk *clk, unsigned long rate); 50 static int da850_round_armrate(struct clk *clk, unsigned long rate); 51 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate); 52 53 static struct pll_data pll0_data = { 54 .num = 1, 55 .phys_base = DA8XX_PLL0_BASE, 56 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, 57 }; 58 59 static struct clk ref_clk = { 60 .name = "ref_clk", 61 .rate = DA850_REF_FREQ, 62 .set_rate = davinci_simple_set_rate, 63 }; 64 65 static struct clk pll0_clk = { 66 .name = "pll0", 67 .parent = &ref_clk, 68 .pll_data = &pll0_data, 69 .flags = CLK_PLL, 70 .set_rate = da850_set_pll0rate, 71 }; 72 73 static struct clk pll0_aux_clk = { 74 .name = "pll0_aux_clk", 75 .parent = &pll0_clk, 76 .flags = CLK_PLL | PRE_PLL, 77 }; 78 79 static struct clk pll0_sysclk2 = { 80 .name = "pll0_sysclk2", 81 .parent = &pll0_clk, 82 .flags = CLK_PLL, 83 .div_reg = PLLDIV2, 84 }; 85 86 static struct clk pll0_sysclk3 = { 87 .name = "pll0_sysclk3", 88 .parent = &pll0_clk, 89 .flags = CLK_PLL, 90 .div_reg = PLLDIV3, 91 .set_rate = davinci_set_sysclk_rate, 92 .maxrate = 100000000, 93 }; 94 95 static struct clk pll0_sysclk4 = { 96 .name = "pll0_sysclk4", 97 .parent = &pll0_clk, 98 .flags = CLK_PLL, 99 .div_reg = PLLDIV4, 100 }; 101 102 static struct clk pll0_sysclk5 = { 103 .name = "pll0_sysclk5", 104 .parent = &pll0_clk, 105 .flags = CLK_PLL, 106 .div_reg = PLLDIV5, 107 }; 108 109 static struct clk pll0_sysclk6 = { 110 .name = "pll0_sysclk6", 111 .parent = &pll0_clk, 112 .flags = CLK_PLL, 113 .div_reg = PLLDIV6, 114 }; 115 116 static struct clk pll0_sysclk7 = { 117 .name = "pll0_sysclk7", 118 .parent = &pll0_clk, 119 .flags = CLK_PLL, 120 .div_reg = PLLDIV7, 121 }; 122 123 static struct pll_data pll1_data = { 124 .num = 2, 125 .phys_base = DA850_PLL1_BASE, 126 .flags = PLL_HAS_POSTDIV, 127 }; 128 129 static struct clk pll1_clk = { 130 .name = "pll1", 131 .parent = &ref_clk, 132 .pll_data = &pll1_data, 133 .flags = CLK_PLL, 134 }; 135 136 static struct clk pll1_aux_clk = { 137 .name = "pll1_aux_clk", 138 .parent = &pll1_clk, 139 .flags = CLK_PLL | PRE_PLL, 140 }; 141 142 static struct clk pll1_sysclk2 = { 143 .name = "pll1_sysclk2", 144 .parent = &pll1_clk, 145 .flags = CLK_PLL, 146 .div_reg = PLLDIV2, 147 }; 148 149 static struct clk pll1_sysclk3 = { 150 .name = "pll1_sysclk3", 151 .parent = &pll1_clk, 152 .flags = CLK_PLL, 153 .div_reg = PLLDIV3, 154 }; 155 156 static struct clk pll1_sysclk4 = { 157 .name = "pll1_sysclk4", 158 .parent = &pll1_clk, 159 .flags = CLK_PLL, 160 .div_reg = PLLDIV4, 161 }; 162 163 static struct clk pll1_sysclk5 = { 164 .name = "pll1_sysclk5", 165 .parent = &pll1_clk, 166 .flags = CLK_PLL, 167 .div_reg = PLLDIV5, 168 }; 169 170 static struct clk pll1_sysclk6 = { 171 .name = "pll0_sysclk6", 172 .parent = &pll0_clk, 173 .flags = CLK_PLL, 174 .div_reg = PLLDIV6, 175 }; 176 177 static struct clk pll1_sysclk7 = { 178 .name = "pll1_sysclk7", 179 .parent = &pll1_clk, 180 .flags = CLK_PLL, 181 .div_reg = PLLDIV7, 182 }; 183 184 static struct clk i2c0_clk = { 185 .name = "i2c0", 186 .parent = &pll0_aux_clk, 187 }; 188 189 static struct clk timerp64_0_clk = { 190 .name = "timer0", 191 .parent = &pll0_aux_clk, 192 }; 193 194 static struct clk timerp64_1_clk = { 195 .name = "timer1", 196 .parent = &pll0_aux_clk, 197 }; 198 199 static struct clk arm_rom_clk = { 200 .name = "arm_rom", 201 .parent = &pll0_sysclk2, 202 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, 203 .flags = ALWAYS_ENABLED, 204 }; 205 206 static struct clk tpcc0_clk = { 207 .name = "tpcc0", 208 .parent = &pll0_sysclk2, 209 .lpsc = DA8XX_LPSC0_TPCC, 210 .flags = ALWAYS_ENABLED | CLK_PSC, 211 }; 212 213 static struct clk tptc0_clk = { 214 .name = "tptc0", 215 .parent = &pll0_sysclk2, 216 .lpsc = DA8XX_LPSC0_TPTC0, 217 .flags = ALWAYS_ENABLED, 218 }; 219 220 static struct clk tptc1_clk = { 221 .name = "tptc1", 222 .parent = &pll0_sysclk2, 223 .lpsc = DA8XX_LPSC0_TPTC1, 224 .flags = ALWAYS_ENABLED, 225 }; 226 227 static struct clk tpcc1_clk = { 228 .name = "tpcc1", 229 .parent = &pll0_sysclk2, 230 .lpsc = DA850_LPSC1_TPCC1, 231 .gpsc = 1, 232 .flags = CLK_PSC | ALWAYS_ENABLED, 233 }; 234 235 static struct clk tptc2_clk = { 236 .name = "tptc2", 237 .parent = &pll0_sysclk2, 238 .lpsc = DA850_LPSC1_TPTC2, 239 .gpsc = 1, 240 .flags = ALWAYS_ENABLED, 241 }; 242 243 static struct clk uart0_clk = { 244 .name = "uart0", 245 .parent = &pll0_sysclk2, 246 .lpsc = DA8XX_LPSC0_UART0, 247 }; 248 249 static struct clk uart1_clk = { 250 .name = "uart1", 251 .parent = &pll0_sysclk2, 252 .lpsc = DA8XX_LPSC1_UART1, 253 .gpsc = 1, 254 .flags = DA850_CLK_ASYNC3, 255 }; 256 257 static struct clk uart2_clk = { 258 .name = "uart2", 259 .parent = &pll0_sysclk2, 260 .lpsc = DA8XX_LPSC1_UART2, 261 .gpsc = 1, 262 .flags = DA850_CLK_ASYNC3, 263 }; 264 265 static struct clk aintc_clk = { 266 .name = "aintc", 267 .parent = &pll0_sysclk4, 268 .lpsc = DA8XX_LPSC0_AINTC, 269 .flags = ALWAYS_ENABLED, 270 }; 271 272 static struct clk gpio_clk = { 273 .name = "gpio", 274 .parent = &pll0_sysclk4, 275 .lpsc = DA8XX_LPSC1_GPIO, 276 .gpsc = 1, 277 }; 278 279 static struct clk i2c1_clk = { 280 .name = "i2c1", 281 .parent = &pll0_sysclk4, 282 .lpsc = DA8XX_LPSC1_I2C, 283 .gpsc = 1, 284 }; 285 286 static struct clk emif3_clk = { 287 .name = "emif3", 288 .parent = &pll0_sysclk5, 289 .lpsc = DA8XX_LPSC1_EMIF3C, 290 .gpsc = 1, 291 .flags = ALWAYS_ENABLED, 292 }; 293 294 static struct clk arm_clk = { 295 .name = "arm", 296 .parent = &pll0_sysclk6, 297 .lpsc = DA8XX_LPSC0_ARM, 298 .flags = ALWAYS_ENABLED, 299 .set_rate = da850_set_armrate, 300 .round_rate = da850_round_armrate, 301 }; 302 303 static struct clk rmii_clk = { 304 .name = "rmii", 305 .parent = &pll0_sysclk7, 306 }; 307 308 static struct clk emac_clk = { 309 .name = "emac", 310 .parent = &pll0_sysclk4, 311 .lpsc = DA8XX_LPSC1_CPGMAC, 312 .gpsc = 1, 313 }; 314 315 static struct clk mcasp_clk = { 316 .name = "mcasp", 317 .parent = &pll0_sysclk2, 318 .lpsc = DA8XX_LPSC1_McASP0, 319 .gpsc = 1, 320 .flags = DA850_CLK_ASYNC3, 321 }; 322 323 static struct clk lcdc_clk = { 324 .name = "lcdc", 325 .parent = &pll0_sysclk2, 326 .lpsc = DA8XX_LPSC1_LCDC, 327 .gpsc = 1, 328 }; 329 330 static struct clk mmcsd0_clk = { 331 .name = "mmcsd0", 332 .parent = &pll0_sysclk2, 333 .lpsc = DA8XX_LPSC0_MMC_SD, 334 }; 335 336 static struct clk mmcsd1_clk = { 337 .name = "mmcsd1", 338 .parent = &pll0_sysclk2, 339 .lpsc = DA850_LPSC1_MMC_SD1, 340 .gpsc = 1, 341 }; 342 343 static struct clk aemif_clk = { 344 .name = "aemif", 345 .parent = &pll0_sysclk3, 346 .lpsc = DA8XX_LPSC0_EMIF25, 347 .flags = ALWAYS_ENABLED, 348 }; 349 350 static struct clk usb11_clk = { 351 .name = "usb11", 352 .parent = &pll0_sysclk4, 353 .lpsc = DA8XX_LPSC1_USB11, 354 .gpsc = 1, 355 }; 356 357 static struct clk usb20_clk = { 358 .name = "usb20", 359 .parent = &pll0_sysclk2, 360 .lpsc = DA8XX_LPSC1_USB20, 361 .gpsc = 1, 362 }; 363 364 static struct clk spi0_clk = { 365 .name = "spi0", 366 .parent = &pll0_sysclk2, 367 .lpsc = DA8XX_LPSC0_SPI0, 368 }; 369 370 static struct clk spi1_clk = { 371 .name = "spi1", 372 .parent = &pll0_sysclk2, 373 .lpsc = DA8XX_LPSC1_SPI1, 374 .gpsc = 1, 375 .flags = DA850_CLK_ASYNC3, 376 }; 377 378 static struct clk sata_clk = { 379 .name = "sata", 380 .parent = &pll0_sysclk2, 381 .lpsc = DA850_LPSC1_SATA, 382 .gpsc = 1, 383 .flags = PSC_FORCE, 384 }; 385 386 static struct clk_lookup da850_clks[] = { 387 CLK(NULL, "ref", &ref_clk), 388 CLK(NULL, "pll0", &pll0_clk), 389 CLK(NULL, "pll0_aux", &pll0_aux_clk), 390 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), 391 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), 392 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), 393 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), 394 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), 395 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), 396 CLK(NULL, "pll1", &pll1_clk), 397 CLK(NULL, "pll1_aux", &pll1_aux_clk), 398 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), 399 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), 400 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), 401 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), 402 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6), 403 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), 404 CLK("i2c_davinci.1", NULL, &i2c0_clk), 405 CLK(NULL, "timer0", &timerp64_0_clk), 406 CLK("watchdog", NULL, &timerp64_1_clk), 407 CLK(NULL, "arm_rom", &arm_rom_clk), 408 CLK(NULL, "tpcc0", &tpcc0_clk), 409 CLK(NULL, "tptc0", &tptc0_clk), 410 CLK(NULL, "tptc1", &tptc1_clk), 411 CLK(NULL, "tpcc1", &tpcc1_clk), 412 CLK(NULL, "tptc2", &tptc2_clk), 413 CLK(NULL, "uart0", &uart0_clk), 414 CLK(NULL, "uart1", &uart1_clk), 415 CLK(NULL, "uart2", &uart2_clk), 416 CLK(NULL, "aintc", &aintc_clk), 417 CLK(NULL, "gpio", &gpio_clk), 418 CLK("i2c_davinci.2", NULL, &i2c1_clk), 419 CLK(NULL, "emif3", &emif3_clk), 420 CLK(NULL, "arm", &arm_clk), 421 CLK(NULL, "rmii", &rmii_clk), 422 CLK("davinci_emac.1", NULL, &emac_clk), 423 CLK("davinci-mcasp.0", NULL, &mcasp_clk), 424 CLK("da8xx_lcdc.0", NULL, &lcdc_clk), 425 CLK("davinci_mmc.0", NULL, &mmcsd0_clk), 426 CLK("davinci_mmc.1", NULL, &mmcsd1_clk), 427 CLK(NULL, "aemif", &aemif_clk), 428 CLK(NULL, "usb11", &usb11_clk), 429 CLK(NULL, "usb20", &usb20_clk), 430 CLK("spi_davinci.0", NULL, &spi0_clk), 431 CLK("spi_davinci.1", NULL, &spi1_clk), 432 CLK("ahci", NULL, &sata_clk), 433 CLK(NULL, NULL, NULL), 434 }; 435 436 /* 437 * Device specific mux setup 438 * 439 * soc description mux mode mode mux dbg 440 * reg offset mask mode 441 */ 442 static const struct mux_config da850_pins[] = { 443 #ifdef CONFIG_DAVINCI_MUX 444 /* UART0 function */ 445 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false) 446 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false) 447 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false) 448 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false) 449 /* UART1 function */ 450 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false) 451 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false) 452 /* UART2 function */ 453 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false) 454 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false) 455 /* I2C1 function */ 456 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false) 457 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false) 458 /* I2C0 function */ 459 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) 460 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) 461 /* EMAC function */ 462 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false) 463 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false) 464 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false) 465 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false) 466 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false) 467 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false) 468 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false) 469 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false) 470 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false) 471 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false) 472 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false) 473 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false) 474 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false) 475 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false) 476 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) 477 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) 478 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) 479 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false) 480 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false) 481 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false) 482 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false) 483 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false) 484 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false) 485 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false) 486 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false) 487 /* McASP function */ 488 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false) 489 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false) 490 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false) 491 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false) 492 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false) 493 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false) 494 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false) 495 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false) 496 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false) 497 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false) 498 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false) 499 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false) 500 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false) 501 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false) 502 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false) 503 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false) 504 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false) 505 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false) 506 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false) 507 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false) 508 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false) 509 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false) 510 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false) 511 /* LCD function */ 512 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false) 513 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false) 514 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false) 515 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false) 516 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false) 517 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false) 518 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false) 519 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false) 520 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false) 521 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false) 522 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false) 523 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false) 524 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false) 525 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false) 526 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false) 527 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false) 528 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false) 529 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false) 530 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false) 531 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false) 532 /* MMC/SD0 function */ 533 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false) 534 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false) 535 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false) 536 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false) 537 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false) 538 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false) 539 /* EMIF2.5/EMIFA function */ 540 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false) 541 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false) 542 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false) 543 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false) 544 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false) 545 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false) 546 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false) 547 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false) 548 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false) 549 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false) 550 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false) 551 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false) 552 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false) 553 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false) 554 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false) 555 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false) 556 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false) 557 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false) 558 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false) 559 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false) 560 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false) 561 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false) 562 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false) 563 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false) 564 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false) 565 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false) 566 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false) 567 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false) 568 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false) 569 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false) 570 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false) 571 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false) 572 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false) 573 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false) 574 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false) 575 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false) 576 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false) 577 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false) 578 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false) 579 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false) 580 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false) 581 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false) 582 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false) 583 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false) 584 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false) 585 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false) 586 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false) 587 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false) 588 /* GPIO function */ 589 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false) 590 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false) 591 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false) 592 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) 593 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false) 594 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false) 595 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) 596 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) 597 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false) 598 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false) 599 #endif 600 }; 601 602 const short da850_i2c0_pins[] __initdata = { 603 DA850_I2C0_SDA, DA850_I2C0_SCL, 604 -1 605 }; 606 607 const short da850_i2c1_pins[] __initdata = { 608 DA850_I2C1_SCL, DA850_I2C1_SDA, 609 -1 610 }; 611 612 const short da850_lcdcntl_pins[] __initdata = { 613 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, 614 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, 615 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, 616 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, 617 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, 618 -1 619 }; 620 621 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ 622 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { 623 [IRQ_DA8XX_COMMTX] = 7, 624 [IRQ_DA8XX_COMMRX] = 7, 625 [IRQ_DA8XX_NINT] = 7, 626 [IRQ_DA8XX_EVTOUT0] = 7, 627 [IRQ_DA8XX_EVTOUT1] = 7, 628 [IRQ_DA8XX_EVTOUT2] = 7, 629 [IRQ_DA8XX_EVTOUT3] = 7, 630 [IRQ_DA8XX_EVTOUT4] = 7, 631 [IRQ_DA8XX_EVTOUT5] = 7, 632 [IRQ_DA8XX_EVTOUT6] = 7, 633 [IRQ_DA8XX_EVTOUT7] = 7, 634 [IRQ_DA8XX_CCINT0] = 7, 635 [IRQ_DA8XX_CCERRINT] = 7, 636 [IRQ_DA8XX_TCERRINT0] = 7, 637 [IRQ_DA8XX_AEMIFINT] = 7, 638 [IRQ_DA8XX_I2CINT0] = 7, 639 [IRQ_DA8XX_MMCSDINT0] = 7, 640 [IRQ_DA8XX_MMCSDINT1] = 7, 641 [IRQ_DA8XX_ALLINT0] = 7, 642 [IRQ_DA8XX_RTC] = 7, 643 [IRQ_DA8XX_SPINT0] = 7, 644 [IRQ_DA8XX_TINT12_0] = 7, 645 [IRQ_DA8XX_TINT34_0] = 7, 646 [IRQ_DA8XX_TINT12_1] = 7, 647 [IRQ_DA8XX_TINT34_1] = 7, 648 [IRQ_DA8XX_UARTINT0] = 7, 649 [IRQ_DA8XX_KEYMGRINT] = 7, 650 [IRQ_DA850_MPUADDRERR0] = 7, 651 [IRQ_DA8XX_CHIPINT0] = 7, 652 [IRQ_DA8XX_CHIPINT1] = 7, 653 [IRQ_DA8XX_CHIPINT2] = 7, 654 [IRQ_DA8XX_CHIPINT3] = 7, 655 [IRQ_DA8XX_TCERRINT1] = 7, 656 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, 657 [IRQ_DA8XX_C0_RX_PULSE] = 7, 658 [IRQ_DA8XX_C0_TX_PULSE] = 7, 659 [IRQ_DA8XX_C0_MISC_PULSE] = 7, 660 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, 661 [IRQ_DA8XX_C1_RX_PULSE] = 7, 662 [IRQ_DA8XX_C1_TX_PULSE] = 7, 663 [IRQ_DA8XX_C1_MISC_PULSE] = 7, 664 [IRQ_DA8XX_MEMERR] = 7, 665 [IRQ_DA8XX_GPIO0] = 7, 666 [IRQ_DA8XX_GPIO1] = 7, 667 [IRQ_DA8XX_GPIO2] = 7, 668 [IRQ_DA8XX_GPIO3] = 7, 669 [IRQ_DA8XX_GPIO4] = 7, 670 [IRQ_DA8XX_GPIO5] = 7, 671 [IRQ_DA8XX_GPIO6] = 7, 672 [IRQ_DA8XX_GPIO7] = 7, 673 [IRQ_DA8XX_GPIO8] = 7, 674 [IRQ_DA8XX_I2CINT1] = 7, 675 [IRQ_DA8XX_LCDINT] = 7, 676 [IRQ_DA8XX_UARTINT1] = 7, 677 [IRQ_DA8XX_MCASPINT] = 7, 678 [IRQ_DA8XX_ALLINT1] = 7, 679 [IRQ_DA8XX_SPINT1] = 7, 680 [IRQ_DA8XX_UHPI_INT1] = 7, 681 [IRQ_DA8XX_USB_INT] = 7, 682 [IRQ_DA8XX_IRQN] = 7, 683 [IRQ_DA8XX_RWAKEUP] = 7, 684 [IRQ_DA8XX_UARTINT2] = 7, 685 [IRQ_DA8XX_DFTSSINT] = 7, 686 [IRQ_DA8XX_EHRPWM0] = 7, 687 [IRQ_DA8XX_EHRPWM0TZ] = 7, 688 [IRQ_DA8XX_EHRPWM1] = 7, 689 [IRQ_DA8XX_EHRPWM1TZ] = 7, 690 [IRQ_DA850_SATAINT] = 7, 691 [IRQ_DA850_TINTALL_2] = 7, 692 [IRQ_DA8XX_ECAP0] = 7, 693 [IRQ_DA8XX_ECAP1] = 7, 694 [IRQ_DA8XX_ECAP2] = 7, 695 [IRQ_DA850_MMCSDINT0_1] = 7, 696 [IRQ_DA850_MMCSDINT1_1] = 7, 697 [IRQ_DA850_T12CMPINT0_2] = 7, 698 [IRQ_DA850_T12CMPINT1_2] = 7, 699 [IRQ_DA850_T12CMPINT2_2] = 7, 700 [IRQ_DA850_T12CMPINT3_2] = 7, 701 [IRQ_DA850_T12CMPINT4_2] = 7, 702 [IRQ_DA850_T12CMPINT5_2] = 7, 703 [IRQ_DA850_T12CMPINT6_2] = 7, 704 [IRQ_DA850_T12CMPINT7_2] = 7, 705 [IRQ_DA850_T12CMPINT0_3] = 7, 706 [IRQ_DA850_T12CMPINT1_3] = 7, 707 [IRQ_DA850_T12CMPINT2_3] = 7, 708 [IRQ_DA850_T12CMPINT3_3] = 7, 709 [IRQ_DA850_T12CMPINT4_3] = 7, 710 [IRQ_DA850_T12CMPINT5_3] = 7, 711 [IRQ_DA850_T12CMPINT6_3] = 7, 712 [IRQ_DA850_T12CMPINT7_3] = 7, 713 [IRQ_DA850_RPIINT] = 7, 714 [IRQ_DA850_VPIFINT] = 7, 715 [IRQ_DA850_CCINT1] = 7, 716 [IRQ_DA850_CCERRINT1] = 7, 717 [IRQ_DA850_TCERRINT2] = 7, 718 [IRQ_DA850_TINTALL_3] = 7, 719 [IRQ_DA850_MCBSP0RINT] = 7, 720 [IRQ_DA850_MCBSP0XINT] = 7, 721 [IRQ_DA850_MCBSP1RINT] = 7, 722 [IRQ_DA850_MCBSP1XINT] = 7, 723 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, 724 }; 725 726 static struct map_desc da850_io_desc[] = { 727 { 728 .virtual = IO_VIRT, 729 .pfn = __phys_to_pfn(IO_PHYS), 730 .length = IO_SIZE, 731 .type = MT_DEVICE 732 }, 733 { 734 .virtual = DA8XX_CP_INTC_VIRT, 735 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), 736 .length = DA8XX_CP_INTC_SIZE, 737 .type = MT_DEVICE 738 }, 739 { 740 .virtual = SRAM_VIRT, 741 .pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE), 742 .length = SZ_8K, 743 .type = MT_DEVICE 744 }, 745 }; 746 747 static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE }; 748 749 /* Contents of JTAG ID register used to identify exact cpu type */ 750 static struct davinci_id da850_ids[] = { 751 { 752 .variant = 0x0, 753 .part_no = 0xb7d1, 754 .manufacturer = 0x017, /* 0x02f >> 1 */ 755 .cpu_id = DAVINCI_CPU_ID_DA850, 756 .name = "da850/omap-l138", 757 }, 758 { 759 .variant = 0x1, 760 .part_no = 0xb7d1, 761 .manufacturer = 0x017, /* 0x02f >> 1 */ 762 .cpu_id = DAVINCI_CPU_ID_DA850, 763 .name = "da850/omap-l138/am18x", 764 }, 765 }; 766 767 static struct davinci_timer_instance da850_timer_instance[4] = { 768 { 769 .base = DA8XX_TIMER64P0_BASE, 770 .bottom_irq = IRQ_DA8XX_TINT12_0, 771 .top_irq = IRQ_DA8XX_TINT34_0, 772 }, 773 { 774 .base = DA8XX_TIMER64P1_BASE, 775 .bottom_irq = IRQ_DA8XX_TINT12_1, 776 .top_irq = IRQ_DA8XX_TINT34_1, 777 }, 778 { 779 .base = DA850_TIMER64P2_BASE, 780 .bottom_irq = IRQ_DA850_TINT12_2, 781 .top_irq = IRQ_DA850_TINT34_2, 782 }, 783 { 784 .base = DA850_TIMER64P3_BASE, 785 .bottom_irq = IRQ_DA850_TINT12_3, 786 .top_irq = IRQ_DA850_TINT34_3, 787 }, 788 }; 789 790 /* 791 * T0_BOT: Timer 0, bottom : Used for clock_event 792 * T0_TOP: Timer 0, top : Used for clocksource 793 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer 794 */ 795 static struct davinci_timer_info da850_timer_info = { 796 .timers = da850_timer_instance, 797 .clockevent_id = T0_BOT, 798 .clocksource_id = T0_TOP, 799 }; 800 801 static void da850_set_async3_src(int pllnum) 802 { 803 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2; 804 struct clk_lookup *c; 805 unsigned int v; 806 int ret; 807 808 for (c = da850_clks; c->clk; c++) { 809 clk = c->clk; 810 if (clk->flags & DA850_CLK_ASYNC3) { 811 ret = clk_set_parent(clk, newparent); 812 WARN(ret, "DA850: unable to re-parent clock %s", 813 clk->name); 814 } 815 } 816 817 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); 818 if (pllnum) 819 v |= CFGCHIP3_ASYNC3_CLKSRC; 820 else 821 v &= ~CFGCHIP3_ASYNC3_CLKSRC; 822 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); 823 } 824 825 #ifdef CONFIG_CPU_FREQ 826 /* 827 * Notes: 828 * According to the TRM, minimum PLLM results in maximum power savings. 829 * The OPP definitions below should keep the PLLM as low as possible. 830 * 831 * The output of the PLLM must be between 300 to 600 MHz. 832 */ 833 struct da850_opp { 834 unsigned int freq; /* in KHz */ 835 unsigned int prediv; 836 unsigned int mult; 837 unsigned int postdiv; 838 unsigned int cvdd_min; /* in uV */ 839 unsigned int cvdd_max; /* in uV */ 840 }; 841 842 static const struct da850_opp da850_opp_456 = { 843 .freq = 456000, 844 .prediv = 1, 845 .mult = 19, 846 .postdiv = 1, 847 .cvdd_min = 1300000, 848 .cvdd_max = 1350000, 849 }; 850 851 static const struct da850_opp da850_opp_408 = { 852 .freq = 408000, 853 .prediv = 1, 854 .mult = 17, 855 .postdiv = 1, 856 .cvdd_min = 1300000, 857 .cvdd_max = 1350000, 858 }; 859 860 static const struct da850_opp da850_opp_372 = { 861 .freq = 372000, 862 .prediv = 2, 863 .mult = 31, 864 .postdiv = 1, 865 .cvdd_min = 1200000, 866 .cvdd_max = 1320000, 867 }; 868 869 static const struct da850_opp da850_opp_300 = { 870 .freq = 300000, 871 .prediv = 1, 872 .mult = 25, 873 .postdiv = 2, 874 .cvdd_min = 1200000, 875 .cvdd_max = 1320000, 876 }; 877 878 static const struct da850_opp da850_opp_200 = { 879 .freq = 200000, 880 .prediv = 1, 881 .mult = 25, 882 .postdiv = 3, 883 .cvdd_min = 1100000, 884 .cvdd_max = 1160000, 885 }; 886 887 static const struct da850_opp da850_opp_96 = { 888 .freq = 96000, 889 .prediv = 1, 890 .mult = 20, 891 .postdiv = 5, 892 .cvdd_min = 1000000, 893 .cvdd_max = 1050000, 894 }; 895 896 #define OPP(freq) \ 897 { \ 898 .index = (unsigned int) &da850_opp_##freq, \ 899 .frequency = freq * 1000, \ 900 } 901 902 static struct cpufreq_frequency_table da850_freq_table[] = { 903 OPP(456), 904 OPP(408), 905 OPP(372), 906 OPP(300), 907 OPP(200), 908 OPP(96), 909 { 910 .index = 0, 911 .frequency = CPUFREQ_TABLE_END, 912 }, 913 }; 914 915 #ifdef CONFIG_REGULATOR 916 static int da850_set_voltage(unsigned int index); 917 static int da850_regulator_init(void); 918 #endif 919 920 static struct davinci_cpufreq_config cpufreq_info = { 921 .freq_table = da850_freq_table, 922 #ifdef CONFIG_REGULATOR 923 .init = da850_regulator_init, 924 .set_voltage = da850_set_voltage, 925 #endif 926 }; 927 928 #ifdef CONFIG_REGULATOR 929 static struct regulator *cvdd; 930 931 static int da850_set_voltage(unsigned int index) 932 { 933 struct da850_opp *opp; 934 935 if (!cvdd) 936 return -ENODEV; 937 938 opp = (struct da850_opp *) cpufreq_info.freq_table[index].index; 939 940 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); 941 } 942 943 static int da850_regulator_init(void) 944 { 945 cvdd = regulator_get(NULL, "cvdd"); 946 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;" 947 " voltage scaling unsupported\n")) { 948 return PTR_ERR(cvdd); 949 } 950 951 return 0; 952 } 953 #endif 954 955 static struct platform_device da850_cpufreq_device = { 956 .name = "cpufreq-davinci", 957 .dev = { 958 .platform_data = &cpufreq_info, 959 }, 960 .id = -1, 961 }; 962 963 unsigned int da850_max_speed = 300000; 964 965 int __init da850_register_cpufreq(char *async_clk) 966 { 967 int i; 968 969 /* cpufreq driver can help keep an "async" clock constant */ 970 if (async_clk) 971 clk_add_alias("async", da850_cpufreq_device.name, 972 async_clk, NULL); 973 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) { 974 if (da850_freq_table[i].frequency <= da850_max_speed) { 975 cpufreq_info.freq_table = &da850_freq_table[i]; 976 break; 977 } 978 } 979 980 return platform_device_register(&da850_cpufreq_device); 981 } 982 983 static int da850_round_armrate(struct clk *clk, unsigned long rate) 984 { 985 int i, ret = 0, diff; 986 unsigned int best = (unsigned int) -1; 987 struct cpufreq_frequency_table *table = cpufreq_info.freq_table; 988 989 rate /= 1000; /* convert to kHz */ 990 991 for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) { 992 diff = table[i].frequency - rate; 993 if (diff < 0) 994 diff = -diff; 995 996 if (diff < best) { 997 best = diff; 998 ret = table[i].frequency; 999 } 1000 } 1001 1002 return ret * 1000; 1003 } 1004 1005 static int da850_set_armrate(struct clk *clk, unsigned long index) 1006 { 1007 struct clk *pllclk = &pll0_clk; 1008 1009 return clk_set_rate(pllclk, index); 1010 } 1011 1012 static int da850_set_pll0rate(struct clk *clk, unsigned long index) 1013 { 1014 unsigned int prediv, mult, postdiv; 1015 struct da850_opp *opp; 1016 struct pll_data *pll = clk->pll_data; 1017 int ret; 1018 1019 opp = (struct da850_opp *) cpufreq_info.freq_table[index].index; 1020 prediv = opp->prediv; 1021 mult = opp->mult; 1022 postdiv = opp->postdiv; 1023 1024 ret = davinci_set_pllrate(pll, prediv, mult, postdiv); 1025 if (WARN_ON(ret)) 1026 return ret; 1027 1028 return 0; 1029 } 1030 #else 1031 int __init da850_register_cpufreq(char *async_clk) 1032 { 1033 return 0; 1034 } 1035 1036 static int da850_set_armrate(struct clk *clk, unsigned long rate) 1037 { 1038 return -EINVAL; 1039 } 1040 1041 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate) 1042 { 1043 return -EINVAL; 1044 } 1045 1046 static int da850_round_armrate(struct clk *clk, unsigned long rate) 1047 { 1048 return clk->rate; 1049 } 1050 #endif 1051 1052 int da850_register_pm(struct platform_device *pdev) 1053 { 1054 int ret; 1055 struct davinci_pm_config *pdata = pdev->dev.platform_data; 1056 1057 ret = davinci_cfg_reg(DA850_RTC_ALARM); 1058 if (ret) 1059 return ret; 1060 1061 pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr(); 1062 pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG); 1063 pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C; 1064 1065 pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K); 1066 if (!pdata->cpupll_reg_base) 1067 return -ENOMEM; 1068 1069 pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K); 1070 if (!pdata->ddrpll_reg_base) { 1071 ret = -ENOMEM; 1072 goto no_ddrpll_mem; 1073 } 1074 1075 pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K); 1076 if (!pdata->ddrpsc_reg_base) { 1077 ret = -ENOMEM; 1078 goto no_ddrpsc_mem; 1079 } 1080 1081 return platform_device_register(pdev); 1082 1083 no_ddrpsc_mem: 1084 iounmap(pdata->ddrpll_reg_base); 1085 no_ddrpll_mem: 1086 iounmap(pdata->cpupll_reg_base); 1087 return ret; 1088 } 1089 1090 static struct davinci_soc_info davinci_soc_info_da850 = { 1091 .io_desc = da850_io_desc, 1092 .io_desc_num = ARRAY_SIZE(da850_io_desc), 1093 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, 1094 .ids = da850_ids, 1095 .ids_num = ARRAY_SIZE(da850_ids), 1096 .cpu_clks = da850_clks, 1097 .psc_bases = da850_psc_bases, 1098 .psc_bases_num = ARRAY_SIZE(da850_psc_bases), 1099 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, 1100 .pinmux_pins = da850_pins, 1101 .pinmux_pins_num = ARRAY_SIZE(da850_pins), 1102 .intc_base = DA8XX_CP_INTC_BASE, 1103 .intc_type = DAVINCI_INTC_TYPE_CP_INTC, 1104 .intc_irq_prios = da850_default_priorities, 1105 .intc_irq_num = DA850_N_CP_INTC_IRQ, 1106 .timer_info = &da850_timer_info, 1107 .gpio_type = GPIO_TYPE_DAVINCI, 1108 .gpio_base = DA8XX_GPIO_BASE, 1109 .gpio_num = 144, 1110 .gpio_irq = IRQ_DA8XX_GPIO0, 1111 .serial_dev = &da8xx_serial_device, 1112 .emac_pdata = &da8xx_emac_pdata, 1113 .sram_dma = DA8XX_ARM_RAM_BASE, 1114 .sram_len = SZ_8K, 1115 .reset_device = &da8xx_wdt_device, 1116 }; 1117 1118 void __init da850_init(void) 1119 { 1120 unsigned int v; 1121 1122 davinci_common_init(&davinci_soc_info_da850); 1123 1124 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); 1125 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module")) 1126 return; 1127 1128 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K); 1129 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module")) 1130 return; 1131 1132 /* 1133 * Move the clock source of Async3 domain to PLL1 SYSCLK2. 1134 * This helps keeping the peripherals on this domain insulated 1135 * from CPU frequency changes caused by DVFS. The firmware sets 1136 * both PLL0 and PLL1 to the same frequency so, there should not 1137 * be any noticeable change even in non-DVFS use cases. 1138 */ 1139 da850_set_async3_src(1); 1140 1141 /* Unlock writing to PLL0 registers */ 1142 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG)); 1143 v &= ~CFGCHIP0_PLL_MASTER_LOCK; 1144 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG)); 1145 1146 /* Unlock writing to PLL1 registers */ 1147 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); 1148 v &= ~CFGCHIP3_PLL1_MASTER_LOCK; 1149 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); 1150 } 1151