1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * TI DA850/OMAP-L138 chip specific setup 4 * 5 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/ 6 * 7 * Derived from: arch/arm/mach-davinci/da830.c 8 * Original Copyrights follow: 9 * 10 * 2009 (c) MontaVista Software, Inc. 11 */ 12 13 #include <linux/clk-provider.h> 14 #include <linux/clk/davinci.h> 15 #include <linux/clkdev.h> 16 #include <linux/cpufreq.h> 17 #include <linux/gpio.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/irqchip/irq-davinci-cp-intc.h> 21 #include <linux/mfd/da8xx-cfgchip.h> 22 #include <linux/platform_data/clk-da8xx-cfgchip.h> 23 #include <linux/platform_data/clk-davinci-pll.h> 24 #include <linux/platform_data/davinci-cpufreq.h> 25 #include <linux/platform_data/gpio-davinci.h> 26 #include <linux/platform_device.h> 27 #include <linux/regmap.h> 28 #include <linux/regulator/consumer.h> 29 #include <clocksource/timer-davinci.h> 30 31 #include <asm/mach/map.h> 32 33 #include "common.h" 34 #include "cputype.h" 35 #include "da8xx.h" 36 #include "pm.h" 37 #include "irqs.h" 38 #include "mux.h" 39 40 #define DA850_PLL1_BASE 0x01e1a000 41 #define DA850_TIMER64P2_BASE 0x01f0c000 42 #define DA850_TIMER64P3_BASE 0x01f0d000 43 44 #define DA850_REF_FREQ 24000000 45 46 /* 47 * Device specific mux setup 48 * 49 * soc description mux mode mode mux dbg 50 * reg offset mask mode 51 */ 52 static const struct mux_config da850_pins[] = { 53 #ifdef CONFIG_DAVINCI_MUX 54 /* UART0 function */ 55 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false) 56 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false) 57 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false) 58 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false) 59 /* UART1 function */ 60 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false) 61 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false) 62 /* UART2 function */ 63 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false) 64 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false) 65 /* I2C1 function */ 66 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false) 67 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false) 68 /* I2C0 function */ 69 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) 70 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) 71 /* EMAC function */ 72 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false) 73 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false) 74 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false) 75 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false) 76 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false) 77 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false) 78 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false) 79 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false) 80 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false) 81 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false) 82 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false) 83 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false) 84 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false) 85 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false) 86 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) 87 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) 88 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) 89 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false) 90 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false) 91 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false) 92 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false) 93 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false) 94 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false) 95 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false) 96 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false) 97 /* McASP function */ 98 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false) 99 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false) 100 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false) 101 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false) 102 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false) 103 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false) 104 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false) 105 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false) 106 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false) 107 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false) 108 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false) 109 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false) 110 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false) 111 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false) 112 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false) 113 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false) 114 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false) 115 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false) 116 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false) 117 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false) 118 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false) 119 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false) 120 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false) 121 /* LCD function */ 122 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false) 123 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false) 124 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false) 125 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false) 126 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false) 127 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false) 128 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false) 129 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false) 130 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false) 131 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false) 132 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false) 133 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false) 134 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false) 135 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false) 136 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false) 137 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false) 138 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false) 139 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false) 140 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false) 141 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false) 142 /* MMC/SD0 function */ 143 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false) 144 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false) 145 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false) 146 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false) 147 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false) 148 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false) 149 /* MMC/SD1 function */ 150 MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false) 151 MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false) 152 MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false) 153 MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false) 154 MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false) 155 MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false) 156 /* EMIF2.5/EMIFA function */ 157 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false) 158 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false) 159 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false) 160 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false) 161 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false) 162 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false) 163 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false) 164 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false) 165 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false) 166 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false) 167 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false) 168 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false) 169 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false) 170 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false) 171 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false) 172 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false) 173 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false) 174 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false) 175 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false) 176 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false) 177 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false) 178 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false) 179 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false) 180 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false) 181 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false) 182 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false) 183 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false) 184 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false) 185 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false) 186 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false) 187 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false) 188 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false) 189 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false) 190 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false) 191 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false) 192 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false) 193 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false) 194 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false) 195 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false) 196 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false) 197 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false) 198 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false) 199 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false) 200 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false) 201 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false) 202 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false) 203 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false) 204 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false) 205 /* GPIO function */ 206 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false) 207 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false) 208 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false) 209 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) 210 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false) 211 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false) 212 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) 213 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) 214 MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false) 215 MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false) 216 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false) 217 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false) 218 /* VPIF Capture */ 219 MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false) 220 MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false) 221 MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false) 222 MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false) 223 MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false) 224 MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false) 225 MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false) 226 MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false) 227 MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false) 228 MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false) 229 MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false) 230 MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false) 231 MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false) 232 MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false) 233 MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false) 234 MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false) 235 MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false) 236 MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false) 237 MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false) 238 MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false) 239 /* VPIF Display */ 240 MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false) 241 MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false) 242 MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false) 243 MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false) 244 MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false) 245 MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false) 246 MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false) 247 MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false) 248 MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false) 249 MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false) 250 MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false) 251 MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false) 252 MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false) 253 MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false) 254 MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false) 255 MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false) 256 MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false) 257 MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false) 258 #endif 259 }; 260 261 const short da850_i2c0_pins[] __initconst = { 262 DA850_I2C0_SDA, DA850_I2C0_SCL, 263 -1 264 }; 265 266 const short da850_i2c1_pins[] __initconst = { 267 DA850_I2C1_SCL, DA850_I2C1_SDA, 268 -1 269 }; 270 271 const short da850_lcdcntl_pins[] __initconst = { 272 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, 273 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, 274 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, 275 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, 276 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, 277 -1 278 }; 279 280 const short da850_vpif_capture_pins[] __initconst = { 281 DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3, 282 DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7, 283 DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11, 284 DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15, 285 DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2, 286 DA850_VPIF_CLKIN3, 287 -1 288 }; 289 290 const short da850_vpif_display_pins[] __initconst = { 291 DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3, 292 DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7, 293 DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10, 294 DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13, 295 DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2, 296 DA850_VPIF_CLKO3, 297 -1 298 }; 299 300 static struct map_desc da850_io_desc[] = { 301 { 302 .virtual = IO_VIRT, 303 .pfn = __phys_to_pfn(IO_PHYS), 304 .length = IO_SIZE, 305 .type = MT_DEVICE 306 }, 307 { 308 .virtual = DA8XX_CP_INTC_VIRT, 309 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), 310 .length = DA8XX_CP_INTC_SIZE, 311 .type = MT_DEVICE 312 }, 313 }; 314 315 /* Contents of JTAG ID register used to identify exact cpu type */ 316 static struct davinci_id da850_ids[] = { 317 { 318 .variant = 0x0, 319 .part_no = 0xb7d1, 320 .manufacturer = 0x017, /* 0x02f >> 1 */ 321 .cpu_id = DAVINCI_CPU_ID_DA850, 322 .name = "da850/omap-l138", 323 }, 324 { 325 .variant = 0x1, 326 .part_no = 0xb7d1, 327 .manufacturer = 0x017, /* 0x02f >> 1 */ 328 .cpu_id = DAVINCI_CPU_ID_DA850, 329 .name = "da850/omap-l138/am18x", 330 }, 331 }; 332 333 /* 334 * Bottom half of timer 0 is used for clock_event, top half for 335 * clocksource. 336 */ 337 static const struct davinci_timer_cfg da850_timer_cfg = { 338 .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K), 339 .irq = { 340 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)), 341 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)), 342 }, 343 }; 344 345 #ifdef CONFIG_CPU_FREQ 346 /* 347 * Notes: 348 * According to the TRM, minimum PLLM results in maximum power savings. 349 * The OPP definitions below should keep the PLLM as low as possible. 350 * 351 * The output of the PLLM must be between 300 to 600 MHz. 352 */ 353 struct da850_opp { 354 unsigned int freq; /* in KHz */ 355 unsigned int prediv; 356 unsigned int mult; 357 unsigned int postdiv; 358 unsigned int cvdd_min; /* in uV */ 359 unsigned int cvdd_max; /* in uV */ 360 }; 361 362 static const struct da850_opp da850_opp_456 = { 363 .freq = 456000, 364 .prediv = 1, 365 .mult = 19, 366 .postdiv = 1, 367 .cvdd_min = 1300000, 368 .cvdd_max = 1350000, 369 }; 370 371 static const struct da850_opp da850_opp_408 = { 372 .freq = 408000, 373 .prediv = 1, 374 .mult = 17, 375 .postdiv = 1, 376 .cvdd_min = 1300000, 377 .cvdd_max = 1350000, 378 }; 379 380 static const struct da850_opp da850_opp_372 = { 381 .freq = 372000, 382 .prediv = 2, 383 .mult = 31, 384 .postdiv = 1, 385 .cvdd_min = 1200000, 386 .cvdd_max = 1320000, 387 }; 388 389 static const struct da850_opp da850_opp_300 = { 390 .freq = 300000, 391 .prediv = 1, 392 .mult = 25, 393 .postdiv = 2, 394 .cvdd_min = 1200000, 395 .cvdd_max = 1320000, 396 }; 397 398 static const struct da850_opp da850_opp_200 = { 399 .freq = 200000, 400 .prediv = 1, 401 .mult = 25, 402 .postdiv = 3, 403 .cvdd_min = 1100000, 404 .cvdd_max = 1160000, 405 }; 406 407 static const struct da850_opp da850_opp_96 = { 408 .freq = 96000, 409 .prediv = 1, 410 .mult = 20, 411 .postdiv = 5, 412 .cvdd_min = 1000000, 413 .cvdd_max = 1050000, 414 }; 415 416 #define OPP(freq) \ 417 { \ 418 .driver_data = (unsigned int) &da850_opp_##freq, \ 419 .frequency = freq * 1000, \ 420 } 421 422 static struct cpufreq_frequency_table da850_freq_table[] = { 423 OPP(456), 424 OPP(408), 425 OPP(372), 426 OPP(300), 427 OPP(200), 428 OPP(96), 429 { 430 .driver_data = 0, 431 .frequency = CPUFREQ_TABLE_END, 432 }, 433 }; 434 435 #ifdef CONFIG_REGULATOR 436 static int da850_set_voltage(unsigned int index); 437 static int da850_regulator_init(void); 438 #endif 439 440 static struct davinci_cpufreq_config cpufreq_info = { 441 .freq_table = da850_freq_table, 442 #ifdef CONFIG_REGULATOR 443 .init = da850_regulator_init, 444 .set_voltage = da850_set_voltage, 445 #endif 446 }; 447 448 #ifdef CONFIG_REGULATOR 449 static struct regulator *cvdd; 450 451 static int da850_set_voltage(unsigned int index) 452 { 453 struct da850_opp *opp; 454 455 if (!cvdd) 456 return -ENODEV; 457 458 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data; 459 460 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); 461 } 462 463 static int da850_regulator_init(void) 464 { 465 cvdd = regulator_get(NULL, "cvdd"); 466 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;" 467 " voltage scaling unsupported\n")) { 468 return PTR_ERR(cvdd); 469 } 470 471 return 0; 472 } 473 #endif 474 475 static struct platform_device da850_cpufreq_device = { 476 .name = "cpufreq-davinci", 477 .dev = { 478 .platform_data = &cpufreq_info, 479 }, 480 .id = -1, 481 }; 482 483 unsigned int da850_max_speed = 300000; 484 485 int da850_register_cpufreq(char *async_clk) 486 { 487 int i; 488 489 /* cpufreq driver can help keep an "async" clock constant */ 490 if (async_clk) 491 clk_add_alias("async", da850_cpufreq_device.name, 492 async_clk, NULL); 493 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) { 494 if (da850_freq_table[i].frequency <= da850_max_speed) { 495 cpufreq_info.freq_table = &da850_freq_table[i]; 496 break; 497 } 498 } 499 500 return platform_device_register(&da850_cpufreq_device); 501 } 502 #else 503 int __init da850_register_cpufreq(char *async_clk) 504 { 505 return 0; 506 } 507 #endif 508 509 /* VPIF resource, platform data */ 510 static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32); 511 512 static struct resource da850_vpif_resource[] = { 513 { 514 .start = DA8XX_VPIF_BASE, 515 .end = DA8XX_VPIF_BASE + 0xfff, 516 .flags = IORESOURCE_MEM, 517 } 518 }; 519 520 static struct platform_device da850_vpif_dev = { 521 .name = "vpif", 522 .id = -1, 523 .dev = { 524 .dma_mask = &da850_vpif_dma_mask, 525 .coherent_dma_mask = DMA_BIT_MASK(32), 526 }, 527 .resource = da850_vpif_resource, 528 .num_resources = ARRAY_SIZE(da850_vpif_resource), 529 }; 530 531 static struct resource da850_vpif_display_resource[] = { 532 { 533 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 534 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 535 .flags = IORESOURCE_IRQ, 536 }, 537 }; 538 539 static struct platform_device da850_vpif_display_dev = { 540 .name = "vpif_display", 541 .id = -1, 542 .dev = { 543 .dma_mask = &da850_vpif_dma_mask, 544 .coherent_dma_mask = DMA_BIT_MASK(32), 545 }, 546 .resource = da850_vpif_display_resource, 547 .num_resources = ARRAY_SIZE(da850_vpif_display_resource), 548 }; 549 550 static struct resource da850_vpif_capture_resource[] = { 551 { 552 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 553 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 554 .flags = IORESOURCE_IRQ, 555 }, 556 { 557 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 558 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 559 .flags = IORESOURCE_IRQ, 560 }, 561 }; 562 563 static struct platform_device da850_vpif_capture_dev = { 564 .name = "vpif_capture", 565 .id = -1, 566 .dev = { 567 .dma_mask = &da850_vpif_dma_mask, 568 .coherent_dma_mask = DMA_BIT_MASK(32), 569 }, 570 .resource = da850_vpif_capture_resource, 571 .num_resources = ARRAY_SIZE(da850_vpif_capture_resource), 572 }; 573 574 int __init da850_register_vpif(void) 575 { 576 return platform_device_register(&da850_vpif_dev); 577 } 578 579 int __init da850_register_vpif_display(struct vpif_display_config 580 *display_config) 581 { 582 da850_vpif_display_dev.dev.platform_data = display_config; 583 return platform_device_register(&da850_vpif_display_dev); 584 } 585 586 int __init da850_register_vpif_capture(struct vpif_capture_config 587 *capture_config) 588 { 589 da850_vpif_capture_dev.dev.platform_data = capture_config; 590 return platform_device_register(&da850_vpif_capture_dev); 591 } 592 593 static struct davinci_gpio_platform_data da850_gpio_platform_data = { 594 .no_auto_base = true, 595 .base = 0, 596 .ngpio = 144, 597 }; 598 599 int __init da850_register_gpio(void) 600 { 601 return da8xx_register_gpio(&da850_gpio_platform_data); 602 } 603 604 static const struct davinci_soc_info davinci_soc_info_da850 = { 605 .io_desc = da850_io_desc, 606 .io_desc_num = ARRAY_SIZE(da850_io_desc), 607 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, 608 .ids = da850_ids, 609 .ids_num = ARRAY_SIZE(da850_ids), 610 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, 611 .pinmux_pins = da850_pins, 612 .pinmux_pins_num = ARRAY_SIZE(da850_pins), 613 .emac_pdata = &da8xx_emac_pdata, 614 .sram_dma = DA8XX_SHARED_RAM_BASE, 615 .sram_len = SZ_128K, 616 }; 617 618 void __init da850_init(void) 619 { 620 davinci_common_init(&davinci_soc_info_da850); 621 622 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); 623 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module")) 624 return; 625 626 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K); 627 WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"); 628 } 629 630 static const struct davinci_cp_intc_config da850_cp_intc_config = { 631 .reg = { 632 .start = DA8XX_CP_INTC_BASE, 633 .end = DA8XX_CP_INTC_BASE + SZ_8K - 1, 634 .flags = IORESOURCE_MEM, 635 }, 636 .num_irqs = DA850_N_CP_INTC_IRQ, 637 }; 638 639 void __init da850_init_irq(void) 640 { 641 davinci_cp_intc_init(&da850_cp_intc_config); 642 } 643 644 void __init da850_init_time(void) 645 { 646 void __iomem *pll0; 647 struct regmap *cfgchip; 648 struct clk *clk; 649 int rv; 650 651 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ); 652 653 pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K); 654 cfgchip = da8xx_get_cfgchip(); 655 656 da850_pll0_init(NULL, pll0, cfgchip); 657 658 clk = clk_get(NULL, "timer0"); 659 if (WARN_ON(IS_ERR(clk))) { 660 pr_err("Unable to get the timer clock\n"); 661 return; 662 } 663 664 rv = davinci_timer_register(clk, &da850_timer_cfg); 665 WARN(rv, "Unable to register the timer: %d\n", rv); 666 } 667 668 static struct resource da850_pll1_resources[] = { 669 { 670 .start = DA850_PLL1_BASE, 671 .end = DA850_PLL1_BASE + SZ_4K - 1, 672 .flags = IORESOURCE_MEM, 673 }, 674 }; 675 676 static struct davinci_pll_platform_data da850_pll1_pdata; 677 678 static struct platform_device da850_pll1_device = { 679 .name = "da850-pll1", 680 .id = -1, 681 .resource = da850_pll1_resources, 682 .num_resources = ARRAY_SIZE(da850_pll1_resources), 683 .dev = { 684 .platform_data = &da850_pll1_pdata, 685 }, 686 }; 687 688 static struct resource da850_psc0_resources[] = { 689 { 690 .start = DA8XX_PSC0_BASE, 691 .end = DA8XX_PSC0_BASE + SZ_4K - 1, 692 .flags = IORESOURCE_MEM, 693 }, 694 }; 695 696 static struct platform_device da850_psc0_device = { 697 .name = "da850-psc0", 698 .id = -1, 699 .resource = da850_psc0_resources, 700 .num_resources = ARRAY_SIZE(da850_psc0_resources), 701 }; 702 703 static struct resource da850_psc1_resources[] = { 704 { 705 .start = DA8XX_PSC1_BASE, 706 .end = DA8XX_PSC1_BASE + SZ_4K - 1, 707 .flags = IORESOURCE_MEM, 708 }, 709 }; 710 711 static struct platform_device da850_psc1_device = { 712 .name = "da850-psc1", 713 .id = -1, 714 .resource = da850_psc1_resources, 715 .num_resources = ARRAY_SIZE(da850_psc1_resources), 716 }; 717 718 static struct da8xx_cfgchip_clk_platform_data da850_async1_pdata; 719 720 static struct platform_device da850_async1_clksrc_device = { 721 .name = "da850-async1-clksrc", 722 .id = -1, 723 .dev = { 724 .platform_data = &da850_async1_pdata, 725 }, 726 }; 727 728 static struct da8xx_cfgchip_clk_platform_data da850_async3_pdata; 729 730 static struct platform_device da850_async3_clksrc_device = { 731 .name = "da850-async3-clksrc", 732 .id = -1, 733 .dev = { 734 .platform_data = &da850_async3_pdata, 735 }, 736 }; 737 738 static struct da8xx_cfgchip_clk_platform_data da850_tbclksync_pdata; 739 740 static struct platform_device da850_tbclksync_device = { 741 .name = "da830-tbclksync", 742 .id = -1, 743 .dev = { 744 .platform_data = &da850_tbclksync_pdata, 745 }, 746 }; 747 748 void __init da850_register_clocks(void) 749 { 750 /* PLL0 is registered in da850_init_time() */ 751 752 da850_pll1_pdata.cfgchip = da8xx_get_cfgchip(); 753 platform_device_register(&da850_pll1_device); 754 755 da850_async1_pdata.cfgchip = da8xx_get_cfgchip(); 756 platform_device_register(&da850_async1_clksrc_device); 757 758 da850_async3_pdata.cfgchip = da8xx_get_cfgchip(); 759 platform_device_register(&da850_async3_clksrc_device); 760 761 platform_device_register(&da850_psc0_device); 762 763 platform_device_register(&da850_psc1_device); 764 765 da850_tbclksync_pdata.cfgchip = da8xx_get_cfgchip(); 766 platform_device_register(&da850_tbclksync_device); 767 } 768