1 /* 2 * TI DA850/OMAP-L138 chip specific setup 3 * 4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * Derived from: arch/arm/mach-davinci/da830.c 7 * Original Copyrights follow: 8 * 9 * 2009 (c) MontaVista Software, Inc. This file is licensed under 10 * the terms of the GNU General Public License version 2. This program 11 * is licensed "as is" without any warranty of any kind, whether express 12 * or implied. 13 */ 14 15 #include <linux/clk-provider.h> 16 #include <linux/clk/davinci.h> 17 #include <linux/clkdev.h> 18 #include <linux/cpufreq.h> 19 #include <linux/gpio.h> 20 #include <linux/init.h> 21 #include <linux/irqchip/irq-davinci-cp-intc.h> 22 #include <linux/mfd/da8xx-cfgchip.h> 23 #include <linux/platform_data/clk-da8xx-cfgchip.h> 24 #include <linux/platform_data/clk-davinci-pll.h> 25 #include <linux/platform_data/gpio-davinci.h> 26 #include <linux/platform_device.h> 27 #include <linux/regmap.h> 28 #include <linux/regulator/consumer.h> 29 30 #include <asm/mach/map.h> 31 32 #include <mach/common.h> 33 #include <mach/cpufreq.h> 34 #include <mach/cputype.h> 35 #include <mach/da8xx.h> 36 #include <mach/pm.h> 37 #include <mach/time.h> 38 39 #include "irqs.h" 40 #include "mux.h" 41 42 #define DA850_PLL1_BASE 0x01e1a000 43 #define DA850_TIMER64P2_BASE 0x01f0c000 44 #define DA850_TIMER64P3_BASE 0x01f0d000 45 46 #define DA850_REF_FREQ 24000000 47 48 /* 49 * Device specific mux setup 50 * 51 * soc description mux mode mode mux dbg 52 * reg offset mask mode 53 */ 54 static const struct mux_config da850_pins[] = { 55 #ifdef CONFIG_DAVINCI_MUX 56 /* UART0 function */ 57 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false) 58 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false) 59 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false) 60 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false) 61 /* UART1 function */ 62 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false) 63 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false) 64 /* UART2 function */ 65 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false) 66 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false) 67 /* I2C1 function */ 68 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false) 69 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false) 70 /* I2C0 function */ 71 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) 72 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) 73 /* EMAC function */ 74 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false) 75 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false) 76 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false) 77 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false) 78 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false) 79 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false) 80 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false) 81 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false) 82 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false) 83 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false) 84 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false) 85 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false) 86 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false) 87 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false) 88 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) 89 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) 90 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) 91 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false) 92 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false) 93 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false) 94 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false) 95 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false) 96 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false) 97 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false) 98 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false) 99 /* McASP function */ 100 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false) 101 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false) 102 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false) 103 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false) 104 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false) 105 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false) 106 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false) 107 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false) 108 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false) 109 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false) 110 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false) 111 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false) 112 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false) 113 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false) 114 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false) 115 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false) 116 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false) 117 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false) 118 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false) 119 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false) 120 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false) 121 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false) 122 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false) 123 /* LCD function */ 124 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false) 125 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false) 126 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false) 127 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false) 128 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false) 129 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false) 130 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false) 131 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false) 132 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false) 133 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false) 134 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false) 135 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false) 136 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false) 137 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false) 138 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false) 139 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false) 140 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false) 141 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false) 142 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false) 143 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false) 144 /* MMC/SD0 function */ 145 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false) 146 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false) 147 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false) 148 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false) 149 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false) 150 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false) 151 /* MMC/SD1 function */ 152 MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false) 153 MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false) 154 MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false) 155 MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false) 156 MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false) 157 MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false) 158 /* EMIF2.5/EMIFA function */ 159 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false) 160 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false) 161 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false) 162 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false) 163 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false) 164 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false) 165 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false) 166 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false) 167 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false) 168 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false) 169 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false) 170 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false) 171 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false) 172 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false) 173 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false) 174 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false) 175 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false) 176 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false) 177 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false) 178 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false) 179 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false) 180 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false) 181 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false) 182 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false) 183 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false) 184 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false) 185 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false) 186 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false) 187 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false) 188 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false) 189 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false) 190 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false) 191 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false) 192 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false) 193 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false) 194 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false) 195 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false) 196 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false) 197 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false) 198 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false) 199 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false) 200 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false) 201 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false) 202 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false) 203 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false) 204 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false) 205 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false) 206 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false) 207 /* GPIO function */ 208 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false) 209 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false) 210 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false) 211 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) 212 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false) 213 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false) 214 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) 215 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) 216 MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false) 217 MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false) 218 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false) 219 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false) 220 /* VPIF Capture */ 221 MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false) 222 MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false) 223 MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false) 224 MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false) 225 MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false) 226 MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false) 227 MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false) 228 MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false) 229 MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false) 230 MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false) 231 MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false) 232 MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false) 233 MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false) 234 MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false) 235 MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false) 236 MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false) 237 MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false) 238 MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false) 239 MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false) 240 MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false) 241 /* VPIF Display */ 242 MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false) 243 MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false) 244 MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false) 245 MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false) 246 MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false) 247 MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false) 248 MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false) 249 MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false) 250 MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false) 251 MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false) 252 MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false) 253 MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false) 254 MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false) 255 MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false) 256 MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false) 257 MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false) 258 MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false) 259 MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false) 260 #endif 261 }; 262 263 const short da850_i2c0_pins[] __initconst = { 264 DA850_I2C0_SDA, DA850_I2C0_SCL, 265 -1 266 }; 267 268 const short da850_i2c1_pins[] __initconst = { 269 DA850_I2C1_SCL, DA850_I2C1_SDA, 270 -1 271 }; 272 273 const short da850_lcdcntl_pins[] __initconst = { 274 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, 275 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, 276 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, 277 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, 278 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, 279 -1 280 }; 281 282 const short da850_vpif_capture_pins[] __initconst = { 283 DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3, 284 DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7, 285 DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11, 286 DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15, 287 DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2, 288 DA850_VPIF_CLKIN3, 289 -1 290 }; 291 292 const short da850_vpif_display_pins[] __initconst = { 293 DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3, 294 DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7, 295 DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10, 296 DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13, 297 DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2, 298 DA850_VPIF_CLKO3, 299 -1 300 }; 301 302 static struct map_desc da850_io_desc[] = { 303 { 304 .virtual = IO_VIRT, 305 .pfn = __phys_to_pfn(IO_PHYS), 306 .length = IO_SIZE, 307 .type = MT_DEVICE 308 }, 309 { 310 .virtual = DA8XX_CP_INTC_VIRT, 311 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), 312 .length = DA8XX_CP_INTC_SIZE, 313 .type = MT_DEVICE 314 }, 315 }; 316 317 /* Contents of JTAG ID register used to identify exact cpu type */ 318 static struct davinci_id da850_ids[] = { 319 { 320 .variant = 0x0, 321 .part_no = 0xb7d1, 322 .manufacturer = 0x017, /* 0x02f >> 1 */ 323 .cpu_id = DAVINCI_CPU_ID_DA850, 324 .name = "da850/omap-l138", 325 }, 326 { 327 .variant = 0x1, 328 .part_no = 0xb7d1, 329 .manufacturer = 0x017, /* 0x02f >> 1 */ 330 .cpu_id = DAVINCI_CPU_ID_DA850, 331 .name = "da850/omap-l138/am18x", 332 }, 333 }; 334 335 static struct davinci_timer_instance da850_timer_instance[4] = { 336 { 337 .base = DA8XX_TIMER64P0_BASE, 338 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0), 339 .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0), 340 }, 341 { 342 .base = DA8XX_TIMER64P1_BASE, 343 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1), 344 .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1), 345 }, 346 { 347 .base = DA850_TIMER64P2_BASE, 348 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_2), 349 .top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_2), 350 }, 351 { 352 .base = DA850_TIMER64P3_BASE, 353 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_3), 354 .top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_3), 355 }, 356 }; 357 358 /* 359 * T0_BOT: Timer 0, bottom : Used for clock_event 360 * T0_TOP: Timer 0, top : Used for clocksource 361 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer 362 */ 363 static struct davinci_timer_info da850_timer_info = { 364 .timers = da850_timer_instance, 365 .clockevent_id = T0_BOT, 366 .clocksource_id = T0_TOP, 367 }; 368 369 #ifdef CONFIG_CPU_FREQ 370 /* 371 * Notes: 372 * According to the TRM, minimum PLLM results in maximum power savings. 373 * The OPP definitions below should keep the PLLM as low as possible. 374 * 375 * The output of the PLLM must be between 300 to 600 MHz. 376 */ 377 struct da850_opp { 378 unsigned int freq; /* in KHz */ 379 unsigned int prediv; 380 unsigned int mult; 381 unsigned int postdiv; 382 unsigned int cvdd_min; /* in uV */ 383 unsigned int cvdd_max; /* in uV */ 384 }; 385 386 static const struct da850_opp da850_opp_456 = { 387 .freq = 456000, 388 .prediv = 1, 389 .mult = 19, 390 .postdiv = 1, 391 .cvdd_min = 1300000, 392 .cvdd_max = 1350000, 393 }; 394 395 static const struct da850_opp da850_opp_408 = { 396 .freq = 408000, 397 .prediv = 1, 398 .mult = 17, 399 .postdiv = 1, 400 .cvdd_min = 1300000, 401 .cvdd_max = 1350000, 402 }; 403 404 static const struct da850_opp da850_opp_372 = { 405 .freq = 372000, 406 .prediv = 2, 407 .mult = 31, 408 .postdiv = 1, 409 .cvdd_min = 1200000, 410 .cvdd_max = 1320000, 411 }; 412 413 static const struct da850_opp da850_opp_300 = { 414 .freq = 300000, 415 .prediv = 1, 416 .mult = 25, 417 .postdiv = 2, 418 .cvdd_min = 1200000, 419 .cvdd_max = 1320000, 420 }; 421 422 static const struct da850_opp da850_opp_200 = { 423 .freq = 200000, 424 .prediv = 1, 425 .mult = 25, 426 .postdiv = 3, 427 .cvdd_min = 1100000, 428 .cvdd_max = 1160000, 429 }; 430 431 static const struct da850_opp da850_opp_96 = { 432 .freq = 96000, 433 .prediv = 1, 434 .mult = 20, 435 .postdiv = 5, 436 .cvdd_min = 1000000, 437 .cvdd_max = 1050000, 438 }; 439 440 #define OPP(freq) \ 441 { \ 442 .driver_data = (unsigned int) &da850_opp_##freq, \ 443 .frequency = freq * 1000, \ 444 } 445 446 static struct cpufreq_frequency_table da850_freq_table[] = { 447 OPP(456), 448 OPP(408), 449 OPP(372), 450 OPP(300), 451 OPP(200), 452 OPP(96), 453 { 454 .driver_data = 0, 455 .frequency = CPUFREQ_TABLE_END, 456 }, 457 }; 458 459 #ifdef CONFIG_REGULATOR 460 static int da850_set_voltage(unsigned int index); 461 static int da850_regulator_init(void); 462 #endif 463 464 static struct davinci_cpufreq_config cpufreq_info = { 465 .freq_table = da850_freq_table, 466 #ifdef CONFIG_REGULATOR 467 .init = da850_regulator_init, 468 .set_voltage = da850_set_voltage, 469 #endif 470 }; 471 472 #ifdef CONFIG_REGULATOR 473 static struct regulator *cvdd; 474 475 static int da850_set_voltage(unsigned int index) 476 { 477 struct da850_opp *opp; 478 479 if (!cvdd) 480 return -ENODEV; 481 482 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data; 483 484 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); 485 } 486 487 static int da850_regulator_init(void) 488 { 489 cvdd = regulator_get(NULL, "cvdd"); 490 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;" 491 " voltage scaling unsupported\n")) { 492 return PTR_ERR(cvdd); 493 } 494 495 return 0; 496 } 497 #endif 498 499 static struct platform_device da850_cpufreq_device = { 500 .name = "cpufreq-davinci", 501 .dev = { 502 .platform_data = &cpufreq_info, 503 }, 504 .id = -1, 505 }; 506 507 unsigned int da850_max_speed = 300000; 508 509 int da850_register_cpufreq(char *async_clk) 510 { 511 int i; 512 513 /* cpufreq driver can help keep an "async" clock constant */ 514 if (async_clk) 515 clk_add_alias("async", da850_cpufreq_device.name, 516 async_clk, NULL); 517 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) { 518 if (da850_freq_table[i].frequency <= da850_max_speed) { 519 cpufreq_info.freq_table = &da850_freq_table[i]; 520 break; 521 } 522 } 523 524 return platform_device_register(&da850_cpufreq_device); 525 } 526 #else 527 int __init da850_register_cpufreq(char *async_clk) 528 { 529 return 0; 530 } 531 #endif 532 533 /* VPIF resource, platform data */ 534 static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32); 535 536 static struct resource da850_vpif_resource[] = { 537 { 538 .start = DA8XX_VPIF_BASE, 539 .end = DA8XX_VPIF_BASE + 0xfff, 540 .flags = IORESOURCE_MEM, 541 } 542 }; 543 544 static struct platform_device da850_vpif_dev = { 545 .name = "vpif", 546 .id = -1, 547 .dev = { 548 .dma_mask = &da850_vpif_dma_mask, 549 .coherent_dma_mask = DMA_BIT_MASK(32), 550 }, 551 .resource = da850_vpif_resource, 552 .num_resources = ARRAY_SIZE(da850_vpif_resource), 553 }; 554 555 static struct resource da850_vpif_display_resource[] = { 556 { 557 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 558 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 559 .flags = IORESOURCE_IRQ, 560 }, 561 }; 562 563 static struct platform_device da850_vpif_display_dev = { 564 .name = "vpif_display", 565 .id = -1, 566 .dev = { 567 .dma_mask = &da850_vpif_dma_mask, 568 .coherent_dma_mask = DMA_BIT_MASK(32), 569 }, 570 .resource = da850_vpif_display_resource, 571 .num_resources = ARRAY_SIZE(da850_vpif_display_resource), 572 }; 573 574 static struct resource da850_vpif_capture_resource[] = { 575 { 576 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 577 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 578 .flags = IORESOURCE_IRQ, 579 }, 580 { 581 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 582 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 583 .flags = IORESOURCE_IRQ, 584 }, 585 }; 586 587 static struct platform_device da850_vpif_capture_dev = { 588 .name = "vpif_capture", 589 .id = -1, 590 .dev = { 591 .dma_mask = &da850_vpif_dma_mask, 592 .coherent_dma_mask = DMA_BIT_MASK(32), 593 }, 594 .resource = da850_vpif_capture_resource, 595 .num_resources = ARRAY_SIZE(da850_vpif_capture_resource), 596 }; 597 598 int __init da850_register_vpif(void) 599 { 600 return platform_device_register(&da850_vpif_dev); 601 } 602 603 int __init da850_register_vpif_display(struct vpif_display_config 604 *display_config) 605 { 606 da850_vpif_display_dev.dev.platform_data = display_config; 607 return platform_device_register(&da850_vpif_display_dev); 608 } 609 610 int __init da850_register_vpif_capture(struct vpif_capture_config 611 *capture_config) 612 { 613 da850_vpif_capture_dev.dev.platform_data = capture_config; 614 return platform_device_register(&da850_vpif_capture_dev); 615 } 616 617 static struct davinci_gpio_platform_data da850_gpio_platform_data = { 618 .no_auto_base = true, 619 .base = 0, 620 .ngpio = 144, 621 }; 622 623 int __init da850_register_gpio(void) 624 { 625 return da8xx_register_gpio(&da850_gpio_platform_data); 626 } 627 628 static const struct davinci_soc_info davinci_soc_info_da850 = { 629 .io_desc = da850_io_desc, 630 .io_desc_num = ARRAY_SIZE(da850_io_desc), 631 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, 632 .ids = da850_ids, 633 .ids_num = ARRAY_SIZE(da850_ids), 634 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, 635 .pinmux_pins = da850_pins, 636 .pinmux_pins_num = ARRAY_SIZE(da850_pins), 637 .timer_info = &da850_timer_info, 638 .emac_pdata = &da8xx_emac_pdata, 639 .sram_dma = DA8XX_SHARED_RAM_BASE, 640 .sram_len = SZ_128K, 641 }; 642 643 void __init da850_init(void) 644 { 645 davinci_common_init(&davinci_soc_info_da850); 646 647 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); 648 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module")) 649 return; 650 651 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K); 652 WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"); 653 } 654 655 static const struct davinci_cp_intc_config da850_cp_intc_config = { 656 .reg = { 657 .start = DA8XX_CP_INTC_BASE, 658 .end = DA8XX_CP_INTC_BASE + SZ_8K - 1, 659 .flags = IORESOURCE_MEM, 660 }, 661 .num_irqs = DA850_N_CP_INTC_IRQ, 662 }; 663 664 void __init da850_init_irq(void) 665 { 666 davinci_cp_intc_init(&da850_cp_intc_config); 667 } 668 669 void __init da850_init_time(void) 670 { 671 void __iomem *pll0; 672 struct regmap *cfgchip; 673 struct clk *clk; 674 675 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ); 676 677 pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K); 678 cfgchip = da8xx_get_cfgchip(); 679 680 da850_pll0_init(NULL, pll0, cfgchip); 681 682 clk = clk_get(NULL, "timer0"); 683 684 davinci_timer_init(clk); 685 } 686 687 static struct resource da850_pll1_resources[] = { 688 { 689 .start = DA850_PLL1_BASE, 690 .end = DA850_PLL1_BASE + SZ_4K - 1, 691 .flags = IORESOURCE_MEM, 692 }, 693 }; 694 695 static struct davinci_pll_platform_data da850_pll1_pdata; 696 697 static struct platform_device da850_pll1_device = { 698 .name = "da850-pll1", 699 .id = -1, 700 .resource = da850_pll1_resources, 701 .num_resources = ARRAY_SIZE(da850_pll1_resources), 702 .dev = { 703 .platform_data = &da850_pll1_pdata, 704 }, 705 }; 706 707 static struct resource da850_psc0_resources[] = { 708 { 709 .start = DA8XX_PSC0_BASE, 710 .end = DA8XX_PSC0_BASE + SZ_4K - 1, 711 .flags = IORESOURCE_MEM, 712 }, 713 }; 714 715 static struct platform_device da850_psc0_device = { 716 .name = "da850-psc0", 717 .id = -1, 718 .resource = da850_psc0_resources, 719 .num_resources = ARRAY_SIZE(da850_psc0_resources), 720 }; 721 722 static struct resource da850_psc1_resources[] = { 723 { 724 .start = DA8XX_PSC1_BASE, 725 .end = DA8XX_PSC1_BASE + SZ_4K - 1, 726 .flags = IORESOURCE_MEM, 727 }, 728 }; 729 730 static struct platform_device da850_psc1_device = { 731 .name = "da850-psc1", 732 .id = -1, 733 .resource = da850_psc1_resources, 734 .num_resources = ARRAY_SIZE(da850_psc1_resources), 735 }; 736 737 static struct da8xx_cfgchip_clk_platform_data da850_async1_pdata; 738 739 static struct platform_device da850_async1_clksrc_device = { 740 .name = "da850-async1-clksrc", 741 .id = -1, 742 .dev = { 743 .platform_data = &da850_async1_pdata, 744 }, 745 }; 746 747 static struct da8xx_cfgchip_clk_platform_data da850_async3_pdata; 748 749 static struct platform_device da850_async3_clksrc_device = { 750 .name = "da850-async3-clksrc", 751 .id = -1, 752 .dev = { 753 .platform_data = &da850_async3_pdata, 754 }, 755 }; 756 757 static struct da8xx_cfgchip_clk_platform_data da850_tbclksync_pdata; 758 759 static struct platform_device da850_tbclksync_device = { 760 .name = "da830-tbclksync", 761 .id = -1, 762 .dev = { 763 .platform_data = &da850_tbclksync_pdata, 764 }, 765 }; 766 767 void __init da850_register_clocks(void) 768 { 769 /* PLL0 is registered in da850_init_time() */ 770 771 da850_pll1_pdata.cfgchip = da8xx_get_cfgchip(); 772 platform_device_register(&da850_pll1_device); 773 774 da850_async1_pdata.cfgchip = da8xx_get_cfgchip(); 775 platform_device_register(&da850_async1_clksrc_device); 776 777 da850_async3_pdata.cfgchip = da8xx_get_cfgchip(); 778 platform_device_register(&da850_async3_clksrc_device); 779 780 platform_device_register(&da850_psc0_device); 781 782 platform_device_register(&da850_psc1_device); 783 784 da850_tbclksync_pdata.cfgchip = da8xx_get_cfgchip(); 785 platform_device_register(&da850_tbclksync_device); 786 } 787