1 /* 2 * TI DA830/OMAP L137 chip specific setup 3 * 4 * Author: Mark A. Greer <mgreer@mvista.com> 5 * 6 * 2009 (c) MontaVista Software, Inc. This file is licensed under 7 * the terms of the GNU General Public License version 2. This program 8 * is licensed "as is" without any warranty of any kind, whether express 9 * or implied. 10 */ 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/clk.h> 14 #include <linux/platform_device.h> 15 16 #include <asm/mach/map.h> 17 18 #include <mach/clock.h> 19 #include <mach/psc.h> 20 #include <mach/mux.h> 21 #include <mach/irqs.h> 22 #include <mach/cputype.h> 23 #include <mach/common.h> 24 #include <mach/time.h> 25 #include <mach/da8xx.h> 26 27 #include "clock.h" 28 #include "mux.h" 29 30 /* Offsets of the 8 compare registers on the da830 */ 31 #define DA830_CMP12_0 0x60 32 #define DA830_CMP12_1 0x64 33 #define DA830_CMP12_2 0x68 34 #define DA830_CMP12_3 0x6c 35 #define DA830_CMP12_4 0x70 36 #define DA830_CMP12_5 0x74 37 #define DA830_CMP12_6 0x78 38 #define DA830_CMP12_7 0x7c 39 40 #define DA830_REF_FREQ 24000000 41 42 static struct pll_data pll0_data = { 43 .num = 1, 44 .phys_base = DA8XX_PLL0_BASE, 45 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, 46 }; 47 48 static struct clk ref_clk = { 49 .name = "ref_clk", 50 .rate = DA830_REF_FREQ, 51 }; 52 53 static struct clk pll0_clk = { 54 .name = "pll0", 55 .parent = &ref_clk, 56 .pll_data = &pll0_data, 57 .flags = CLK_PLL, 58 }; 59 60 static struct clk pll0_aux_clk = { 61 .name = "pll0_aux_clk", 62 .parent = &pll0_clk, 63 .flags = CLK_PLL | PRE_PLL, 64 }; 65 66 static struct clk pll0_sysclk2 = { 67 .name = "pll0_sysclk2", 68 .parent = &pll0_clk, 69 .flags = CLK_PLL, 70 .div_reg = PLLDIV2, 71 }; 72 73 static struct clk pll0_sysclk3 = { 74 .name = "pll0_sysclk3", 75 .parent = &pll0_clk, 76 .flags = CLK_PLL, 77 .div_reg = PLLDIV3, 78 }; 79 80 static struct clk pll0_sysclk4 = { 81 .name = "pll0_sysclk4", 82 .parent = &pll0_clk, 83 .flags = CLK_PLL, 84 .div_reg = PLLDIV4, 85 }; 86 87 static struct clk pll0_sysclk5 = { 88 .name = "pll0_sysclk5", 89 .parent = &pll0_clk, 90 .flags = CLK_PLL, 91 .div_reg = PLLDIV5, 92 }; 93 94 static struct clk pll0_sysclk6 = { 95 .name = "pll0_sysclk6", 96 .parent = &pll0_clk, 97 .flags = CLK_PLL, 98 .div_reg = PLLDIV6, 99 }; 100 101 static struct clk pll0_sysclk7 = { 102 .name = "pll0_sysclk7", 103 .parent = &pll0_clk, 104 .flags = CLK_PLL, 105 .div_reg = PLLDIV7, 106 }; 107 108 static struct clk i2c0_clk = { 109 .name = "i2c0", 110 .parent = &pll0_aux_clk, 111 }; 112 113 static struct clk timerp64_0_clk = { 114 .name = "timer0", 115 .parent = &pll0_aux_clk, 116 }; 117 118 static struct clk timerp64_1_clk = { 119 .name = "timer1", 120 .parent = &pll0_aux_clk, 121 }; 122 123 static struct clk arm_rom_clk = { 124 .name = "arm_rom", 125 .parent = &pll0_sysclk2, 126 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, 127 .flags = ALWAYS_ENABLED, 128 }; 129 130 static struct clk scr0_ss_clk = { 131 .name = "scr0_ss", 132 .parent = &pll0_sysclk2, 133 .lpsc = DA8XX_LPSC0_SCR0_SS, 134 .flags = ALWAYS_ENABLED, 135 }; 136 137 static struct clk scr1_ss_clk = { 138 .name = "scr1_ss", 139 .parent = &pll0_sysclk2, 140 .lpsc = DA8XX_LPSC0_SCR1_SS, 141 .flags = ALWAYS_ENABLED, 142 }; 143 144 static struct clk scr2_ss_clk = { 145 .name = "scr2_ss", 146 .parent = &pll0_sysclk2, 147 .lpsc = DA8XX_LPSC0_SCR2_SS, 148 .flags = ALWAYS_ENABLED, 149 }; 150 151 static struct clk dmax_clk = { 152 .name = "dmax", 153 .parent = &pll0_sysclk2, 154 .lpsc = DA8XX_LPSC0_DMAX, 155 .flags = ALWAYS_ENABLED, 156 }; 157 158 static struct clk tpcc_clk = { 159 .name = "tpcc", 160 .parent = &pll0_sysclk2, 161 .lpsc = DA8XX_LPSC0_TPCC, 162 .flags = ALWAYS_ENABLED | CLK_PSC, 163 }; 164 165 static struct clk tptc0_clk = { 166 .name = "tptc0", 167 .parent = &pll0_sysclk2, 168 .lpsc = DA8XX_LPSC0_TPTC0, 169 .flags = ALWAYS_ENABLED, 170 }; 171 172 static struct clk tptc1_clk = { 173 .name = "tptc1", 174 .parent = &pll0_sysclk2, 175 .lpsc = DA8XX_LPSC0_TPTC1, 176 .flags = ALWAYS_ENABLED, 177 }; 178 179 static struct clk mmcsd_clk = { 180 .name = "mmcsd", 181 .parent = &pll0_sysclk2, 182 .lpsc = DA8XX_LPSC0_MMC_SD, 183 }; 184 185 static struct clk uart0_clk = { 186 .name = "uart0", 187 .parent = &pll0_sysclk2, 188 .lpsc = DA8XX_LPSC0_UART0, 189 }; 190 191 static struct clk uart1_clk = { 192 .name = "uart1", 193 .parent = &pll0_sysclk2, 194 .lpsc = DA8XX_LPSC1_UART1, 195 .psc_ctlr = 1, 196 }; 197 198 static struct clk uart2_clk = { 199 .name = "uart2", 200 .parent = &pll0_sysclk2, 201 .lpsc = DA8XX_LPSC1_UART2, 202 .psc_ctlr = 1, 203 }; 204 205 static struct clk spi0_clk = { 206 .name = "spi0", 207 .parent = &pll0_sysclk2, 208 .lpsc = DA8XX_LPSC0_SPI0, 209 }; 210 211 static struct clk spi1_clk = { 212 .name = "spi1", 213 .parent = &pll0_sysclk2, 214 .lpsc = DA8XX_LPSC1_SPI1, 215 .psc_ctlr = 1, 216 }; 217 218 static struct clk ecap0_clk = { 219 .name = "ecap0", 220 .parent = &pll0_sysclk2, 221 .lpsc = DA8XX_LPSC1_ECAP, 222 .psc_ctlr = 1, 223 }; 224 225 static struct clk ecap1_clk = { 226 .name = "ecap1", 227 .parent = &pll0_sysclk2, 228 .lpsc = DA8XX_LPSC1_ECAP, 229 .psc_ctlr = 1, 230 }; 231 232 static struct clk ecap2_clk = { 233 .name = "ecap2", 234 .parent = &pll0_sysclk2, 235 .lpsc = DA8XX_LPSC1_ECAP, 236 .psc_ctlr = 1, 237 }; 238 239 static struct clk pwm0_clk = { 240 .name = "pwm0", 241 .parent = &pll0_sysclk2, 242 .lpsc = DA8XX_LPSC1_PWM, 243 .psc_ctlr = 1, 244 }; 245 246 static struct clk pwm1_clk = { 247 .name = "pwm1", 248 .parent = &pll0_sysclk2, 249 .lpsc = DA8XX_LPSC1_PWM, 250 .psc_ctlr = 1, 251 }; 252 253 static struct clk pwm2_clk = { 254 .name = "pwm2", 255 .parent = &pll0_sysclk2, 256 .lpsc = DA8XX_LPSC1_PWM, 257 .psc_ctlr = 1, 258 }; 259 260 static struct clk eqep0_clk = { 261 .name = "eqep0", 262 .parent = &pll0_sysclk2, 263 .lpsc = DA830_LPSC1_EQEP, 264 .psc_ctlr = 1, 265 }; 266 267 static struct clk eqep1_clk = { 268 .name = "eqep1", 269 .parent = &pll0_sysclk2, 270 .lpsc = DA830_LPSC1_EQEP, 271 .psc_ctlr = 1, 272 }; 273 274 static struct clk lcdc_clk = { 275 .name = "lcdc", 276 .parent = &pll0_sysclk2, 277 .lpsc = DA8XX_LPSC1_LCDC, 278 .psc_ctlr = 1, 279 }; 280 281 static struct clk mcasp0_clk = { 282 .name = "mcasp0", 283 .parent = &pll0_sysclk2, 284 .lpsc = DA8XX_LPSC1_McASP0, 285 .psc_ctlr = 1, 286 }; 287 288 static struct clk mcasp1_clk = { 289 .name = "mcasp1", 290 .parent = &pll0_sysclk2, 291 .lpsc = DA830_LPSC1_McASP1, 292 .psc_ctlr = 1, 293 }; 294 295 static struct clk mcasp2_clk = { 296 .name = "mcasp2", 297 .parent = &pll0_sysclk2, 298 .lpsc = DA830_LPSC1_McASP2, 299 .psc_ctlr = 1, 300 }; 301 302 static struct clk usb20_clk = { 303 .name = "usb20", 304 .parent = &pll0_sysclk2, 305 .lpsc = DA8XX_LPSC1_USB20, 306 .psc_ctlr = 1, 307 }; 308 309 static struct clk aemif_clk = { 310 .name = "aemif", 311 .parent = &pll0_sysclk3, 312 .lpsc = DA8XX_LPSC0_EMIF25, 313 .flags = ALWAYS_ENABLED, 314 }; 315 316 static struct clk aintc_clk = { 317 .name = "aintc", 318 .parent = &pll0_sysclk4, 319 .lpsc = DA8XX_LPSC0_AINTC, 320 .flags = ALWAYS_ENABLED, 321 }; 322 323 static struct clk secu_mgr_clk = { 324 .name = "secu_mgr", 325 .parent = &pll0_sysclk4, 326 .lpsc = DA8XX_LPSC0_SECU_MGR, 327 .flags = ALWAYS_ENABLED, 328 }; 329 330 static struct clk emac_clk = { 331 .name = "emac", 332 .parent = &pll0_sysclk4, 333 .lpsc = DA8XX_LPSC1_CPGMAC, 334 .psc_ctlr = 1, 335 }; 336 337 static struct clk gpio_clk = { 338 .name = "gpio", 339 .parent = &pll0_sysclk4, 340 .lpsc = DA8XX_LPSC1_GPIO, 341 .psc_ctlr = 1, 342 }; 343 344 static struct clk i2c1_clk = { 345 .name = "i2c1", 346 .parent = &pll0_sysclk4, 347 .lpsc = DA8XX_LPSC1_I2C, 348 .psc_ctlr = 1, 349 }; 350 351 static struct clk usb11_clk = { 352 .name = "usb11", 353 .parent = &pll0_sysclk4, 354 .lpsc = DA8XX_LPSC1_USB11, 355 .psc_ctlr = 1, 356 }; 357 358 static struct clk emif3_clk = { 359 .name = "emif3", 360 .parent = &pll0_sysclk5, 361 .lpsc = DA8XX_LPSC1_EMIF3C, 362 .flags = ALWAYS_ENABLED, 363 .psc_ctlr = 1, 364 }; 365 366 static struct clk arm_clk = { 367 .name = "arm", 368 .parent = &pll0_sysclk6, 369 .lpsc = DA8XX_LPSC0_ARM, 370 .flags = ALWAYS_ENABLED, 371 }; 372 373 static struct clk rmii_clk = { 374 .name = "rmii", 375 .parent = &pll0_sysclk7, 376 }; 377 378 static struct davinci_clk da830_clks[] = { 379 CLK(NULL, "ref", &ref_clk), 380 CLK(NULL, "pll0", &pll0_clk), 381 CLK(NULL, "pll0_aux", &pll0_aux_clk), 382 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), 383 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), 384 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), 385 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), 386 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), 387 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), 388 CLK("i2c_davinci.1", NULL, &i2c0_clk), 389 CLK(NULL, "timer0", &timerp64_0_clk), 390 CLK("watchdog", NULL, &timerp64_1_clk), 391 CLK(NULL, "arm_rom", &arm_rom_clk), 392 CLK(NULL, "scr0_ss", &scr0_ss_clk), 393 CLK(NULL, "scr1_ss", &scr1_ss_clk), 394 CLK(NULL, "scr2_ss", &scr2_ss_clk), 395 CLK(NULL, "dmax", &dmax_clk), 396 CLK(NULL, "tpcc", &tpcc_clk), 397 CLK(NULL, "tptc0", &tptc0_clk), 398 CLK(NULL, "tptc1", &tptc1_clk), 399 CLK("davinci_mmc.0", NULL, &mmcsd_clk), 400 CLK(NULL, "uart0", &uart0_clk), 401 CLK(NULL, "uart1", &uart1_clk), 402 CLK(NULL, "uart2", &uart2_clk), 403 CLK("dm_spi.0", NULL, &spi0_clk), 404 CLK("dm_spi.1", NULL, &spi1_clk), 405 CLK(NULL, "ecap0", &ecap0_clk), 406 CLK(NULL, "ecap1", &ecap1_clk), 407 CLK(NULL, "ecap2", &ecap2_clk), 408 CLK(NULL, "pwm0", &pwm0_clk), 409 CLK(NULL, "pwm1", &pwm1_clk), 410 CLK(NULL, "pwm2", &pwm2_clk), 411 CLK("eqep.0", NULL, &eqep0_clk), 412 CLK("eqep.1", NULL, &eqep1_clk), 413 CLK("da830_lcdc", NULL, &lcdc_clk), 414 CLK("soc-audio.0", NULL, &mcasp0_clk), 415 CLK("soc-audio.1", NULL, &mcasp1_clk), 416 CLK("soc-audio.2", NULL, &mcasp2_clk), 417 CLK("musb_hdrc", NULL, &usb20_clk), 418 CLK(NULL, "aemif", &aemif_clk), 419 CLK(NULL, "aintc", &aintc_clk), 420 CLK(NULL, "secu_mgr", &secu_mgr_clk), 421 CLK("davinci_emac.1", NULL, &emac_clk), 422 CLK(NULL, "gpio", &gpio_clk), 423 CLK("i2c_davinci.2", NULL, &i2c1_clk), 424 CLK(NULL, "usb11", &usb11_clk), 425 CLK(NULL, "emif3", &emif3_clk), 426 CLK(NULL, "arm", &arm_clk), 427 CLK(NULL, "rmii", &rmii_clk), 428 CLK(NULL, NULL, NULL), 429 }; 430 431 #define PINMUX0 0x00 432 #define PINMUX1 0x04 433 #define PINMUX2 0x08 434 #define PINMUX3 0x0c 435 #define PINMUX4 0x10 436 #define PINMUX5 0x14 437 #define PINMUX6 0x18 438 #define PINMUX7 0x1c 439 #define PINMUX8 0x20 440 #define PINMUX9 0x24 441 #define PINMUX10 0x28 442 #define PINMUX11 0x2c 443 #define PINMUX12 0x30 444 #define PINMUX13 0x34 445 #define PINMUX14 0x38 446 #define PINMUX15 0x3c 447 #define PINMUX16 0x40 448 #define PINMUX17 0x44 449 #define PINMUX18 0x48 450 #define PINMUX19 0x4c 451 452 /* 453 * Device specific mux setup 454 * 455 * soc description mux mode mode mux dbg 456 * reg offset mask mode 457 */ 458 static const struct mux_config da830_pins[] = { 459 #ifdef CONFIG_DAVINCI_MUX 460 MUX_CFG(DA830, GPIO7_14, 0, 0, 0xf, 1, false) 461 MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false) 462 MUX_CFG(DA830, GPIO7_15, 0, 4, 0xf, 1, false) 463 MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false) 464 MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false) 465 MUX_CFG(DA830, EMB_CLK_GLUE, 0, 12, 0xf, 1, false) 466 MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false) 467 MUX_CFG(DA830, NEMB_CS_0, 0, 16, 0xf, 1, false) 468 MUX_CFG(DA830, NEMB_CAS, 0, 20, 0xf, 1, false) 469 MUX_CFG(DA830, NEMB_RAS, 0, 24, 0xf, 1, false) 470 MUX_CFG(DA830, NEMB_WE, 0, 28, 0xf, 1, false) 471 MUX_CFG(DA830, EMB_BA_1, 1, 0, 0xf, 1, false) 472 MUX_CFG(DA830, EMB_BA_0, 1, 4, 0xf, 1, false) 473 MUX_CFG(DA830, EMB_A_0, 1, 8, 0xf, 1, false) 474 MUX_CFG(DA830, EMB_A_1, 1, 12, 0xf, 1, false) 475 MUX_CFG(DA830, EMB_A_2, 1, 16, 0xf, 1, false) 476 MUX_CFG(DA830, EMB_A_3, 1, 20, 0xf, 1, false) 477 MUX_CFG(DA830, EMB_A_4, 1, 24, 0xf, 1, false) 478 MUX_CFG(DA830, EMB_A_5, 1, 28, 0xf, 1, false) 479 MUX_CFG(DA830, GPIO7_0, 1, 0, 0xf, 8, false) 480 MUX_CFG(DA830, GPIO7_1, 1, 4, 0xf, 8, false) 481 MUX_CFG(DA830, GPIO7_2, 1, 8, 0xf, 8, false) 482 MUX_CFG(DA830, GPIO7_3, 1, 12, 0xf, 8, false) 483 MUX_CFG(DA830, GPIO7_4, 1, 16, 0xf, 8, false) 484 MUX_CFG(DA830, GPIO7_5, 1, 20, 0xf, 8, false) 485 MUX_CFG(DA830, GPIO7_6, 1, 24, 0xf, 8, false) 486 MUX_CFG(DA830, GPIO7_7, 1, 28, 0xf, 8, false) 487 MUX_CFG(DA830, EMB_A_6, 2, 0, 0xf, 1, false) 488 MUX_CFG(DA830, EMB_A_7, 2, 4, 0xf, 1, false) 489 MUX_CFG(DA830, EMB_A_8, 2, 8, 0xf, 1, false) 490 MUX_CFG(DA830, EMB_A_9, 2, 12, 0xf, 1, false) 491 MUX_CFG(DA830, EMB_A_10, 2, 16, 0xf, 1, false) 492 MUX_CFG(DA830, EMB_A_11, 2, 20, 0xf, 1, false) 493 MUX_CFG(DA830, EMB_A_12, 2, 24, 0xf, 1, false) 494 MUX_CFG(DA830, EMB_D_31, 2, 28, 0xf, 1, false) 495 MUX_CFG(DA830, GPIO7_8, 2, 0, 0xf, 8, false) 496 MUX_CFG(DA830, GPIO7_9, 2, 4, 0xf, 8, false) 497 MUX_CFG(DA830, GPIO7_10, 2, 8, 0xf, 8, false) 498 MUX_CFG(DA830, GPIO7_11, 2, 12, 0xf, 8, false) 499 MUX_CFG(DA830, GPIO7_12, 2, 16, 0xf, 8, false) 500 MUX_CFG(DA830, GPIO7_13, 2, 20, 0xf, 8, false) 501 MUX_CFG(DA830, GPIO3_13, 2, 24, 0xf, 8, false) 502 MUX_CFG(DA830, EMB_D_30, 3, 0, 0xf, 1, false) 503 MUX_CFG(DA830, EMB_D_29, 3, 4, 0xf, 1, false) 504 MUX_CFG(DA830, EMB_D_28, 3, 8, 0xf, 1, false) 505 MUX_CFG(DA830, EMB_D_27, 3, 12, 0xf, 1, false) 506 MUX_CFG(DA830, EMB_D_26, 3, 16, 0xf, 1, false) 507 MUX_CFG(DA830, EMB_D_25, 3, 20, 0xf, 1, false) 508 MUX_CFG(DA830, EMB_D_24, 3, 24, 0xf, 1, false) 509 MUX_CFG(DA830, EMB_D_23, 3, 28, 0xf, 1, false) 510 MUX_CFG(DA830, EMB_D_22, 4, 0, 0xf, 1, false) 511 MUX_CFG(DA830, EMB_D_21, 4, 4, 0xf, 1, false) 512 MUX_CFG(DA830, EMB_D_20, 4, 8, 0xf, 1, false) 513 MUX_CFG(DA830, EMB_D_19, 4, 12, 0xf, 1, false) 514 MUX_CFG(DA830, EMB_D_18, 4, 16, 0xf, 1, false) 515 MUX_CFG(DA830, EMB_D_17, 4, 20, 0xf, 1, false) 516 MUX_CFG(DA830, EMB_D_16, 4, 24, 0xf, 1, false) 517 MUX_CFG(DA830, NEMB_WE_DQM_3, 4, 28, 0xf, 1, false) 518 MUX_CFG(DA830, NEMB_WE_DQM_2, 5, 0, 0xf, 1, false) 519 MUX_CFG(DA830, EMB_D_0, 5, 4, 0xf, 1, false) 520 MUX_CFG(DA830, EMB_D_1, 5, 8, 0xf, 1, false) 521 MUX_CFG(DA830, EMB_D_2, 5, 12, 0xf, 1, false) 522 MUX_CFG(DA830, EMB_D_3, 5, 16, 0xf, 1, false) 523 MUX_CFG(DA830, EMB_D_4, 5, 20, 0xf, 1, false) 524 MUX_CFG(DA830, EMB_D_5, 5, 24, 0xf, 1, false) 525 MUX_CFG(DA830, EMB_D_6, 5, 28, 0xf, 1, false) 526 MUX_CFG(DA830, GPIO6_0, 5, 4, 0xf, 8, false) 527 MUX_CFG(DA830, GPIO6_1, 5, 8, 0xf, 8, false) 528 MUX_CFG(DA830, GPIO6_2, 5, 12, 0xf, 8, false) 529 MUX_CFG(DA830, GPIO6_3, 5, 16, 0xf, 8, false) 530 MUX_CFG(DA830, GPIO6_4, 5, 20, 0xf, 8, false) 531 MUX_CFG(DA830, GPIO6_5, 5, 24, 0xf, 8, false) 532 MUX_CFG(DA830, GPIO6_6, 5, 28, 0xf, 8, false) 533 MUX_CFG(DA830, EMB_D_7, 6, 0, 0xf, 1, false) 534 MUX_CFG(DA830, EMB_D_8, 6, 4, 0xf, 1, false) 535 MUX_CFG(DA830, EMB_D_9, 6, 8, 0xf, 1, false) 536 MUX_CFG(DA830, EMB_D_10, 6, 12, 0xf, 1, false) 537 MUX_CFG(DA830, EMB_D_11, 6, 16, 0xf, 1, false) 538 MUX_CFG(DA830, EMB_D_12, 6, 20, 0xf, 1, false) 539 MUX_CFG(DA830, EMB_D_13, 6, 24, 0xf, 1, false) 540 MUX_CFG(DA830, EMB_D_14, 6, 28, 0xf, 1, false) 541 MUX_CFG(DA830, GPIO6_7, 6, 0, 0xf, 8, false) 542 MUX_CFG(DA830, GPIO6_8, 6, 4, 0xf, 8, false) 543 MUX_CFG(DA830, GPIO6_9, 6, 8, 0xf, 8, false) 544 MUX_CFG(DA830, GPIO6_10, 6, 12, 0xf, 8, false) 545 MUX_CFG(DA830, GPIO6_11, 6, 16, 0xf, 8, false) 546 MUX_CFG(DA830, GPIO6_12, 6, 20, 0xf, 8, false) 547 MUX_CFG(DA830, GPIO6_13, 6, 24, 0xf, 8, false) 548 MUX_CFG(DA830, GPIO6_14, 6, 28, 0xf, 8, false) 549 MUX_CFG(DA830, EMB_D_15, 7, 0, 0xf, 1, false) 550 MUX_CFG(DA830, NEMB_WE_DQM_1, 7, 4, 0xf, 1, false) 551 MUX_CFG(DA830, NEMB_WE_DQM_0, 7, 8, 0xf, 1, false) 552 MUX_CFG(DA830, SPI0_SOMI_0, 7, 12, 0xf, 1, false) 553 MUX_CFG(DA830, SPI0_SIMO_0, 7, 16, 0xf, 1, false) 554 MUX_CFG(DA830, SPI0_CLK, 7, 20, 0xf, 1, false) 555 MUX_CFG(DA830, NSPI0_ENA, 7, 24, 0xf, 1, false) 556 MUX_CFG(DA830, NSPI0_SCS_0, 7, 28, 0xf, 1, false) 557 MUX_CFG(DA830, EQEP0I, 7, 12, 0xf, 2, false) 558 MUX_CFG(DA830, EQEP0S, 7, 16, 0xf, 2, false) 559 MUX_CFG(DA830, EQEP1I, 7, 20, 0xf, 2, false) 560 MUX_CFG(DA830, NUART0_CTS, 7, 24, 0xf, 2, false) 561 MUX_CFG(DA830, NUART0_RTS, 7, 28, 0xf, 2, false) 562 MUX_CFG(DA830, EQEP0A, 7, 24, 0xf, 4, false) 563 MUX_CFG(DA830, EQEP0B, 7, 28, 0xf, 4, false) 564 MUX_CFG(DA830, GPIO6_15, 7, 0, 0xf, 8, false) 565 MUX_CFG(DA830, GPIO5_14, 7, 4, 0xf, 8, false) 566 MUX_CFG(DA830, GPIO5_15, 7, 8, 0xf, 8, false) 567 MUX_CFG(DA830, GPIO5_0, 7, 12, 0xf, 8, false) 568 MUX_CFG(DA830, GPIO5_1, 7, 16, 0xf, 8, false) 569 MUX_CFG(DA830, GPIO5_2, 7, 20, 0xf, 8, false) 570 MUX_CFG(DA830, GPIO5_3, 7, 24, 0xf, 8, false) 571 MUX_CFG(DA830, GPIO5_4, 7, 28, 0xf, 8, false) 572 MUX_CFG(DA830, SPI1_SOMI_0, 8, 0, 0xf, 1, false) 573 MUX_CFG(DA830, SPI1_SIMO_0, 8, 4, 0xf, 1, false) 574 MUX_CFG(DA830, SPI1_CLK, 8, 8, 0xf, 1, false) 575 MUX_CFG(DA830, UART0_RXD, 8, 12, 0xf, 1, false) 576 MUX_CFG(DA830, UART0_TXD, 8, 16, 0xf, 1, false) 577 MUX_CFG(DA830, AXR1_10, 8, 20, 0xf, 1, false) 578 MUX_CFG(DA830, AXR1_11, 8, 24, 0xf, 1, false) 579 MUX_CFG(DA830, NSPI1_ENA, 8, 28, 0xf, 1, false) 580 MUX_CFG(DA830, I2C1_SCL, 8, 0, 0xf, 2, false) 581 MUX_CFG(DA830, I2C1_SDA, 8, 4, 0xf, 2, false) 582 MUX_CFG(DA830, EQEP1S, 8, 8, 0xf, 2, false) 583 MUX_CFG(DA830, I2C0_SDA, 8, 12, 0xf, 2, false) 584 MUX_CFG(DA830, I2C0_SCL, 8, 16, 0xf, 2, false) 585 MUX_CFG(DA830, UART2_RXD, 8, 28, 0xf, 2, false) 586 MUX_CFG(DA830, TM64P0_IN12, 8, 12, 0xf, 4, false) 587 MUX_CFG(DA830, TM64P0_OUT12, 8, 16, 0xf, 4, false) 588 MUX_CFG(DA830, GPIO5_5, 8, 0, 0xf, 8, false) 589 MUX_CFG(DA830, GPIO5_6, 8, 4, 0xf, 8, false) 590 MUX_CFG(DA830, GPIO5_7, 8, 8, 0xf, 8, false) 591 MUX_CFG(DA830, GPIO5_8, 8, 12, 0xf, 8, false) 592 MUX_CFG(DA830, GPIO5_9, 8, 16, 0xf, 8, false) 593 MUX_CFG(DA830, GPIO5_10, 8, 20, 0xf, 8, false) 594 MUX_CFG(DA830, GPIO5_11, 8, 24, 0xf, 8, false) 595 MUX_CFG(DA830, GPIO5_12, 8, 28, 0xf, 8, false) 596 MUX_CFG(DA830, NSPI1_SCS_0, 9, 0, 0xf, 1, false) 597 MUX_CFG(DA830, USB0_DRVVBUS, 9, 4, 0xf, 1, false) 598 MUX_CFG(DA830, AHCLKX0, 9, 8, 0xf, 1, false) 599 MUX_CFG(DA830, ACLKX0, 9, 12, 0xf, 1, false) 600 MUX_CFG(DA830, AFSX0, 9, 16, 0xf, 1, false) 601 MUX_CFG(DA830, AHCLKR0, 9, 20, 0xf, 1, false) 602 MUX_CFG(DA830, ACLKR0, 9, 24, 0xf, 1, false) 603 MUX_CFG(DA830, AFSR0, 9, 28, 0xf, 1, false) 604 MUX_CFG(DA830, UART2_TXD, 9, 0, 0xf, 2, false) 605 MUX_CFG(DA830, AHCLKX2, 9, 8, 0xf, 2, false) 606 MUX_CFG(DA830, ECAP0_APWM0, 9, 12, 0xf, 2, false) 607 MUX_CFG(DA830, RMII_MHZ_50_CLK, 9, 20, 0xf, 2, false) 608 MUX_CFG(DA830, ECAP1_APWM1, 9, 24, 0xf, 2, false) 609 MUX_CFG(DA830, USB_REFCLKIN, 9, 8, 0xf, 4, false) 610 MUX_CFG(DA830, GPIO5_13, 9, 0, 0xf, 8, false) 611 MUX_CFG(DA830, GPIO4_15, 9, 4, 0xf, 8, false) 612 MUX_CFG(DA830, GPIO2_11, 9, 8, 0xf, 8, false) 613 MUX_CFG(DA830, GPIO2_12, 9, 12, 0xf, 8, false) 614 MUX_CFG(DA830, GPIO2_13, 9, 16, 0xf, 8, false) 615 MUX_CFG(DA830, GPIO2_14, 9, 20, 0xf, 8, false) 616 MUX_CFG(DA830, GPIO2_15, 9, 24, 0xf, 8, false) 617 MUX_CFG(DA830, GPIO3_12, 9, 28, 0xf, 8, false) 618 MUX_CFG(DA830, AMUTE0, 10, 0, 0xf, 1, false) 619 MUX_CFG(DA830, AXR0_0, 10, 4, 0xf, 1, false) 620 MUX_CFG(DA830, AXR0_1, 10, 8, 0xf, 1, false) 621 MUX_CFG(DA830, AXR0_2, 10, 12, 0xf, 1, false) 622 MUX_CFG(DA830, AXR0_3, 10, 16, 0xf, 1, false) 623 MUX_CFG(DA830, AXR0_4, 10, 20, 0xf, 1, false) 624 MUX_CFG(DA830, AXR0_5, 10, 24, 0xf, 1, false) 625 MUX_CFG(DA830, AXR0_6, 10, 28, 0xf, 1, false) 626 MUX_CFG(DA830, RMII_TXD_0, 10, 4, 0xf, 2, false) 627 MUX_CFG(DA830, RMII_TXD_1, 10, 8, 0xf, 2, false) 628 MUX_CFG(DA830, RMII_TXEN, 10, 12, 0xf, 2, false) 629 MUX_CFG(DA830, RMII_CRS_DV, 10, 16, 0xf, 2, false) 630 MUX_CFG(DA830, RMII_RXD_0, 10, 20, 0xf, 2, false) 631 MUX_CFG(DA830, RMII_RXD_1, 10, 24, 0xf, 2, false) 632 MUX_CFG(DA830, RMII_RXER, 10, 28, 0xf, 2, false) 633 MUX_CFG(DA830, AFSR2, 10, 4, 0xf, 4, false) 634 MUX_CFG(DA830, ACLKX2, 10, 8, 0xf, 4, false) 635 MUX_CFG(DA830, AXR2_3, 10, 12, 0xf, 4, false) 636 MUX_CFG(DA830, AXR2_2, 10, 16, 0xf, 4, false) 637 MUX_CFG(DA830, AXR2_1, 10, 20, 0xf, 4, false) 638 MUX_CFG(DA830, AFSX2, 10, 24, 0xf, 4, false) 639 MUX_CFG(DA830, ACLKR2, 10, 28, 0xf, 4, false) 640 MUX_CFG(DA830, NRESETOUT, 10, 0, 0xf, 8, false) 641 MUX_CFG(DA830, GPIO3_0, 10, 4, 0xf, 8, false) 642 MUX_CFG(DA830, GPIO3_1, 10, 8, 0xf, 8, false) 643 MUX_CFG(DA830, GPIO3_2, 10, 12, 0xf, 8, false) 644 MUX_CFG(DA830, GPIO3_3, 10, 16, 0xf, 8, false) 645 MUX_CFG(DA830, GPIO3_4, 10, 20, 0xf, 8, false) 646 MUX_CFG(DA830, GPIO3_5, 10, 24, 0xf, 8, false) 647 MUX_CFG(DA830, GPIO3_6, 10, 28, 0xf, 8, false) 648 MUX_CFG(DA830, AXR0_7, 11, 0, 0xf, 1, false) 649 MUX_CFG(DA830, AXR0_8, 11, 4, 0xf, 1, false) 650 MUX_CFG(DA830, UART1_RXD, 11, 8, 0xf, 1, false) 651 MUX_CFG(DA830, UART1_TXD, 11, 12, 0xf, 1, false) 652 MUX_CFG(DA830, AXR0_11, 11, 16, 0xf, 1, false) 653 MUX_CFG(DA830, AHCLKX1, 11, 20, 0xf, 1, false) 654 MUX_CFG(DA830, ACLKX1, 11, 24, 0xf, 1, false) 655 MUX_CFG(DA830, AFSX1, 11, 28, 0xf, 1, false) 656 MUX_CFG(DA830, MDIO_CLK, 11, 0, 0xf, 2, false) 657 MUX_CFG(DA830, MDIO_D, 11, 4, 0xf, 2, false) 658 MUX_CFG(DA830, AXR0_9, 11, 8, 0xf, 2, false) 659 MUX_CFG(DA830, AXR0_10, 11, 12, 0xf, 2, false) 660 MUX_CFG(DA830, EPWM0B, 11, 20, 0xf, 2, false) 661 MUX_CFG(DA830, EPWM0A, 11, 24, 0xf, 2, false) 662 MUX_CFG(DA830, EPWMSYNCI, 11, 28, 0xf, 2, false) 663 MUX_CFG(DA830, AXR2_0, 11, 16, 0xf, 4, false) 664 MUX_CFG(DA830, EPWMSYNC0, 11, 28, 0xf, 4, false) 665 MUX_CFG(DA830, GPIO3_7, 11, 0, 0xf, 8, false) 666 MUX_CFG(DA830, GPIO3_8, 11, 4, 0xf, 8, false) 667 MUX_CFG(DA830, GPIO3_9, 11, 8, 0xf, 8, false) 668 MUX_CFG(DA830, GPIO3_10, 11, 12, 0xf, 8, false) 669 MUX_CFG(DA830, GPIO3_11, 11, 16, 0xf, 8, false) 670 MUX_CFG(DA830, GPIO3_14, 11, 20, 0xf, 8, false) 671 MUX_CFG(DA830, GPIO3_15, 11, 24, 0xf, 8, false) 672 MUX_CFG(DA830, GPIO4_10, 11, 28, 0xf, 8, false) 673 MUX_CFG(DA830, AHCLKR1, 12, 0, 0xf, 1, false) 674 MUX_CFG(DA830, ACLKR1, 12, 4, 0xf, 1, false) 675 MUX_CFG(DA830, AFSR1, 12, 8, 0xf, 1, false) 676 MUX_CFG(DA830, AMUTE1, 12, 12, 0xf, 1, false) 677 MUX_CFG(DA830, AXR1_0, 12, 16, 0xf, 1, false) 678 MUX_CFG(DA830, AXR1_1, 12, 20, 0xf, 1, false) 679 MUX_CFG(DA830, AXR1_2, 12, 24, 0xf, 1, false) 680 MUX_CFG(DA830, AXR1_3, 12, 28, 0xf, 1, false) 681 MUX_CFG(DA830, ECAP2_APWM2, 12, 4, 0xf, 2, false) 682 MUX_CFG(DA830, EHRPWMGLUETZ, 12, 12, 0xf, 2, false) 683 MUX_CFG(DA830, EQEP1A, 12, 28, 0xf, 2, false) 684 MUX_CFG(DA830, GPIO4_11, 12, 0, 0xf, 8, false) 685 MUX_CFG(DA830, GPIO4_12, 12, 4, 0xf, 8, false) 686 MUX_CFG(DA830, GPIO4_13, 12, 8, 0xf, 8, false) 687 MUX_CFG(DA830, GPIO4_14, 12, 12, 0xf, 8, false) 688 MUX_CFG(DA830, GPIO4_0, 12, 16, 0xf, 8, false) 689 MUX_CFG(DA830, GPIO4_1, 12, 20, 0xf, 8, false) 690 MUX_CFG(DA830, GPIO4_2, 12, 24, 0xf, 8, false) 691 MUX_CFG(DA830, GPIO4_3, 12, 28, 0xf, 8, false) 692 MUX_CFG(DA830, AXR1_4, 13, 0, 0xf, 1, false) 693 MUX_CFG(DA830, AXR1_5, 13, 4, 0xf, 1, false) 694 MUX_CFG(DA830, AXR1_6, 13, 8, 0xf, 1, false) 695 MUX_CFG(DA830, AXR1_7, 13, 12, 0xf, 1, false) 696 MUX_CFG(DA830, AXR1_8, 13, 16, 0xf, 1, false) 697 MUX_CFG(DA830, AXR1_9, 13, 20, 0xf, 1, false) 698 MUX_CFG(DA830, EMA_D_0, 13, 24, 0xf, 1, false) 699 MUX_CFG(DA830, EMA_D_1, 13, 28, 0xf, 1, false) 700 MUX_CFG(DA830, EQEP1B, 13, 0, 0xf, 2, false) 701 MUX_CFG(DA830, EPWM2B, 13, 4, 0xf, 2, false) 702 MUX_CFG(DA830, EPWM2A, 13, 8, 0xf, 2, false) 703 MUX_CFG(DA830, EPWM1B, 13, 12, 0xf, 2, false) 704 MUX_CFG(DA830, EPWM1A, 13, 16, 0xf, 2, false) 705 MUX_CFG(DA830, MMCSD_DAT_0, 13, 24, 0xf, 2, false) 706 MUX_CFG(DA830, MMCSD_DAT_1, 13, 28, 0xf, 2, false) 707 MUX_CFG(DA830, UHPI_HD_0, 13, 24, 0xf, 4, false) 708 MUX_CFG(DA830, UHPI_HD_1, 13, 28, 0xf, 4, false) 709 MUX_CFG(DA830, GPIO4_4, 13, 0, 0xf, 8, false) 710 MUX_CFG(DA830, GPIO4_5, 13, 4, 0xf, 8, false) 711 MUX_CFG(DA830, GPIO4_6, 13, 8, 0xf, 8, false) 712 MUX_CFG(DA830, GPIO4_7, 13, 12, 0xf, 8, false) 713 MUX_CFG(DA830, GPIO4_8, 13, 16, 0xf, 8, false) 714 MUX_CFG(DA830, GPIO4_9, 13, 20, 0xf, 8, false) 715 MUX_CFG(DA830, GPIO0_0, 13, 24, 0xf, 8, false) 716 MUX_CFG(DA830, GPIO0_1, 13, 28, 0xf, 8, false) 717 MUX_CFG(DA830, EMA_D_2, 14, 0, 0xf, 1, false) 718 MUX_CFG(DA830, EMA_D_3, 14, 4, 0xf, 1, false) 719 MUX_CFG(DA830, EMA_D_4, 14, 8, 0xf, 1, false) 720 MUX_CFG(DA830, EMA_D_5, 14, 12, 0xf, 1, false) 721 MUX_CFG(DA830, EMA_D_6, 14, 16, 0xf, 1, false) 722 MUX_CFG(DA830, EMA_D_7, 14, 20, 0xf, 1, false) 723 MUX_CFG(DA830, EMA_D_8, 14, 24, 0xf, 1, false) 724 MUX_CFG(DA830, EMA_D_9, 14, 28, 0xf, 1, false) 725 MUX_CFG(DA830, MMCSD_DAT_2, 14, 0, 0xf, 2, false) 726 MUX_CFG(DA830, MMCSD_DAT_3, 14, 4, 0xf, 2, false) 727 MUX_CFG(DA830, MMCSD_DAT_4, 14, 8, 0xf, 2, false) 728 MUX_CFG(DA830, MMCSD_DAT_5, 14, 12, 0xf, 2, false) 729 MUX_CFG(DA830, MMCSD_DAT_6, 14, 16, 0xf, 2, false) 730 MUX_CFG(DA830, MMCSD_DAT_7, 14, 20, 0xf, 2, false) 731 MUX_CFG(DA830, UHPI_HD_8, 14, 24, 0xf, 2, false) 732 MUX_CFG(DA830, UHPI_HD_9, 14, 28, 0xf, 2, false) 733 MUX_CFG(DA830, UHPI_HD_2, 14, 0, 0xf, 4, false) 734 MUX_CFG(DA830, UHPI_HD_3, 14, 4, 0xf, 4, false) 735 MUX_CFG(DA830, UHPI_HD_4, 14, 8, 0xf, 4, false) 736 MUX_CFG(DA830, UHPI_HD_5, 14, 12, 0xf, 4, false) 737 MUX_CFG(DA830, UHPI_HD_6, 14, 16, 0xf, 4, false) 738 MUX_CFG(DA830, UHPI_HD_7, 14, 20, 0xf, 4, false) 739 MUX_CFG(DA830, LCD_D_8, 14, 24, 0xf, 4, false) 740 MUX_CFG(DA830, LCD_D_9, 14, 28, 0xf, 4, false) 741 MUX_CFG(DA830, GPIO0_2, 14, 0, 0xf, 8, false) 742 MUX_CFG(DA830, GPIO0_3, 14, 4, 0xf, 8, false) 743 MUX_CFG(DA830, GPIO0_4, 14, 8, 0xf, 8, false) 744 MUX_CFG(DA830, GPIO0_5, 14, 12, 0xf, 8, false) 745 MUX_CFG(DA830, GPIO0_6, 14, 16, 0xf, 8, false) 746 MUX_CFG(DA830, GPIO0_7, 14, 20, 0xf, 8, false) 747 MUX_CFG(DA830, GPIO0_8, 14, 24, 0xf, 8, false) 748 MUX_CFG(DA830, GPIO0_9, 14, 28, 0xf, 8, false) 749 MUX_CFG(DA830, EMA_D_10, 15, 0, 0xf, 1, false) 750 MUX_CFG(DA830, EMA_D_11, 15, 4, 0xf, 1, false) 751 MUX_CFG(DA830, EMA_D_12, 15, 8, 0xf, 1, false) 752 MUX_CFG(DA830, EMA_D_13, 15, 12, 0xf, 1, false) 753 MUX_CFG(DA830, EMA_D_14, 15, 16, 0xf, 1, false) 754 MUX_CFG(DA830, EMA_D_15, 15, 20, 0xf, 1, false) 755 MUX_CFG(DA830, EMA_A_0, 15, 24, 0xf, 1, false) 756 MUX_CFG(DA830, EMA_A_1, 15, 28, 0xf, 1, false) 757 MUX_CFG(DA830, UHPI_HD_10, 15, 0, 0xf, 2, false) 758 MUX_CFG(DA830, UHPI_HD_11, 15, 4, 0xf, 2, false) 759 MUX_CFG(DA830, UHPI_HD_12, 15, 8, 0xf, 2, false) 760 MUX_CFG(DA830, UHPI_HD_13, 15, 12, 0xf, 2, false) 761 MUX_CFG(DA830, UHPI_HD_14, 15, 16, 0xf, 2, false) 762 MUX_CFG(DA830, UHPI_HD_15, 15, 20, 0xf, 2, false) 763 MUX_CFG(DA830, LCD_D_7, 15, 24, 0xf, 2, false) 764 MUX_CFG(DA830, MMCSD_CLK, 15, 28, 0xf, 2, false) 765 MUX_CFG(DA830, LCD_D_10, 15, 0, 0xf, 4, false) 766 MUX_CFG(DA830, LCD_D_11, 15, 4, 0xf, 4, false) 767 MUX_CFG(DA830, LCD_D_12, 15, 8, 0xf, 4, false) 768 MUX_CFG(DA830, LCD_D_13, 15, 12, 0xf, 4, false) 769 MUX_CFG(DA830, LCD_D_14, 15, 16, 0xf, 4, false) 770 MUX_CFG(DA830, LCD_D_15, 15, 20, 0xf, 4, false) 771 MUX_CFG(DA830, UHPI_HCNTL0, 15, 28, 0xf, 4, false) 772 MUX_CFG(DA830, GPIO0_10, 15, 0, 0xf, 8, false) 773 MUX_CFG(DA830, GPIO0_11, 15, 4, 0xf, 8, false) 774 MUX_CFG(DA830, GPIO0_12, 15, 8, 0xf, 8, false) 775 MUX_CFG(DA830, GPIO0_13, 15, 12, 0xf, 8, false) 776 MUX_CFG(DA830, GPIO0_14, 15, 16, 0xf, 8, false) 777 MUX_CFG(DA830, GPIO0_15, 15, 20, 0xf, 8, false) 778 MUX_CFG(DA830, GPIO1_0, 15, 24, 0xf, 8, false) 779 MUX_CFG(DA830, GPIO1_1, 15, 28, 0xf, 8, false) 780 MUX_CFG(DA830, EMA_A_2, 16, 0, 0xf, 1, false) 781 MUX_CFG(DA830, EMA_A_3, 16, 4, 0xf, 1, false) 782 MUX_CFG(DA830, EMA_A_4, 16, 8, 0xf, 1, false) 783 MUX_CFG(DA830, EMA_A_5, 16, 12, 0xf, 1, false) 784 MUX_CFG(DA830, EMA_A_6, 16, 16, 0xf, 1, false) 785 MUX_CFG(DA830, EMA_A_7, 16, 20, 0xf, 1, false) 786 MUX_CFG(DA830, EMA_A_8, 16, 24, 0xf, 1, false) 787 MUX_CFG(DA830, EMA_A_9, 16, 28, 0xf, 1, false) 788 MUX_CFG(DA830, MMCSD_CMD, 16, 0, 0xf, 2, false) 789 MUX_CFG(DA830, LCD_D_6, 16, 4, 0xf, 2, false) 790 MUX_CFG(DA830, LCD_D_3, 16, 8, 0xf, 2, false) 791 MUX_CFG(DA830, LCD_D_2, 16, 12, 0xf, 2, false) 792 MUX_CFG(DA830, LCD_D_1, 16, 16, 0xf, 2, false) 793 MUX_CFG(DA830, LCD_D_0, 16, 20, 0xf, 2, false) 794 MUX_CFG(DA830, LCD_PCLK, 16, 24, 0xf, 2, false) 795 MUX_CFG(DA830, LCD_HSYNC, 16, 28, 0xf, 2, false) 796 MUX_CFG(DA830, UHPI_HCNTL1, 16, 0, 0xf, 4, false) 797 MUX_CFG(DA830, GPIO1_2, 16, 0, 0xf, 8, false) 798 MUX_CFG(DA830, GPIO1_3, 16, 4, 0xf, 8, false) 799 MUX_CFG(DA830, GPIO1_4, 16, 8, 0xf, 8, false) 800 MUX_CFG(DA830, GPIO1_5, 16, 12, 0xf, 8, false) 801 MUX_CFG(DA830, GPIO1_6, 16, 16, 0xf, 8, false) 802 MUX_CFG(DA830, GPIO1_7, 16, 20, 0xf, 8, false) 803 MUX_CFG(DA830, GPIO1_8, 16, 24, 0xf, 8, false) 804 MUX_CFG(DA830, GPIO1_9, 16, 28, 0xf, 8, false) 805 MUX_CFG(DA830, EMA_A_10, 17, 0, 0xf, 1, false) 806 MUX_CFG(DA830, EMA_A_11, 17, 4, 0xf, 1, false) 807 MUX_CFG(DA830, EMA_A_12, 17, 8, 0xf, 1, false) 808 MUX_CFG(DA830, EMA_BA_1, 17, 12, 0xf, 1, false) 809 MUX_CFG(DA830, EMA_BA_0, 17, 16, 0xf, 1, false) 810 MUX_CFG(DA830, EMA_CLK, 17, 20, 0xf, 1, false) 811 MUX_CFG(DA830, EMA_SDCKE, 17, 24, 0xf, 1, false) 812 MUX_CFG(DA830, NEMA_CAS, 17, 28, 0xf, 1, false) 813 MUX_CFG(DA830, LCD_VSYNC, 17, 0, 0xf, 2, false) 814 MUX_CFG(DA830, NLCD_AC_ENB_CS, 17, 4, 0xf, 2, false) 815 MUX_CFG(DA830, LCD_MCLK, 17, 8, 0xf, 2, false) 816 MUX_CFG(DA830, LCD_D_5, 17, 12, 0xf, 2, false) 817 MUX_CFG(DA830, LCD_D_4, 17, 16, 0xf, 2, false) 818 MUX_CFG(DA830, OBSCLK, 17, 20, 0xf, 2, false) 819 MUX_CFG(DA830, NEMA_CS_4, 17, 28, 0xf, 2, false) 820 MUX_CFG(DA830, UHPI_HHWIL, 17, 12, 0xf, 4, false) 821 MUX_CFG(DA830, AHCLKR2, 17, 20, 0xf, 4, false) 822 MUX_CFG(DA830, GPIO1_10, 17, 0, 0xf, 8, false) 823 MUX_CFG(DA830, GPIO1_11, 17, 4, 0xf, 8, false) 824 MUX_CFG(DA830, GPIO1_12, 17, 8, 0xf, 8, false) 825 MUX_CFG(DA830, GPIO1_13, 17, 12, 0xf, 8, false) 826 MUX_CFG(DA830, GPIO1_14, 17, 16, 0xf, 8, false) 827 MUX_CFG(DA830, GPIO1_15, 17, 20, 0xf, 8, false) 828 MUX_CFG(DA830, GPIO2_0, 17, 24, 0xf, 8, false) 829 MUX_CFG(DA830, GPIO2_1, 17, 28, 0xf, 8, false) 830 MUX_CFG(DA830, NEMA_RAS, 18, 0, 0xf, 1, false) 831 MUX_CFG(DA830, NEMA_WE, 18, 4, 0xf, 1, false) 832 MUX_CFG(DA830, NEMA_CS_0, 18, 8, 0xf, 1, false) 833 MUX_CFG(DA830, NEMA_CS_2, 18, 12, 0xf, 1, false) 834 MUX_CFG(DA830, NEMA_CS_3, 18, 16, 0xf, 1, false) 835 MUX_CFG(DA830, NEMA_OE, 18, 20, 0xf, 1, false) 836 MUX_CFG(DA830, NEMA_WE_DQM_1, 18, 24, 0xf, 1, false) 837 MUX_CFG(DA830, NEMA_WE_DQM_0, 18, 28, 0xf, 1, false) 838 MUX_CFG(DA830, NEMA_CS_5, 18, 0, 0xf, 2, false) 839 MUX_CFG(DA830, UHPI_HRNW, 18, 4, 0xf, 2, false) 840 MUX_CFG(DA830, NUHPI_HAS, 18, 8, 0xf, 2, false) 841 MUX_CFG(DA830, NUHPI_HCS, 18, 12, 0xf, 2, false) 842 MUX_CFG(DA830, NUHPI_HDS1, 18, 20, 0xf, 2, false) 843 MUX_CFG(DA830, NUHPI_HDS2, 18, 24, 0xf, 2, false) 844 MUX_CFG(DA830, NUHPI_HINT, 18, 28, 0xf, 2, false) 845 MUX_CFG(DA830, AXR0_12, 18, 4, 0xf, 4, false) 846 MUX_CFG(DA830, AMUTE2, 18, 16, 0xf, 4, false) 847 MUX_CFG(DA830, AXR0_13, 18, 20, 0xf, 4, false) 848 MUX_CFG(DA830, AXR0_14, 18, 24, 0xf, 4, false) 849 MUX_CFG(DA830, AXR0_15, 18, 28, 0xf, 4, false) 850 MUX_CFG(DA830, GPIO2_2, 18, 0, 0xf, 8, false) 851 MUX_CFG(DA830, GPIO2_3, 18, 4, 0xf, 8, false) 852 MUX_CFG(DA830, GPIO2_4, 18, 8, 0xf, 8, false) 853 MUX_CFG(DA830, GPIO2_5, 18, 12, 0xf, 8, false) 854 MUX_CFG(DA830, GPIO2_6, 18, 16, 0xf, 8, false) 855 MUX_CFG(DA830, GPIO2_7, 18, 20, 0xf, 8, false) 856 MUX_CFG(DA830, GPIO2_8, 18, 24, 0xf, 8, false) 857 MUX_CFG(DA830, GPIO2_9, 18, 28, 0xf, 8, false) 858 MUX_CFG(DA830, EMA_WAIT_0, 19, 0, 0xf, 1, false) 859 MUX_CFG(DA830, NUHPI_HRDY, 19, 0, 0xf, 2, false) 860 MUX_CFG(DA830, GPIO2_10, 19, 0, 0xf, 8, false) 861 #endif 862 }; 863 864 const short da830_emif25_pins[] __initdata = { 865 DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3, 866 DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7, 867 DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11, 868 DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15, 869 DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3, 870 DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7, 871 DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11, 872 DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK, 873 DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE, 874 DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, 875 DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0, 876 -1 877 }; 878 879 const short da830_spi0_pins[] __initdata = { 880 DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA, 881 DA830_NSPI0_SCS_0, 882 -1 883 }; 884 885 const short da830_spi1_pins[] __initdata = { 886 DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA, 887 DA830_NSPI1_SCS_0, 888 -1 889 }; 890 891 const short da830_mmc_sd_pins[] __initdata = { 892 DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2, 893 DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5, 894 DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK, 895 DA830_MMCSD_CMD, 896 -1 897 }; 898 899 const short da830_uart0_pins[] __initdata = { 900 DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD, 901 -1 902 }; 903 904 const short da830_uart1_pins[] __initdata = { 905 DA830_UART1_RXD, DA830_UART1_TXD, 906 -1 907 }; 908 909 const short da830_uart2_pins[] __initdata = { 910 DA830_UART2_RXD, DA830_UART2_TXD, 911 -1 912 }; 913 914 const short da830_usb20_pins[] __initdata = { 915 DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN, 916 -1 917 }; 918 919 const short da830_usb11_pins[] __initdata = { 920 DA830_USB_REFCLKIN, 921 -1 922 }; 923 924 const short da830_uhpi_pins[] __initdata = { 925 DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3, 926 DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7, 927 DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11, 928 DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15, 929 DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW, 930 DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2, 931 DA830_NUHPI_HINT, DA830_NUHPI_HRDY, 932 -1 933 }; 934 935 const short da830_cpgmac_pins[] __initdata = { 936 DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV, 937 DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK, 938 DA830_MDIO_D, 939 -1 940 }; 941 942 const short da830_emif3c_pins[] __initdata = { 943 DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0, 944 DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1, 945 DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2, 946 DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6, 947 DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10, 948 DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3, 949 DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2, 950 DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6, 951 DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10, 952 DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14, 953 DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18, 954 DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22, 955 DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26, 956 DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30, 957 DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0, 958 -1 959 }; 960 961 const short da830_mcasp0_pins[] __initdata = { 962 DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0, 963 DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0, 964 DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3, 965 DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7, 966 DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11, 967 DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15, 968 -1 969 }; 970 971 const short da830_mcasp1_pins[] __initdata = { 972 DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, 973 DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1, 974 DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3, 975 DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7, 976 DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11, 977 -1 978 }; 979 980 const short da830_mcasp2_pins[] __initdata = { 981 DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2, 982 DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2, 983 DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3, 984 -1 985 }; 986 987 const short da830_i2c0_pins[] __initdata = { 988 DA830_I2C0_SDA, DA830_I2C0_SCL, 989 -1 990 }; 991 992 const short da830_i2c1_pins[] __initdata = { 993 DA830_I2C1_SCL, DA830_I2C1_SDA, 994 -1 995 }; 996 997 const short da830_lcdcntl_pins[] __initdata = { 998 DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3, 999 DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7, 1000 DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11, 1001 DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15, 1002 DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS, 1003 DA830_LCD_MCLK, 1004 -1 1005 }; 1006 1007 const short da830_pwm_pins[] __initdata = { 1008 DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A, 1009 DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ, 1010 DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A, 1011 -1 1012 }; 1013 1014 const short da830_ecap0_pins[] __initdata = { 1015 DA830_ECAP0_APWM0, 1016 -1 1017 }; 1018 1019 const short da830_ecap1_pins[] __initdata = { 1020 DA830_ECAP1_APWM1, 1021 -1 1022 }; 1023 1024 const short da830_ecap2_pins[] __initdata = { 1025 DA830_ECAP2_APWM2, 1026 -1 1027 }; 1028 1029 const short da830_eqep0_pins[] __initdata = { 1030 DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B, 1031 -1 1032 }; 1033 1034 const short da830_eqep1_pins[] __initdata = { 1035 DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B, 1036 -1 1037 }; 1038 1039 int da830_pinmux_setup(const short pins[]) 1040 { 1041 int i, error = -EINVAL; 1042 1043 if (pins) 1044 for (i = 0; pins[i] >= 0; i++) { 1045 error = davinci_cfg_reg(pins[i]); 1046 if (error) 1047 break; 1048 } 1049 1050 return error; 1051 } 1052 1053 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ 1054 static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = { 1055 [IRQ_DA8XX_COMMTX] = 7, 1056 [IRQ_DA8XX_COMMRX] = 7, 1057 [IRQ_DA8XX_NINT] = 7, 1058 [IRQ_DA8XX_EVTOUT0] = 7, 1059 [IRQ_DA8XX_EVTOUT1] = 7, 1060 [IRQ_DA8XX_EVTOUT2] = 7, 1061 [IRQ_DA8XX_EVTOUT3] = 7, 1062 [IRQ_DA8XX_EVTOUT4] = 7, 1063 [IRQ_DA8XX_EVTOUT5] = 7, 1064 [IRQ_DA8XX_EVTOUT6] = 7, 1065 [IRQ_DA8XX_EVTOUT6] = 7, 1066 [IRQ_DA8XX_EVTOUT7] = 7, 1067 [IRQ_DA8XX_CCINT0] = 7, 1068 [IRQ_DA8XX_CCERRINT] = 7, 1069 [IRQ_DA8XX_TCERRINT0] = 7, 1070 [IRQ_DA8XX_AEMIFINT] = 7, 1071 [IRQ_DA8XX_I2CINT0] = 7, 1072 [IRQ_DA8XX_MMCSDINT0] = 7, 1073 [IRQ_DA8XX_MMCSDINT1] = 7, 1074 [IRQ_DA8XX_ALLINT0] = 7, 1075 [IRQ_DA8XX_RTC] = 7, 1076 [IRQ_DA8XX_SPINT0] = 7, 1077 [IRQ_DA8XX_TINT12_0] = 7, 1078 [IRQ_DA8XX_TINT34_0] = 7, 1079 [IRQ_DA8XX_TINT12_1] = 7, 1080 [IRQ_DA8XX_TINT34_1] = 7, 1081 [IRQ_DA8XX_UARTINT0] = 7, 1082 [IRQ_DA8XX_KEYMGRINT] = 7, 1083 [IRQ_DA8XX_SECINT] = 7, 1084 [IRQ_DA8XX_SECKEYERR] = 7, 1085 [IRQ_DA830_MPUERR] = 7, 1086 [IRQ_DA830_IOPUERR] = 7, 1087 [IRQ_DA830_BOOTCFGERR] = 7, 1088 [IRQ_DA8XX_CHIPINT0] = 7, 1089 [IRQ_DA8XX_CHIPINT1] = 7, 1090 [IRQ_DA8XX_CHIPINT2] = 7, 1091 [IRQ_DA8XX_CHIPINT3] = 7, 1092 [IRQ_DA8XX_TCERRINT1] = 7, 1093 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, 1094 [IRQ_DA8XX_C0_RX_PULSE] = 7, 1095 [IRQ_DA8XX_C0_TX_PULSE] = 7, 1096 [IRQ_DA8XX_C0_MISC_PULSE] = 7, 1097 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, 1098 [IRQ_DA8XX_C1_RX_PULSE] = 7, 1099 [IRQ_DA8XX_C1_TX_PULSE] = 7, 1100 [IRQ_DA8XX_C1_MISC_PULSE] = 7, 1101 [IRQ_DA8XX_MEMERR] = 7, 1102 [IRQ_DA8XX_GPIO0] = 7, 1103 [IRQ_DA8XX_GPIO1] = 7, 1104 [IRQ_DA8XX_GPIO2] = 7, 1105 [IRQ_DA8XX_GPIO3] = 7, 1106 [IRQ_DA8XX_GPIO4] = 7, 1107 [IRQ_DA8XX_GPIO5] = 7, 1108 [IRQ_DA8XX_GPIO6] = 7, 1109 [IRQ_DA8XX_GPIO7] = 7, 1110 [IRQ_DA8XX_GPIO8] = 7, 1111 [IRQ_DA8XX_I2CINT1] = 7, 1112 [IRQ_DA8XX_LCDINT] = 7, 1113 [IRQ_DA8XX_UARTINT1] = 7, 1114 [IRQ_DA8XX_MCASPINT] = 7, 1115 [IRQ_DA8XX_ALLINT1] = 7, 1116 [IRQ_DA8XX_SPINT1] = 7, 1117 [IRQ_DA8XX_UHPI_INT1] = 7, 1118 [IRQ_DA8XX_USB_INT] = 7, 1119 [IRQ_DA8XX_IRQN] = 7, 1120 [IRQ_DA8XX_RWAKEUP] = 7, 1121 [IRQ_DA8XX_UARTINT2] = 7, 1122 [IRQ_DA8XX_DFTSSINT] = 7, 1123 [IRQ_DA8XX_EHRPWM0] = 7, 1124 [IRQ_DA8XX_EHRPWM0TZ] = 7, 1125 [IRQ_DA8XX_EHRPWM1] = 7, 1126 [IRQ_DA8XX_EHRPWM1TZ] = 7, 1127 [IRQ_DA830_EHRPWM2] = 7, 1128 [IRQ_DA830_EHRPWM2TZ] = 7, 1129 [IRQ_DA8XX_ECAP0] = 7, 1130 [IRQ_DA8XX_ECAP1] = 7, 1131 [IRQ_DA8XX_ECAP2] = 7, 1132 [IRQ_DA830_EQEP0] = 7, 1133 [IRQ_DA830_EQEP1] = 7, 1134 [IRQ_DA830_T12CMPINT0_0] = 7, 1135 [IRQ_DA830_T12CMPINT1_0] = 7, 1136 [IRQ_DA830_T12CMPINT2_0] = 7, 1137 [IRQ_DA830_T12CMPINT3_0] = 7, 1138 [IRQ_DA830_T12CMPINT4_0] = 7, 1139 [IRQ_DA830_T12CMPINT5_0] = 7, 1140 [IRQ_DA830_T12CMPINT6_0] = 7, 1141 [IRQ_DA830_T12CMPINT7_0] = 7, 1142 [IRQ_DA830_T12CMPINT0_1] = 7, 1143 [IRQ_DA830_T12CMPINT1_1] = 7, 1144 [IRQ_DA830_T12CMPINT2_1] = 7, 1145 [IRQ_DA830_T12CMPINT3_1] = 7, 1146 [IRQ_DA830_T12CMPINT4_1] = 7, 1147 [IRQ_DA830_T12CMPINT5_1] = 7, 1148 [IRQ_DA830_T12CMPINT6_1] = 7, 1149 [IRQ_DA830_T12CMPINT7_1] = 7, 1150 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, 1151 }; 1152 1153 static struct map_desc da830_io_desc[] = { 1154 { 1155 .virtual = IO_VIRT, 1156 .pfn = __phys_to_pfn(IO_PHYS), 1157 .length = IO_SIZE, 1158 .type = MT_DEVICE 1159 }, 1160 { 1161 .virtual = DA8XX_CP_INTC_VIRT, 1162 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), 1163 .length = DA8XX_CP_INTC_SIZE, 1164 .type = MT_DEVICE 1165 }, 1166 }; 1167 1168 static void __iomem *da830_psc_bases[] = { 1169 IO_ADDRESS(DA8XX_PSC0_BASE), 1170 IO_ADDRESS(DA8XX_PSC1_BASE), 1171 }; 1172 1173 /* Contents of JTAG ID register used to identify exact cpu type */ 1174 static struct davinci_id da830_ids[] = { 1175 { 1176 .variant = 0x0, 1177 .part_no = 0xb7df, 1178 .manufacturer = 0x017, /* 0x02f >> 1 */ 1179 .cpu_id = DAVINCI_CPU_ID_DA830, 1180 .name = "da830/omap l137", 1181 }, 1182 }; 1183 1184 static struct davinci_timer_instance da830_timer_instance[2] = { 1185 { 1186 .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE), 1187 .bottom_irq = IRQ_DA8XX_TINT12_0, 1188 .top_irq = IRQ_DA8XX_TINT34_0, 1189 .cmp_off = DA830_CMP12_0, 1190 .cmp_irq = IRQ_DA830_T12CMPINT0_0, 1191 }, 1192 { 1193 .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE), 1194 .bottom_irq = IRQ_DA8XX_TINT12_1, 1195 .top_irq = IRQ_DA8XX_TINT34_1, 1196 .cmp_off = DA830_CMP12_0, 1197 .cmp_irq = IRQ_DA830_T12CMPINT0_1, 1198 }, 1199 }; 1200 1201 /* 1202 * T0_BOT: Timer 0, bottom : Used for clock_event & clocksource 1203 * T0_TOP: Timer 0, top : Used by DSP 1204 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer 1205 */ 1206 static struct davinci_timer_info da830_timer_info = { 1207 .timers = da830_timer_instance, 1208 .clockevent_id = T0_BOT, 1209 .clocksource_id = T0_BOT, 1210 }; 1211 1212 static struct davinci_soc_info davinci_soc_info_da830 = { 1213 .io_desc = da830_io_desc, 1214 .io_desc_num = ARRAY_SIZE(da830_io_desc), 1215 .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG), 1216 .ids = da830_ids, 1217 .ids_num = ARRAY_SIZE(da830_ids), 1218 .cpu_clks = da830_clks, 1219 .psc_bases = da830_psc_bases, 1220 .psc_bases_num = ARRAY_SIZE(da830_psc_bases), 1221 .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120), 1222 .pinmux_pins = da830_pins, 1223 .pinmux_pins_num = ARRAY_SIZE(da830_pins), 1224 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, 1225 .intc_type = DAVINCI_INTC_TYPE_CP_INTC, 1226 .intc_irq_prios = da830_default_priorities, 1227 .intc_irq_num = DA830_N_CP_INTC_IRQ, 1228 .timer_info = &da830_timer_info, 1229 .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE), 1230 .gpio_num = 128, 1231 .gpio_irq = IRQ_DA8XX_GPIO0, 1232 .serial_dev = &da8xx_serial_device, 1233 .emac_pdata = &da8xx_emac_pdata, 1234 }; 1235 1236 void __init da830_init(void) 1237 { 1238 davinci_common_init(&davinci_soc_info_da830); 1239 } 1240