1 /* 2 * CPU idle for DaVinci SoCs 3 * 4 * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/ 5 * 6 * Derived from Marvell Kirkwood CPU idle code 7 * (arch/arm/mach-kirkwood/cpuidle.c) 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 #include <linux/platform_device.h> 17 #include <linux/cpuidle.h> 18 #include <linux/io.h> 19 #include <asm/proc-fns.h> 20 21 #include <mach/cpuidle.h> 22 23 #define DAVINCI_CPUIDLE_MAX_STATES 2 24 25 struct davinci_ops { 26 void (*enter) (u32 flags); 27 void (*exit) (u32 flags); 28 u32 flags; 29 }; 30 31 /* fields in davinci_ops.flags */ 32 #define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN BIT(0) 33 34 static struct cpuidle_driver davinci_idle_driver = { 35 .name = "cpuidle-davinci", 36 .owner = THIS_MODULE, 37 }; 38 39 static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device); 40 static void __iomem *ddr2_reg_base; 41 42 #define DDR2_SDRCR_OFFSET 0xc 43 #define DDR2_SRPD_BIT BIT(23) 44 #define DDR2_LPMODEN_BIT BIT(31) 45 46 static void davinci_save_ddr_power(int enter, bool pdown) 47 { 48 u32 val; 49 50 val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET); 51 52 if (enter) { 53 if (pdown) 54 val |= DDR2_SRPD_BIT; 55 else 56 val &= ~DDR2_SRPD_BIT; 57 val |= DDR2_LPMODEN_BIT; 58 } else { 59 val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT); 60 } 61 62 __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET); 63 } 64 65 static void davinci_c2state_enter(u32 flags) 66 { 67 davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN)); 68 } 69 70 static void davinci_c2state_exit(u32 flags) 71 { 72 davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN)); 73 } 74 75 static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = { 76 [1] = { 77 .enter = davinci_c2state_enter, 78 .exit = davinci_c2state_exit, 79 }, 80 }; 81 82 /* Actual code that puts the SoC in different idle states */ 83 static int davinci_enter_idle(struct cpuidle_device *dev, 84 struct cpuidle_state *state) 85 { 86 struct davinci_ops *ops = cpuidle_get_statedata(state); 87 struct timeval before, after; 88 int idle_time; 89 90 local_irq_disable(); 91 do_gettimeofday(&before); 92 93 if (ops && ops->enter) 94 ops->enter(ops->flags); 95 /* Wait for interrupt state */ 96 cpu_do_idle(); 97 if (ops && ops->exit) 98 ops->exit(ops->flags); 99 100 do_gettimeofday(&after); 101 local_irq_enable(); 102 idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + 103 (after.tv_usec - before.tv_usec); 104 return idle_time; 105 } 106 107 static int __init davinci_cpuidle_probe(struct platform_device *pdev) 108 { 109 int ret; 110 struct cpuidle_device *device; 111 struct davinci_cpuidle_config *pdata = pdev->dev.platform_data; 112 struct resource *ddr2_regs; 113 resource_size_t len; 114 115 device = &per_cpu(davinci_cpuidle_device, smp_processor_id()); 116 117 if (!pdata) { 118 dev_err(&pdev->dev, "cannot get platform data\n"); 119 return -ENOENT; 120 } 121 122 ddr2_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 123 if (!ddr2_regs) { 124 dev_err(&pdev->dev, "cannot get DDR2 controller register base"); 125 return -ENODEV; 126 } 127 128 len = resource_size(ddr2_regs); 129 130 ddr2_regs = request_mem_region(ddr2_regs->start, len, ddr2_regs->name); 131 if (!ddr2_regs) 132 return -EBUSY; 133 134 ddr2_reg_base = ioremap(ddr2_regs->start, len); 135 if (!ddr2_reg_base) { 136 ret = -ENOMEM; 137 goto ioremap_fail; 138 } 139 140 ret = cpuidle_register_driver(&davinci_idle_driver); 141 if (ret) { 142 dev_err(&pdev->dev, "failed to register driver\n"); 143 goto driver_register_fail; 144 } 145 146 /* Wait for interrupt state */ 147 device->states[0].enter = davinci_enter_idle; 148 device->states[0].exit_latency = 1; 149 device->states[0].target_residency = 10000; 150 device->states[0].flags = CPUIDLE_FLAG_TIME_VALID; 151 strcpy(device->states[0].name, "WFI"); 152 strcpy(device->states[0].desc, "Wait for interrupt"); 153 154 /* Wait for interrupt and DDR self refresh state */ 155 device->states[1].enter = davinci_enter_idle; 156 device->states[1].exit_latency = 10; 157 device->states[1].target_residency = 10000; 158 device->states[1].flags = CPUIDLE_FLAG_TIME_VALID; 159 strcpy(device->states[1].name, "DDR SR"); 160 strcpy(device->states[1].desc, "WFI and DDR Self Refresh"); 161 if (pdata->ddr2_pdown) 162 davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN; 163 cpuidle_set_statedata(&device->states[1], &davinci_states[1]); 164 165 device->state_count = DAVINCI_CPUIDLE_MAX_STATES; 166 167 ret = cpuidle_register_device(device); 168 if (ret) { 169 dev_err(&pdev->dev, "failed to register device\n"); 170 goto device_register_fail; 171 } 172 173 return 0; 174 175 device_register_fail: 176 cpuidle_unregister_driver(&davinci_idle_driver); 177 driver_register_fail: 178 iounmap(ddr2_reg_base); 179 ioremap_fail: 180 release_mem_region(ddr2_regs->start, len); 181 return ret; 182 } 183 184 static struct platform_driver davinci_cpuidle_driver = { 185 .driver = { 186 .name = "cpuidle-davinci", 187 .owner = THIS_MODULE, 188 }, 189 }; 190 191 static int __init davinci_cpuidle_init(void) 192 { 193 return platform_driver_probe(&davinci_cpuidle_driver, 194 davinci_cpuidle_probe); 195 } 196 device_initcall(davinci_cpuidle_init); 197 198