1 /* 2 * TI DaVinci clock definitions 3 * 4 * Copyright (C) 2006-2007 Texas Instruments. 5 * Copyright (C) 2008-2009 Deep Root Systems, LLC 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #ifndef __ARCH_ARM_DAVINCI_CLOCK_H 13 #define __ARCH_ARM_DAVINCI_CLOCK_H 14 15 /* PLL/Reset register offsets */ 16 #define PLLCTL 0x100 17 #define PLLCTL_PLLEN BIT(0) 18 #define PLLCTL_PLLPWRDN BIT(1) 19 #define PLLCTL_PLLRST BIT(3) 20 #define PLLCTL_PLLDIS BIT(4) 21 #define PLLCTL_PLLENSRC BIT(5) 22 #define PLLCTL_CLKMODE BIT(8) 23 24 #define PLLM 0x110 25 #define PLLM_PLLM_MASK 0xff 26 27 #define PREDIV 0x114 28 #define PLLDIV1 0x118 29 #define PLLDIV2 0x11c 30 #define PLLDIV3 0x120 31 #define POSTDIV 0x128 32 #define BPDIV 0x12c 33 #define PLLCMD 0x138 34 #define PLLSTAT 0x13c 35 #define PLLALNCTL 0x140 36 #define PLLDCHANGE 0x144 37 #define PLLCKEN 0x148 38 #define PLLCKSTAT 0x14c 39 #define PLLSYSTAT 0x150 40 #define PLLDIV4 0x160 41 #define PLLDIV5 0x164 42 #define PLLDIV6 0x168 43 #define PLLDIV7 0x16c 44 #define PLLDIV8 0x170 45 #define PLLDIV9 0x174 46 #define PLLDIV_EN BIT(15) 47 #define PLLDIV_RATIO_MASK 0x1f 48 49 /* 50 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN 51 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us 52 * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input 53 * is ~25MHz. Units are micro seconds. 54 */ 55 #define PLL_BYPASS_TIME 1 56 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */ 57 #define PLL_RESET_TIME 1 58 /* 59 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4 60 * Units are micro seconds. 61 */ 62 #define PLL_LOCK_TIME 20 63 64 #ifndef __ASSEMBLER__ 65 66 #include <linux/list.h> 67 #include <linux/clkdev.h> 68 69 #define PLLSTAT_GOSTAT BIT(0) 70 #define PLLCMD_GOSET BIT(0) 71 72 struct pll_data { 73 u32 phys_base; 74 void __iomem *base; 75 u32 num; 76 u32 flags; 77 u32 input_rate; 78 u32 div_ratio_mask; 79 }; 80 #define PLL_HAS_PREDIV 0x01 81 #define PLL_HAS_POSTDIV 0x02 82 83 struct clk { 84 struct list_head node; 85 struct module *owner; 86 const char *name; 87 unsigned long rate; 88 unsigned long maxrate; /* H/W supported max rate */ 89 u8 usecount; 90 u8 lpsc; 91 u8 gpsc; 92 u8 domain; 93 u32 flags; 94 struct clk *parent; 95 struct list_head children; /* list of children */ 96 struct list_head childnode; /* parent's child list node */ 97 struct pll_data *pll_data; 98 u32 div_reg; 99 unsigned long (*recalc) (struct clk *); 100 int (*set_rate) (struct clk *clk, unsigned long rate); 101 int (*round_rate) (struct clk *clk, unsigned long rate); 102 int (*reset) (struct clk *clk, bool reset); 103 void (*clk_enable) (struct clk *clk); 104 void (*clk_disable) (struct clk *clk); 105 int (*set_parent) (struct clk *clk, struct clk *parent); 106 }; 107 108 /* Clock flags: SoC-specific flags start at BIT(16) */ 109 #define ALWAYS_ENABLED BIT(1) 110 #define CLK_PSC BIT(2) 111 #define CLK_PLL BIT(3) /* PLL-derived clock */ 112 #define PRE_PLL BIT(4) /* source is before PLL mult/div */ 113 #define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */ 114 #define PSC_FORCE BIT(6) /* Force module state transtition */ 115 #define PSC_LRST BIT(8) /* Use local reset on enable/disable */ 116 117 #define CLK(dev, con, ck) \ 118 { \ 119 .dev_id = dev, \ 120 .con_id = con, \ 121 .clk = ck, \ 122 } \ 123 124 int davinci_clk_init(struct clk_lookup *clocks); 125 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, 126 unsigned int mult, unsigned int postdiv); 127 int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); 128 int davinci_set_refclk_rate(unsigned long rate); 129 int davinci_simple_set_rate(struct clk *clk, unsigned long rate); 130 int davinci_clk_reset(struct clk *clk, bool reset); 131 void davinci_clk_enable(struct clk *clk); 132 void davinci_clk_disable(struct clk *clk); 133 134 #endif 135 136 #endif 137