1 /* 2 * Copyright (C) 2014-2015 Broadcom Corporation 3 * Copyright 2014 Linaro Limited 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation version 2. 8 * 9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 10 * kind, whether express or implied; without even the implied warranty 11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/cpumask.h> 16 #include <linux/delay.h> 17 #include <linux/errno.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/jiffies.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 #include <linux/sched.h> 24 #include <linux/sched/clock.h> 25 #include <linux/smp.h> 26 27 #include <asm/cacheflush.h> 28 #include <asm/smp.h> 29 #include <asm/smp_plat.h> 30 #include <asm/smp_scu.h> 31 32 /* Size of mapped Cortex A9 SCU address space */ 33 #define CORTEX_A9_SCU_SIZE 0x58 34 35 #define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */ 36 #define BOOT_ADDR_CPUID_MASK 0x3 37 38 /* Name of device node property defining secondary boot register location */ 39 #define OF_SECONDARY_BOOT "secondary-boot-reg" 40 #define MPIDR_CPUID_BITMASK 0x3 41 42 /* 43 * Enable the Cortex A9 Snoop Control Unit 44 * 45 * By the time this is called we already know there are multiple 46 * cores present. We assume we're running on a Cortex A9 processor, 47 * so any trouble getting the base address register or getting the 48 * SCU base is a problem. 49 * 50 * Return 0 if successful or an error code otherwise. 51 */ 52 static int __init scu_a9_enable(void) 53 { 54 unsigned long config_base; 55 void __iomem *scu_base; 56 57 if (!scu_a9_has_base()) { 58 pr_err("no configuration base address register!\n"); 59 return -ENXIO; 60 } 61 62 /* Config base address register value is zero for uniprocessor */ 63 config_base = scu_a9_get_base(); 64 if (!config_base) { 65 pr_err("hardware reports only one core\n"); 66 return -ENOENT; 67 } 68 69 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); 70 if (!scu_base) { 71 pr_err("failed to remap config base (%lu/%u) for SCU\n", 72 config_base, CORTEX_A9_SCU_SIZE); 73 return -ENOMEM; 74 } 75 76 scu_enable(scu_base); 77 78 iounmap(scu_base); /* That's the last we'll need of this */ 79 80 return 0; 81 } 82 83 static u32 secondary_boot_addr_for(unsigned int cpu) 84 { 85 u32 secondary_boot_addr = 0; 86 struct device_node *cpu_node = of_get_cpu_node(cpu, NULL); 87 88 if (!cpu_node) { 89 pr_err("Failed to find device tree node for CPU%u\n", cpu); 90 return 0; 91 } 92 93 if (of_property_read_u32(cpu_node, 94 OF_SECONDARY_BOOT, 95 &secondary_boot_addr)) 96 pr_err("required secondary boot register not specified for CPU%u\n", 97 cpu); 98 99 of_node_put(cpu_node); 100 101 return secondary_boot_addr; 102 } 103 104 static int nsp_write_lut(unsigned int cpu) 105 { 106 void __iomem *sku_rom_lut; 107 phys_addr_t secondary_startup_phy; 108 const u32 secondary_boot_addr = secondary_boot_addr_for(cpu); 109 110 if (!secondary_boot_addr) 111 return -EINVAL; 112 113 sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr, 114 sizeof(phys_addr_t)); 115 if (!sku_rom_lut) { 116 pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu); 117 return -ENOMEM; 118 } 119 120 secondary_startup_phy = __pa_symbol(secondary_startup); 121 BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX); 122 123 writel_relaxed(secondary_startup_phy, sku_rom_lut); 124 125 /* Ensure the write is visible to the secondary core */ 126 smp_wmb(); 127 128 iounmap(sku_rom_lut); 129 130 return 0; 131 } 132 133 static void __init bcm_smp_prepare_cpus(unsigned int max_cpus) 134 { 135 const cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; 136 137 /* Enable the SCU on Cortex A9 based SoCs */ 138 if (scu_a9_enable()) { 139 /* Update the CPU present map to reflect uniprocessor mode */ 140 pr_warn("failed to enable A9 SCU - disabling SMP\n"); 141 init_cpu_present(&only_cpu_0); 142 } 143 } 144 145 /* 146 * The ROM code has the secondary cores looping, waiting for an event. 147 * When an event occurs each core examines the bottom two bits of the 148 * secondary boot register. When a core finds those bits contain its 149 * own core id, it performs initialization, including computing its boot 150 * address by clearing the boot register value's bottom two bits. The 151 * core signals that it is beginning its execution by writing its boot 152 * address back to the secondary boot register, and finally jumps to 153 * that address. 154 * 155 * So to start a core executing we need to: 156 * - Encode the (hardware) CPU id with the bottom bits of the secondary 157 * start address. 158 * - Write that value into the secondary boot register. 159 * - Generate an event to wake up the secondary CPU(s). 160 * - Wait for the secondary boot register to be re-written, which 161 * indicates the secondary core has started. 162 */ 163 static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle) 164 { 165 void __iomem *boot_reg; 166 phys_addr_t boot_func; 167 u64 start_clock; 168 u32 cpu_id; 169 u32 boot_val; 170 bool timeout = false; 171 const u32 secondary_boot_addr = secondary_boot_addr_for(cpu); 172 173 cpu_id = cpu_logical_map(cpu); 174 if (cpu_id & ~BOOT_ADDR_CPUID_MASK) { 175 pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK); 176 return -EINVAL; 177 } 178 179 if (!secondary_boot_addr) 180 return -EINVAL; 181 182 boot_reg = ioremap_nocache((phys_addr_t)secondary_boot_addr, 183 sizeof(phys_addr_t)); 184 if (!boot_reg) { 185 pr_err("unable to map boot register for cpu %u\n", cpu_id); 186 return -ENOMEM; 187 } 188 189 /* 190 * Secondary cores will start in secondary_startup(), 191 * defined in "arch/arm/kernel/head.S" 192 */ 193 boot_func = __pa_symbol(secondary_startup); 194 BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK); 195 BUG_ON(boot_func > (phys_addr_t)U32_MAX); 196 197 /* The core to start is encoded in the low bits */ 198 boot_val = (u32)boot_func | cpu_id; 199 writel_relaxed(boot_val, boot_reg); 200 201 sev(); 202 203 /* The low bits will be cleared once the core has started */ 204 start_clock = local_clock(); 205 while (!timeout && readl_relaxed(boot_reg) == boot_val) 206 timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS; 207 208 iounmap(boot_reg); 209 210 if (!timeout) 211 return 0; 212 213 pr_err("timeout waiting for cpu %u to start\n", cpu_id); 214 215 return -ENXIO; 216 } 217 218 /* Cluster Dormant Control command to bring CPU into a running state */ 219 #define CDC_CMD 6 220 #define CDC_CMD_OFFSET 0 221 #define CDC_CMD_REG(cpu) (CDC_CMD_OFFSET + 4*(cpu)) 222 223 /* 224 * BCM23550 has a Cluster Dormant Control block that keeps the core in 225 * idle state. A command needs to be sent to the block to bring the CPU 226 * into running state. 227 */ 228 static int bcm23550_boot_secondary(unsigned int cpu, struct task_struct *idle) 229 { 230 void __iomem *cdc_base; 231 struct device_node *dn; 232 char *name; 233 int ret; 234 235 /* Make sure a CDC node exists before booting the 236 * secondary core. 237 */ 238 name = "brcm,bcm23550-cdc"; 239 dn = of_find_compatible_node(NULL, NULL, name); 240 if (!dn) { 241 pr_err("unable to find cdc node\n"); 242 return -ENODEV; 243 } 244 245 cdc_base = of_iomap(dn, 0); 246 of_node_put(dn); 247 248 if (!cdc_base) { 249 pr_err("unable to remap cdc base register\n"); 250 return -ENOMEM; 251 } 252 253 /* Boot the secondary core */ 254 ret = kona_boot_secondary(cpu, idle); 255 if (ret) 256 goto out; 257 258 /* Bring this CPU to RUN state so that nIRQ nFIQ 259 * signals are unblocked. 260 */ 261 writel_relaxed(CDC_CMD, cdc_base + CDC_CMD_REG(cpu)); 262 263 out: 264 iounmap(cdc_base); 265 266 return ret; 267 } 268 269 static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle) 270 { 271 int ret; 272 273 /* 274 * After wake up, secondary core branches to the startup 275 * address programmed at SKU ROM LUT location. 276 */ 277 ret = nsp_write_lut(cpu); 278 if (ret) { 279 pr_err("unable to write startup addr to SKU ROM LUT\n"); 280 goto out; 281 } 282 283 /* Send a CPU wakeup interrupt to the secondary core */ 284 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); 285 286 out: 287 return ret; 288 } 289 290 static const struct smp_operations kona_smp_ops __initconst = { 291 .smp_prepare_cpus = bcm_smp_prepare_cpus, 292 .smp_boot_secondary = kona_boot_secondary, 293 }; 294 CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", 295 &kona_smp_ops); 296 297 static const struct smp_operations bcm23550_smp_ops __initconst = { 298 .smp_boot_secondary = bcm23550_boot_secondary, 299 }; 300 CPU_METHOD_OF_DECLARE(bcm_smp_bcm23550, "brcm,bcm23550", 301 &bcm23550_smp_ops); 302 303 static const struct smp_operations nsp_smp_ops __initconst = { 304 .smp_prepare_cpus = bcm_smp_prepare_cpus, 305 .smp_boot_secondary = nsp_boot_secondary, 306 }; 307 CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops); 308