1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * arch/arm/mach-at91/pm_slow_clock.S 4 * 5 * Copyright (C) 2006 Savin Zlobec 6 * 7 * AT91SAM9 support: 8 * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee> 9 */ 10#include <linux/linkage.h> 11#include <linux/clk/at91_pmc.h> 12#include "pm.h" 13#include "pm_data-offsets.h" 14 15#define SRAMC_SELF_FRESH_ACTIVE 0x01 16#define SRAMC_SELF_FRESH_EXIT 0x00 17 18pmc .req r0 19tmp1 .req r4 20tmp2 .req r5 21tmp3 .req r6 22 23/* 24 * Wait until master clock is ready (after switching master clock source) 25 */ 26 .macro wait_mckrdy 271: ldr tmp1, [pmc, #AT91_PMC_SR] 28 tst tmp1, #AT91_PMC_MCKRDY 29 beq 1b 30 .endm 31 32/* 33 * Wait until master oscillator has stabilized. 34 */ 35 .macro wait_moscrdy 361: ldr tmp1, [pmc, #AT91_PMC_SR] 37 tst tmp1, #AT91_PMC_MOSCS 38 beq 1b 39 .endm 40 41/* 42 * Wait for main oscillator selection is done 43 */ 44 .macro wait_moscsels 451: ldr tmp1, [pmc, #AT91_PMC_SR] 46 tst tmp1, #AT91_PMC_MOSCSELS 47 beq 1b 48 .endm 49 50/* 51 * Put the processor to enter the idle state 52 */ 53 .macro at91_cpu_idle 54 55#if defined(CONFIG_CPU_V7) 56 mov tmp1, #AT91_PMC_PCK 57 str tmp1, [pmc, #AT91_PMC_SCDR] 58 59 dsb 60 61 wfi @ Wait For Interrupt 62#else 63 mcr p15, 0, tmp1, c7, c0, 4 64#endif 65 66 .endm 67 68 .text 69 70 .arm 71 72/* 73 * void at91_suspend_sram_fn(struct at91_pm_data*) 74 * @input param: 75 * @r0: base address of struct at91_pm_data 76 */ 77/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */ 78 .align 3 79ENTRY(at91_pm_suspend_in_sram) 80 /* Save registers on stack */ 81 stmfd sp!, {r4 - r12, lr} 82 83 /* Drain write buffer */ 84 mov tmp1, #0 85 mcr p15, 0, tmp1, c7, c10, 4 86 87 ldr tmp1, [r0, #PM_DATA_PMC] 88 str tmp1, .pmc_base 89 ldr tmp1, [r0, #PM_DATA_RAMC0] 90 str tmp1, .sramc_base 91 ldr tmp1, [r0, #PM_DATA_RAMC1] 92 str tmp1, .sramc1_base 93 ldr tmp1, [r0, #PM_DATA_MEMCTRL] 94 str tmp1, .memtype 95 ldr tmp1, [r0, #PM_DATA_MODE] 96 str tmp1, .pm_mode 97 ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] 98 str tmp1, .mckr_offset 99 ldr tmp1, [r0, #PM_DATA_PMC_VERSION] 100 str tmp1, .pmc_version 101 /* Both ldrne below are here to preload their address in the TLB */ 102 ldr tmp1, [r0, #PM_DATA_SHDWC] 103 str tmp1, .shdwc 104 cmp tmp1, #0 105 ldrne tmp2, [tmp1, #0] 106 ldr tmp1, [r0, #PM_DATA_SFRBU] 107 str tmp1, .sfrbu 108 cmp tmp1, #0 109 ldrne tmp2, [tmp1, #0x10] 110 111 /* Active the self-refresh mode */ 112 mov r0, #SRAMC_SELF_FRESH_ACTIVE 113 bl at91_sramc_self_refresh 114 115 ldr r0, .pm_mode 116 cmp r0, #AT91_PM_STANDBY 117 beq standby 118 cmp r0, #AT91_PM_BACKUP 119 beq backup_mode 120 121 bl at91_ulp_mode 122 b exit_suspend 123 124standby: 125 /* Wait for interrupt */ 126 ldr pmc, .pmc_base 127 at91_cpu_idle 128 b exit_suspend 129 130backup_mode: 131 bl at91_backup_mode 132 b exit_suspend 133 134exit_suspend: 135 /* Exit the self-refresh mode */ 136 mov r0, #SRAMC_SELF_FRESH_EXIT 137 bl at91_sramc_self_refresh 138 139 /* Restore registers, and return */ 140 ldmfd sp!, {r4 - r12, pc} 141ENDPROC(at91_pm_suspend_in_sram) 142 143ENTRY(at91_backup_mode) 144 /* Switch the master clock source to slow clock. */ 145 ldr pmc, .pmc_base 146 ldr tmp2, .mckr_offset 147 ldr tmp1, [pmc, tmp2] 148 bic tmp1, tmp1, #AT91_PMC_CSS 149 str tmp1, [pmc, tmp2] 150 151 wait_mckrdy 152 153 /*BUMEN*/ 154 ldr r0, .sfrbu 155 mov tmp1, #0x1 156 str tmp1, [r0, #0x10] 157 158 /* Shutdown */ 159 ldr r0, .shdwc 160 mov tmp1, #0xA5000000 161 add tmp1, tmp1, #0x1 162 str tmp1, [r0, #0] 163ENDPROC(at91_backup_mode) 164 165.macro at91_pm_ulp0_mode 166 ldr pmc, .pmc_base 167 168 /* Turn off the crystal oscillator */ 169 ldr tmp1, [pmc, #AT91_CKGR_MOR] 170 bic tmp1, tmp1, #AT91_PMC_MOSCEN 171 orr tmp1, tmp1, #AT91_PMC_KEY 172 str tmp1, [pmc, #AT91_CKGR_MOR] 173 174 /* Save RC oscillator state */ 175 ldr tmp1, [pmc, #AT91_PMC_SR] 176 str tmp1, .saved_osc_status 177 tst tmp1, #AT91_PMC_MOSCRCS 178 bne 1f 179 180 /* Turn off RC oscillator */ 181 ldr tmp1, [pmc, #AT91_CKGR_MOR] 182 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN 183 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 184 orr tmp1, tmp1, #AT91_PMC_KEY 185 str tmp1, [pmc, #AT91_CKGR_MOR] 186 187 /* Wait main RC disabled done */ 1882: ldr tmp1, [pmc, #AT91_PMC_SR] 189 tst tmp1, #AT91_PMC_MOSCRCS 190 bne 2b 191 192 /* Wait for interrupt */ 1931: at91_cpu_idle 194 195 /* Restore RC oscillator state */ 196 ldr tmp1, .saved_osc_status 197 tst tmp1, #AT91_PMC_MOSCRCS 198 beq 4f 199 200 /* Turn on RC oscillator */ 201 ldr tmp1, [pmc, #AT91_CKGR_MOR] 202 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN 203 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 204 orr tmp1, tmp1, #AT91_PMC_KEY 205 str tmp1, [pmc, #AT91_CKGR_MOR] 206 207 /* Wait main RC stabilization */ 2083: ldr tmp1, [pmc, #AT91_PMC_SR] 209 tst tmp1, #AT91_PMC_MOSCRCS 210 beq 3b 211 212 /* Turn on the crystal oscillator */ 2134: ldr tmp1, [pmc, #AT91_CKGR_MOR] 214 orr tmp1, tmp1, #AT91_PMC_MOSCEN 215 orr tmp1, tmp1, #AT91_PMC_KEY 216 str tmp1, [pmc, #AT91_CKGR_MOR] 217 218 wait_moscrdy 219.endm 220 221/** 222 * Note: This procedure only applies on the platform which uses 223 * the external crystal oscillator as a main clock source. 224 */ 225.macro at91_pm_ulp1_mode 226 ldr pmc, .pmc_base 227 ldr tmp2, .mckr_offset 228 229 /* Save RC oscillator state and check if it is enabled. */ 230 ldr tmp1, [pmc, #AT91_PMC_SR] 231 str tmp1, .saved_osc_status 232 tst tmp1, #AT91_PMC_MOSCRCS 233 bne 2f 234 235 /* Enable RC oscillator */ 236 ldr tmp1, [pmc, #AT91_CKGR_MOR] 237 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN 238 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 239 orr tmp1, tmp1, #AT91_PMC_KEY 240 str tmp1, [pmc, #AT91_CKGR_MOR] 241 242 /* Wait main RC stabilization */ 2431: ldr tmp1, [pmc, #AT91_PMC_SR] 244 tst tmp1, #AT91_PMC_MOSCRCS 245 beq 1b 246 247 /* Switch the main clock source to 12-MHz RC oscillator */ 2482: ldr tmp1, [pmc, #AT91_CKGR_MOR] 249 bic tmp1, tmp1, #AT91_PMC_MOSCSEL 250 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 251 orr tmp1, tmp1, #AT91_PMC_KEY 252 str tmp1, [pmc, #AT91_CKGR_MOR] 253 254 wait_moscsels 255 256 /* Disable the crystal oscillator */ 257 ldr tmp1, [pmc, #AT91_CKGR_MOR] 258 bic tmp1, tmp1, #AT91_PMC_MOSCEN 259 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 260 orr tmp1, tmp1, #AT91_PMC_KEY 261 str tmp1, [pmc, #AT91_CKGR_MOR] 262 263 /* Switch the master clock source to main clock */ 264 ldr tmp1, [pmc, tmp2] 265 bic tmp1, tmp1, #AT91_PMC_CSS 266 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN 267 str tmp1, [pmc, tmp2] 268 269 wait_mckrdy 270 271 /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */ 272 ldr tmp1, [pmc, #AT91_CKGR_MOR] 273 orr tmp1, tmp1, #AT91_PMC_WAITMODE 274 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 275 orr tmp1, tmp1, #AT91_PMC_KEY 276 str tmp1, [pmc, #AT91_CKGR_MOR] 277 278 /* Quirk for SAM9X60's PMC */ 279 nop 280 nop 281 282 wait_mckrdy 283 284 /* Enable the crystal oscillator */ 285 ldr tmp1, [pmc, #AT91_CKGR_MOR] 286 orr tmp1, tmp1, #AT91_PMC_MOSCEN 287 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 288 orr tmp1, tmp1, #AT91_PMC_KEY 289 str tmp1, [pmc, #AT91_CKGR_MOR] 290 291 wait_moscrdy 292 293 /* Switch the master clock source to slow clock */ 294 ldr tmp1, [pmc, tmp2] 295 bic tmp1, tmp1, #AT91_PMC_CSS 296 str tmp1, [pmc, tmp2] 297 298 wait_mckrdy 299 300 /* Switch main clock source to crystal oscillator */ 301 ldr tmp1, [pmc, #AT91_CKGR_MOR] 302 orr tmp1, tmp1, #AT91_PMC_MOSCSEL 303 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 304 orr tmp1, tmp1, #AT91_PMC_KEY 305 str tmp1, [pmc, #AT91_CKGR_MOR] 306 307 wait_moscsels 308 309 /* Switch the master clock source to main clock */ 310 ldr tmp1, [pmc, tmp2] 311 bic tmp1, tmp1, #AT91_PMC_CSS 312 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN 313 str tmp1, [pmc, tmp2] 314 315 wait_mckrdy 316 317 /* Restore RC oscillator state */ 318 ldr tmp1, .saved_osc_status 319 tst tmp1, #AT91_PMC_MOSCRCS 320 bne 3f 321 322 /* Disable RC oscillator */ 323 ldr tmp1, [pmc, #AT91_CKGR_MOR] 324 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN 325 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 326 orr tmp1, tmp1, #AT91_PMC_KEY 327 str tmp1, [pmc, #AT91_CKGR_MOR] 328 329 /* Wait RC oscillator disable done */ 3304: ldr tmp1, [pmc, #AT91_PMC_SR] 331 tst tmp1, #AT91_PMC_MOSCRCS 332 bne 4b 333 3343: 335.endm 336 337.macro at91_plla_disable 338 /* Save PLLA setting and disable it */ 339 ldr tmp1, .pmc_version 340 cmp tmp1, #AT91_PMC_V1 341 beq 1f 342 343#ifdef CONFIG_SOC_SAM9X60 344 /* Save PLLA settings. */ 345 ldr tmp2, [pmc, #AT91_PMC_PLL_UPDT] 346 bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID 347 str tmp2, [pmc, #AT91_PMC_PLL_UPDT] 348 349 /* save div. */ 350 mov tmp1, #0 351 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0] 352 bic tmp2, tmp2, #0xffffff00 353 orr tmp1, tmp1, tmp2 354 355 /* save mul. */ 356 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL1] 357 bic tmp2, tmp2, #0xffffff 358 orr tmp1, tmp1, tmp2 359 str tmp1, .saved_pllar 360 361 /* step 2. */ 362 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 363 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 364 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 365 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 366 367 /* step 3. */ 368 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 369 bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK 370 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL 371 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 372 373 /* step 4. */ 374 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 375 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 376 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 377 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 378 379 /* step 5. */ 380 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 381 bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL 382 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 383 384 /* step 7. */ 385 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 386 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 387 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 388 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 389 390 b 2f 391#endif 392 3931: /* Save PLLA setting and disable it */ 394 ldr tmp1, [pmc, #AT91_CKGR_PLLAR] 395 str tmp1, .saved_pllar 396 397 /* Disable PLLA. */ 398 mov tmp1, #AT91_PMC_PLLCOUNT 399 orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */ 400 str tmp1, [pmc, #AT91_CKGR_PLLAR] 4012: 402.endm 403 404.macro at91_plla_enable 405 ldr tmp2, .saved_pllar 406 ldr tmp3, .pmc_version 407 cmp tmp3, #AT91_PMC_V1 408 beq 4f 409 410#ifdef CONFIG_SOC_SAM9X60 411 /* step 1. */ 412 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 413 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 414 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 415 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 416 417 /* step 2. */ 418 ldr tmp1, =#AT91_PMC_PLL_ACR_DEFAULT_PLLA 419 str tmp1, [pmc, #AT91_PMC_PLL_ACR] 420 421 /* step 3. */ 422 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL1] 423 mov tmp3, tmp2 424 bic tmp3, tmp3, #0xffffff 425 orr tmp1, tmp1, tmp3 426 str tmp1, [pmc, #AT91_PMC_PLL_CTRL1] 427 428 /* step 8. */ 429 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 430 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 431 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 432 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 433 434 /* step 9. */ 435 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 436 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENLOCK 437 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL 438 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK 439 bic tmp1, tmp1, #0xff 440 mov tmp3, tmp2 441 bic tmp3, tmp3, #0xffffff00 442 orr tmp1, tmp1, tmp3 443 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 444 445 /* step 10. */ 446 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 447 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 448 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 449 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 450 451 /* step 11. */ 4523: ldr tmp1, [pmc, #AT91_PMC_PLL_ISR0] 453 tst tmp1, #0x1 454 beq 3b 455 b 2f 456#endif 457 458 /* Restore PLLA setting */ 4594: str tmp2, [pmc, #AT91_CKGR_PLLAR] 460 461 /* Enable PLLA. */ 462 tst tmp2, #(AT91_PMC_MUL & 0xff0000) 463 bne 1f 464 tst tmp2, #(AT91_PMC_MUL & ~0xff0000) 465 beq 2f 466 4671: ldr tmp1, [pmc, #AT91_PMC_SR] 468 tst tmp1, #AT91_PMC_LOCKA 469 beq 1b 4702: 471.endm 472 473ENTRY(at91_ulp_mode) 474 ldr pmc, .pmc_base 475 ldr tmp2, .mckr_offset 476 477 /* Save Master clock setting */ 478 ldr tmp1, [pmc, tmp2] 479 str tmp1, .saved_mckr 480 481 /* 482 * Set the Master clock source to slow clock 483 */ 484 bic tmp1, tmp1, #AT91_PMC_CSS 485 str tmp1, [pmc, tmp2] 486 487 wait_mckrdy 488 489 at91_plla_disable 490 491 ldr r0, .pm_mode 492 cmp r0, #AT91_PM_ULP1 493 beq ulp1_mode 494 495 at91_pm_ulp0_mode 496 b ulp_exit 497 498ulp1_mode: 499 at91_pm_ulp1_mode 500 b ulp_exit 501 502ulp_exit: 503 ldr pmc, .pmc_base 504 505 at91_plla_enable 506 507 /* 508 * Restore master clock setting 509 */ 510 ldr tmp1, .mckr_offset 511 ldr tmp2, .saved_mckr 512 str tmp2, [pmc, tmp1] 513 514 wait_mckrdy 515 516 mov pc, lr 517ENDPROC(at91_ulp_mode) 518 519/* 520 * void at91_sramc_self_refresh(unsigned int is_active) 521 * 522 * @input param: 523 * @r0: 1 - active self-refresh mode 524 * 0 - exit self-refresh mode 525 * register usage: 526 * @r1: memory type 527 * @r2: base address of the sram controller 528 */ 529 530ENTRY(at91_sramc_self_refresh) 531 ldr r1, .memtype 532 ldr r2, .sramc_base 533 534 cmp r1, #AT91_MEMCTRL_MC 535 bne ddrc_sf 536 537 /* 538 * at91rm9200 Memory controller 539 */ 540 541 /* 542 * For exiting the self-refresh mode, do nothing, 543 * automatically exit the self-refresh mode. 544 */ 545 tst r0, #SRAMC_SELF_FRESH_ACTIVE 546 beq exit_sramc_sf 547 548 /* Active SDRAM self-refresh mode */ 549 mov r3, #1 550 str r3, [r2, #AT91_MC_SDRAMC_SRR] 551 b exit_sramc_sf 552 553ddrc_sf: 554 cmp r1, #AT91_MEMCTRL_DDRSDR 555 bne sdramc_sf 556 557 /* 558 * DDR Memory controller 559 */ 560 tst r0, #SRAMC_SELF_FRESH_ACTIVE 561 beq ddrc_exit_sf 562 563 /* LPDDR1 --> force DDR2 mode during self-refresh */ 564 ldr r3, [r2, #AT91_DDRSDRC_MDR] 565 str r3, .saved_sam9_mdr 566 bic r3, r3, #~AT91_DDRSDRC_MD 567 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR 568 ldreq r3, [r2, #AT91_DDRSDRC_MDR] 569 biceq r3, r3, #AT91_DDRSDRC_MD 570 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 571 streq r3, [r2, #AT91_DDRSDRC_MDR] 572 573 /* Active DDRC self-refresh mode */ 574 ldr r3, [r2, #AT91_DDRSDRC_LPR] 575 str r3, .saved_sam9_lpr 576 bic r3, r3, #AT91_DDRSDRC_LPCB 577 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH 578 str r3, [r2, #AT91_DDRSDRC_LPR] 579 580 /* If using the 2nd ddr controller */ 581 ldr r2, .sramc1_base 582 cmp r2, #0 583 beq no_2nd_ddrc 584 585 ldr r3, [r2, #AT91_DDRSDRC_MDR] 586 str r3, .saved_sam9_mdr1 587 bic r3, r3, #~AT91_DDRSDRC_MD 588 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR 589 ldreq r3, [r2, #AT91_DDRSDRC_MDR] 590 biceq r3, r3, #AT91_DDRSDRC_MD 591 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 592 streq r3, [r2, #AT91_DDRSDRC_MDR] 593 594 /* Active DDRC self-refresh mode */ 595 ldr r3, [r2, #AT91_DDRSDRC_LPR] 596 str r3, .saved_sam9_lpr1 597 bic r3, r3, #AT91_DDRSDRC_LPCB 598 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH 599 str r3, [r2, #AT91_DDRSDRC_LPR] 600 601no_2nd_ddrc: 602 b exit_sramc_sf 603 604ddrc_exit_sf: 605 /* Restore MDR in case of LPDDR1 */ 606 ldr r3, .saved_sam9_mdr 607 str r3, [r2, #AT91_DDRSDRC_MDR] 608 /* Restore LPR on AT91 with DDRAM */ 609 ldr r3, .saved_sam9_lpr 610 str r3, [r2, #AT91_DDRSDRC_LPR] 611 612 /* If using the 2nd ddr controller */ 613 ldr r2, .sramc1_base 614 cmp r2, #0 615 ldrne r3, .saved_sam9_mdr1 616 strne r3, [r2, #AT91_DDRSDRC_MDR] 617 ldrne r3, .saved_sam9_lpr1 618 strne r3, [r2, #AT91_DDRSDRC_LPR] 619 620 b exit_sramc_sf 621 622 /* 623 * SDRAMC Memory controller 624 */ 625sdramc_sf: 626 tst r0, #SRAMC_SELF_FRESH_ACTIVE 627 beq sdramc_exit_sf 628 629 /* Active SDRAMC self-refresh mode */ 630 ldr r3, [r2, #AT91_SDRAMC_LPR] 631 str r3, .saved_sam9_lpr 632 bic r3, r3, #AT91_SDRAMC_LPCB 633 orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH 634 str r3, [r2, #AT91_SDRAMC_LPR] 635 636sdramc_exit_sf: 637 ldr r3, .saved_sam9_lpr 638 str r3, [r2, #AT91_SDRAMC_LPR] 639 640exit_sramc_sf: 641 mov pc, lr 642ENDPROC(at91_sramc_self_refresh) 643 644.pmc_base: 645 .word 0 646.sramc_base: 647 .word 0 648.sramc1_base: 649 .word 0 650.shdwc: 651 .word 0 652.sfrbu: 653 .word 0 654.memtype: 655 .word 0 656.pm_mode: 657 .word 0 658.mckr_offset: 659 .word 0 660.pmc_version: 661 .word 0 662.saved_mckr: 663 .word 0 664.saved_pllar: 665 .word 0 666.saved_sam9_lpr: 667 .word 0 668.saved_sam9_lpr1: 669 .word 0 670.saved_sam9_mdr: 671 .word 0 672.saved_sam9_mdr1: 673 .word 0 674.saved_osc_status: 675 .word 0 676 677ENTRY(at91_pm_suspend_in_sram_sz) 678 .word .-at91_pm_suspend_in_sram 679