1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * arch/arm/mach-at91/pm_slow_clock.S 4 * 5 * Copyright (C) 2006 Savin Zlobec 6 * 7 * AT91SAM9 support: 8 * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee> 9 */ 10#include <linux/linkage.h> 11#include <linux/clk/at91_pmc.h> 12#include "pm.h" 13#include "pm_data-offsets.h" 14 15#ifdef CONFIG_CPU_V7 16.arch armv7-a 17#endif 18 19#define SRAMC_SELF_FRESH_ACTIVE 0x01 20#define SRAMC_SELF_FRESH_EXIT 0x00 21 22pmc .req r0 23tmp1 .req r4 24tmp2 .req r5 25tmp3 .req r6 26 27/* 28 * Wait until master clock is ready (after switching master clock source) 29 * 30 * @r_mckid: register holding master clock identifier 31 * 32 * Side effects: overwrites r7, r8 33 */ 34 .macro wait_mckrdy r_mckid 35#ifdef CONFIG_SOC_SAMA7 36 cmp \r_mckid, #0 37 beq 1f 38 mov r7, #AT91_PMC_MCKXRDY 39 b 2f 40#endif 411: mov r7, #AT91_PMC_MCKRDY 422: ldr r8, [pmc, #AT91_PMC_SR] 43 and r8, r7 44 cmp r8, r7 45 bne 2b 46 .endm 47 48/* 49 * Wait until master oscillator has stabilized. 50 * 51 * Side effects: overwrites r7 52 */ 53 .macro wait_moscrdy 541: ldr r7, [pmc, #AT91_PMC_SR] 55 tst r7, #AT91_PMC_MOSCS 56 beq 1b 57 .endm 58 59/* 60 * Wait for main oscillator selection is done 61 * 62 * Side effects: overwrites r7 63 */ 64 .macro wait_moscsels 651: ldr r7, [pmc, #AT91_PMC_SR] 66 tst r7, #AT91_PMC_MOSCSELS 67 beq 1b 68 .endm 69 70/* 71 * Put the processor to enter the idle state 72 * 73 * Side effects: overwrites r7 74 */ 75 .macro at91_cpu_idle 76 77#if defined(CONFIG_CPU_V7) 78 mov r7, #AT91_PMC_PCK 79 str r7, [pmc, #AT91_PMC_SCDR] 80 81 dsb 82 83 wfi @ Wait For Interrupt 84#else 85 mcr p15, 0, tmp1, c7, c0, 4 86#endif 87 88 .endm 89 90/** 91 * Set state for 2.5V low power regulator 92 * @ena: 0 - disable regulator 93 * 1 - enable regulator 94 * 95 * Side effects: overwrites r7, r8, r9, r10 96 */ 97 .macro at91_2_5V_reg_set_low_power ena 98#ifdef CONFIG_SOC_SAMA7 99 ldr r7, .sfrbu 100 mov r8, #\ena 101 ldr r9, [r7, #AT91_SFRBU_25LDOCR] 102 orr r9, r9, #AT91_SFRBU_25LDOCR_LP 103 cmp r8, #1 104 beq lp_done_\ena 105 bic r9, r9, #AT91_SFRBU_25LDOCR_LP 106lp_done_\ena: 107 ldr r10, =AT91_SFRBU_25LDOCR_LDOANAKEY 108 orr r9, r9, r10 109 str r9, [r7, #AT91_SFRBU_25LDOCR] 110#endif 111 .endm 112 113 .macro at91_backup_set_lpm reg 114#ifdef CONFIG_SOC_SAMA7 115 orr \reg, \reg, #0x200000 116#endif 117 .endm 118 119 .text 120 121 .arm 122 123#ifdef CONFIG_SOC_SAMA7 124/** 125 * Enable self-refresh 126 * 127 * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3, r7 128 */ 129.macro at91_sramc_self_refresh_ena 130 ldr r2, .sramc_base 131 ldr r3, .sramc_phy_base 132 ldr r7, .pm_mode 133 134 dsb 135 136 /* Disable all AXI ports. */ 137 ldr tmp1, [r2, #UDDRC_PCTRL_0] 138 bic tmp1, tmp1, #0x1 139 str tmp1, [r2, #UDDRC_PCTRL_0] 140 141 ldr tmp1, [r2, #UDDRC_PCTRL_1] 142 bic tmp1, tmp1, #0x1 143 str tmp1, [r2, #UDDRC_PCTRL_1] 144 145 ldr tmp1, [r2, #UDDRC_PCTRL_2] 146 bic tmp1, tmp1, #0x1 147 str tmp1, [r2, #UDDRC_PCTRL_2] 148 149 ldr tmp1, [r2, #UDDRC_PCTRL_3] 150 bic tmp1, tmp1, #0x1 151 str tmp1, [r2, #UDDRC_PCTRL_3] 152 153 ldr tmp1, [r2, #UDDRC_PCTRL_4] 154 bic tmp1, tmp1, #0x1 155 str tmp1, [r2, #UDDRC_PCTRL_4] 156 157sr_ena_1: 158 /* Wait for all ports to disable. */ 159 ldr tmp1, [r2, #UDDRC_PSTAT] 160 ldr tmp2, =UDDRC_PSTAT_ALL_PORTS 161 tst tmp1, tmp2 162 bne sr_ena_1 163 164 /* Switch to self-refresh. */ 165 ldr tmp1, [r2, #UDDRC_PWRCTL] 166 orr tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW 167 str tmp1, [r2, #UDDRC_PWRCTL] 168 169sr_ena_2: 170 /* Wait for self-refresh enter. */ 171 ldr tmp1, [r2, #UDDRC_STAT] 172 bic tmp1, tmp1, #~UDDRC_STAT_SELFREF_TYPE_MSK 173 cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW 174 bne sr_ena_2 175 176 /* Put DDR PHY's DLL in bypass mode for non-backup modes. */ 177 cmp r7, #AT91_PM_BACKUP 178 beq sr_ena_3 179 ldr tmp1, [r3, #DDR3PHY_PIR] 180 orr tmp1, tmp1, #DDR3PHY_PIR_DLLBYP 181 str tmp1, [r3, #DDR3PHY_PIR] 182 183sr_ena_3: 184 /* Power down DDR PHY data receivers. */ 185 ldr tmp1, [r3, #DDR3PHY_DXCCR] 186 orr tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR 187 str tmp1, [r3, #DDR3PHY_DXCCR] 188 189 /* Power down ADDR/CMD IO. */ 190 ldr tmp1, [r3, #DDR3PHY_ACIOCR] 191 orr tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD 192 orr tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0 193 orr tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0 194 str tmp1, [r3, #DDR3PHY_ACIOCR] 195 196 /* Power down ODT. */ 197 ldr tmp1, [r3, #DDR3PHY_DSGCR] 198 orr tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0 199 str tmp1, [r3, #DDR3PHY_DSGCR] 200.endm 201 202/** 203 * Disable self-refresh 204 * 205 * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3 206 */ 207.macro at91_sramc_self_refresh_dis 208 ldr r2, .sramc_base 209 ldr r3, .sramc_phy_base 210 211 /* Power up DDR PHY data receivers. */ 212 ldr tmp1, [r3, #DDR3PHY_DXCCR] 213 bic tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR 214 str tmp1, [r3, #DDR3PHY_DXCCR] 215 216 /* Power up the output of CK and CS pins. */ 217 ldr tmp1, [r3, #DDR3PHY_ACIOCR] 218 bic tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD 219 bic tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0 220 bic tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0 221 str tmp1, [r3, #DDR3PHY_ACIOCR] 222 223 /* Power up ODT. */ 224 ldr tmp1, [r3, #DDR3PHY_DSGCR] 225 bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0 226 str tmp1, [r3, #DDR3PHY_DSGCR] 227 228 /* Take DDR PHY's DLL out of bypass mode. */ 229 ldr tmp1, [r3, #DDR3PHY_PIR] 230 bic tmp1, tmp1, #DDR3PHY_PIR_DLLBYP 231 str tmp1, [r3, #DDR3PHY_PIR] 232 233 /* Enable quasi-dynamic programming. */ 234 mov tmp1, #0 235 str tmp1, [r2, #UDDRC_SWCTRL] 236 237 /* De-assert SDRAM initialization. */ 238 ldr tmp1, [r2, #UDDRC_DFIMISC] 239 bic tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN 240 str tmp1, [r2, #UDDRC_DFIMISC] 241 242 /* Quasi-dynamic programming done. */ 243 mov tmp1, #UDDRC_SWCTRL_SW_DONE 244 str tmp1, [r2, #UDDRC_SWCTRL] 245 246sr_dis_1: 247 ldr tmp1, [r2, #UDDRC_SWSTAT] 248 tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK 249 beq sr_dis_1 250 251 /* DLL soft-reset + DLL lock wait + ITM reset */ 252 mov tmp1, #(DDR3PHY_PIR_INIT | DDR3PHY_PIR_DLLSRST | \ 253 DDR3PHY_PIR_DLLLOCK | DDR3PHY_PIR_ITMSRST) 254 str tmp1, [r3, #DDR3PHY_PIR] 255 256sr_dis_4: 257 /* Wait for it. */ 258 ldr tmp1, [r3, #DDR3PHY_PGSR] 259 tst tmp1, #DDR3PHY_PGSR_IDONE 260 beq sr_dis_4 261 262 /* Enable quasi-dynamic programming. */ 263 mov tmp1, #0 264 str tmp1, [r2, #UDDRC_SWCTRL] 265 266 /* Assert PHY init complete enable signal. */ 267 ldr tmp1, [r2, #UDDRC_DFIMISC] 268 orr tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN 269 str tmp1, [r2, #UDDRC_DFIMISC] 270 271 /* Programming is done. Set sw_done. */ 272 mov tmp1, #UDDRC_SWCTRL_SW_DONE 273 str tmp1, [r2, #UDDRC_SWCTRL] 274 275sr_dis_5: 276 /* Wait for it. */ 277 ldr tmp1, [r2, #UDDRC_SWSTAT] 278 tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK 279 beq sr_dis_5 280 281 /* Trigger self-refresh exit. */ 282 ldr tmp1, [r2, #UDDRC_PWRCTL] 283 bic tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW 284 str tmp1, [r2, #UDDRC_PWRCTL] 285 286sr_dis_6: 287 /* Wait for self-refresh exit done. */ 288 ldr tmp1, [r2, #UDDRC_STAT] 289 bic tmp1, tmp1, #~UDDRC_STAT_OPMODE_MSK 290 cmp tmp1, #UDDRC_STAT_OPMODE_NORMAL 291 bne sr_dis_6 292 293 /* Enable all AXI ports. */ 294 ldr tmp1, [r2, #UDDRC_PCTRL_0] 295 orr tmp1, tmp1, #0x1 296 str tmp1, [r2, #UDDRC_PCTRL_0] 297 298 ldr tmp1, [r2, #UDDRC_PCTRL_1] 299 orr tmp1, tmp1, #0x1 300 str tmp1, [r2, #UDDRC_PCTRL_1] 301 302 ldr tmp1, [r2, #UDDRC_PCTRL_2] 303 orr tmp1, tmp1, #0x1 304 str tmp1, [r2, #UDDRC_PCTRL_2] 305 306 ldr tmp1, [r2, #UDDRC_PCTRL_3] 307 orr tmp1, tmp1, #0x1 308 str tmp1, [r2, #UDDRC_PCTRL_3] 309 310 ldr tmp1, [r2, #UDDRC_PCTRL_4] 311 orr tmp1, tmp1, #0x1 312 str tmp1, [r2, #UDDRC_PCTRL_4] 313 314 dsb 315.endm 316#else 317/** 318 * Enable self-refresh 319 * 320 * register usage: 321 * @r1: memory type 322 * @r2: base address of the sram controller 323 * @r3: temporary 324 */ 325.macro at91_sramc_self_refresh_ena 326 ldr r1, .memtype 327 ldr r2, .sramc_base 328 329 cmp r1, #AT91_MEMCTRL_MC 330 bne sr_ena_ddrc_sf 331 332 /* Active SDRAM self-refresh mode */ 333 mov r3, #1 334 str r3, [r2, #AT91_MC_SDRAMC_SRR] 335 b sr_ena_exit 336 337sr_ena_ddrc_sf: 338 cmp r1, #AT91_MEMCTRL_DDRSDR 339 bne sr_ena_sdramc_sf 340 341 /* 342 * DDR Memory controller 343 */ 344 345 /* LPDDR1 --> force DDR2 mode during self-refresh */ 346 ldr r3, [r2, #AT91_DDRSDRC_MDR] 347 str r3, .saved_sam9_mdr 348 bic r3, r3, #~AT91_DDRSDRC_MD 349 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR 350 ldreq r3, [r2, #AT91_DDRSDRC_MDR] 351 biceq r3, r3, #AT91_DDRSDRC_MD 352 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 353 streq r3, [r2, #AT91_DDRSDRC_MDR] 354 355 /* Active DDRC self-refresh mode */ 356 ldr r3, [r2, #AT91_DDRSDRC_LPR] 357 str r3, .saved_sam9_lpr 358 bic r3, r3, #AT91_DDRSDRC_LPCB 359 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH 360 str r3, [r2, #AT91_DDRSDRC_LPR] 361 362 /* If using the 2nd ddr controller */ 363 ldr r2, .sramc1_base 364 cmp r2, #0 365 beq sr_ena_no_2nd_ddrc 366 367 ldr r3, [r2, #AT91_DDRSDRC_MDR] 368 str r3, .saved_sam9_mdr1 369 bic r3, r3, #~AT91_DDRSDRC_MD 370 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR 371 ldreq r3, [r2, #AT91_DDRSDRC_MDR] 372 biceq r3, r3, #AT91_DDRSDRC_MD 373 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 374 streq r3, [r2, #AT91_DDRSDRC_MDR] 375 376 /* Active DDRC self-refresh mode */ 377 ldr r3, [r2, #AT91_DDRSDRC_LPR] 378 str r3, .saved_sam9_lpr1 379 bic r3, r3, #AT91_DDRSDRC_LPCB 380 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH 381 str r3, [r2, #AT91_DDRSDRC_LPR] 382 383sr_ena_no_2nd_ddrc: 384 b sr_ena_exit 385 386 /* 387 * SDRAMC Memory controller 388 */ 389sr_ena_sdramc_sf: 390 /* Active SDRAMC self-refresh mode */ 391 ldr r3, [r2, #AT91_SDRAMC_LPR] 392 str r3, .saved_sam9_lpr 393 bic r3, r3, #AT91_SDRAMC_LPCB 394 orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH 395 str r3, [r2, #AT91_SDRAMC_LPR] 396 397 ldr r3, .saved_sam9_lpr 398 str r3, [r2, #AT91_SDRAMC_LPR] 399 400sr_ena_exit: 401.endm 402 403/** 404 * Disable self-refresh 405 * 406 * register usage: 407 * @r1: memory type 408 * @r2: base address of the sram controller 409 * @r3: temporary 410 */ 411.macro at91_sramc_self_refresh_dis 412 ldr r1, .memtype 413 ldr r2, .sramc_base 414 415 cmp r1, #AT91_MEMCTRL_MC 416 bne sr_dis_ddrc_exit_sf 417 418 /* 419 * at91rm9200 Memory controller 420 */ 421 422 /* 423 * For exiting the self-refresh mode, do nothing, 424 * automatically exit the self-refresh mode. 425 */ 426 b sr_dis_exit 427 428sr_dis_ddrc_exit_sf: 429 cmp r1, #AT91_MEMCTRL_DDRSDR 430 bne sdramc_exit_sf 431 432 /* DDR Memory controller */ 433 434 /* Restore MDR in case of LPDDR1 */ 435 ldr r3, .saved_sam9_mdr 436 str r3, [r2, #AT91_DDRSDRC_MDR] 437 /* Restore LPR on AT91 with DDRAM */ 438 ldr r3, .saved_sam9_lpr 439 str r3, [r2, #AT91_DDRSDRC_LPR] 440 441 /* If using the 2nd ddr controller */ 442 ldr r2, .sramc1_base 443 cmp r2, #0 444 ldrne r3, .saved_sam9_mdr1 445 strne r3, [r2, #AT91_DDRSDRC_MDR] 446 ldrne r3, .saved_sam9_lpr1 447 strne r3, [r2, #AT91_DDRSDRC_LPR] 448 449 b sr_dis_exit 450 451sdramc_exit_sf: 452 /* SDRAMC Memory controller */ 453 ldr r3, .saved_sam9_lpr 454 str r3, [r2, #AT91_SDRAMC_LPR] 455 456sr_dis_exit: 457.endm 458#endif 459 460.macro at91_pm_ulp0_mode 461 ldr pmc, .pmc_base 462 ldr tmp2, .pm_mode 463 ldr tmp3, .mckr_offset 464 465 /* Check if ULP0 fast variant has been requested. */ 466 cmp tmp2, #AT91_PM_ULP0_FAST 467 bne 0f 468 469 /* Set highest prescaler for power saving */ 470 ldr tmp1, [pmc, tmp3] 471 bic tmp1, tmp1, #AT91_PMC_PRES 472 orr tmp1, tmp1, #AT91_PMC_PRES_64 473 str tmp1, [pmc, tmp3] 474 475 mov tmp3, #0 476 wait_mckrdy tmp3 477 b 1f 478 4790: 480 /* Turn off the crystal oscillator */ 481 ldr tmp1, [pmc, #AT91_CKGR_MOR] 482 bic tmp1, tmp1, #AT91_PMC_MOSCEN 483 orr tmp1, tmp1, #AT91_PMC_KEY 484 str tmp1, [pmc, #AT91_CKGR_MOR] 485 486 /* Save RC oscillator state */ 487 ldr tmp1, [pmc, #AT91_PMC_SR] 488 str tmp1, .saved_osc_status 489 tst tmp1, #AT91_PMC_MOSCRCS 490 bne 1f 491 492 /* Turn off RC oscillator */ 493 ldr tmp1, [pmc, #AT91_CKGR_MOR] 494 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN 495 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 496 orr tmp1, tmp1, #AT91_PMC_KEY 497 str tmp1, [pmc, #AT91_CKGR_MOR] 498 499 /* Wait main RC disabled done */ 5002: ldr tmp1, [pmc, #AT91_PMC_SR] 501 tst tmp1, #AT91_PMC_MOSCRCS 502 bne 2b 503 504 /* Wait for interrupt */ 5051: at91_cpu_idle 506 507 /* Check if ULP0 fast variant has been requested. */ 508 cmp tmp2, #AT91_PM_ULP0_FAST 509 bne 5f 510 511 /* Set lowest prescaler for fast resume. */ 512 ldr tmp3, .mckr_offset 513 ldr tmp1, [pmc, tmp3] 514 bic tmp1, tmp1, #AT91_PMC_PRES 515 str tmp1, [pmc, tmp3] 516 517 mov tmp3, #0 518 wait_mckrdy tmp3 519 b 6f 520 5215: /* Restore RC oscillator state */ 522 ldr tmp1, .saved_osc_status 523 tst tmp1, #AT91_PMC_MOSCRCS 524 beq 4f 525 526 /* Turn on RC oscillator */ 527 ldr tmp1, [pmc, #AT91_CKGR_MOR] 528 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN 529 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 530 orr tmp1, tmp1, #AT91_PMC_KEY 531 str tmp1, [pmc, #AT91_CKGR_MOR] 532 533 /* Wait main RC stabilization */ 5343: ldr tmp1, [pmc, #AT91_PMC_SR] 535 tst tmp1, #AT91_PMC_MOSCRCS 536 beq 3b 537 538 /* Turn on the crystal oscillator */ 5394: ldr tmp1, [pmc, #AT91_CKGR_MOR] 540 orr tmp1, tmp1, #AT91_PMC_MOSCEN 541 orr tmp1, tmp1, #AT91_PMC_KEY 542 str tmp1, [pmc, #AT91_CKGR_MOR] 543 544 wait_moscrdy 5456: 546.endm 547 548/** 549 * Note: This procedure only applies on the platform which uses 550 * the external crystal oscillator as a main clock source. 551 */ 552.macro at91_pm_ulp1_mode 553 ldr pmc, .pmc_base 554 ldr tmp2, .mckr_offset 555 mov tmp3, #0 556 557 /* Save RC oscillator state and check if it is enabled. */ 558 ldr tmp1, [pmc, #AT91_PMC_SR] 559 str tmp1, .saved_osc_status 560 tst tmp1, #AT91_PMC_MOSCRCS 561 bne 2f 562 563 /* Enable RC oscillator */ 564 ldr tmp1, [pmc, #AT91_CKGR_MOR] 565 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN 566 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 567 orr tmp1, tmp1, #AT91_PMC_KEY 568 str tmp1, [pmc, #AT91_CKGR_MOR] 569 570 /* Wait main RC stabilization */ 5711: ldr tmp1, [pmc, #AT91_PMC_SR] 572 tst tmp1, #AT91_PMC_MOSCRCS 573 beq 1b 574 575 /* Switch the main clock source to 12-MHz RC oscillator */ 5762: ldr tmp1, [pmc, #AT91_CKGR_MOR] 577 bic tmp1, tmp1, #AT91_PMC_MOSCSEL 578 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 579 orr tmp1, tmp1, #AT91_PMC_KEY 580 str tmp1, [pmc, #AT91_CKGR_MOR] 581 582 wait_moscsels 583 584 /* Disable the crystal oscillator */ 585 ldr tmp1, [pmc, #AT91_CKGR_MOR] 586 bic tmp1, tmp1, #AT91_PMC_MOSCEN 587 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 588 orr tmp1, tmp1, #AT91_PMC_KEY 589 str tmp1, [pmc, #AT91_CKGR_MOR] 590 591 /* Switch the master clock source to main clock */ 592 ldr tmp1, [pmc, tmp2] 593 bic tmp1, tmp1, #AT91_PMC_CSS 594 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN 595 str tmp1, [pmc, tmp2] 596 597 wait_mckrdy tmp3 598 599 /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */ 600 ldr tmp1, [pmc, #AT91_CKGR_MOR] 601 orr tmp1, tmp1, #AT91_PMC_WAITMODE 602 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 603 orr tmp1, tmp1, #AT91_PMC_KEY 604 str tmp1, [pmc, #AT91_CKGR_MOR] 605 606 /* Quirk for SAM9X60's PMC */ 607 nop 608 nop 609 610 wait_mckrdy tmp3 611 612 /* Enable the crystal oscillator */ 613 ldr tmp1, [pmc, #AT91_CKGR_MOR] 614 orr tmp1, tmp1, #AT91_PMC_MOSCEN 615 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 616 orr tmp1, tmp1, #AT91_PMC_KEY 617 str tmp1, [pmc, #AT91_CKGR_MOR] 618 619 wait_moscrdy 620 621 /* Switch the master clock source to slow clock */ 622 ldr tmp1, [pmc, tmp2] 623 bic tmp1, tmp1, #AT91_PMC_CSS 624 str tmp1, [pmc, tmp2] 625 626 wait_mckrdy tmp3 627 628 /* Switch main clock source to crystal oscillator */ 629 ldr tmp1, [pmc, #AT91_CKGR_MOR] 630 orr tmp1, tmp1, #AT91_PMC_MOSCSEL 631 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 632 orr tmp1, tmp1, #AT91_PMC_KEY 633 str tmp1, [pmc, #AT91_CKGR_MOR] 634 635 wait_moscsels 636 637 /* Switch the master clock source to main clock */ 638 ldr tmp1, [pmc, tmp2] 639 bic tmp1, tmp1, #AT91_PMC_CSS 640 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN 641 str tmp1, [pmc, tmp2] 642 643 wait_mckrdy tmp3 644 645 /* Restore RC oscillator state */ 646 ldr tmp1, .saved_osc_status 647 tst tmp1, #AT91_PMC_MOSCRCS 648 bne 3f 649 650 /* Disable RC oscillator */ 651 ldr tmp1, [pmc, #AT91_CKGR_MOR] 652 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN 653 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 654 orr tmp1, tmp1, #AT91_PMC_KEY 655 str tmp1, [pmc, #AT91_CKGR_MOR] 656 657 /* Wait RC oscillator disable done */ 6584: ldr tmp1, [pmc, #AT91_PMC_SR] 659 tst tmp1, #AT91_PMC_MOSCRCS 660 bne 4b 661 6623: 663.endm 664 665.macro at91_plla_disable 666 /* Save PLLA setting and disable it */ 667 ldr tmp1, .pmc_version 668 cmp tmp1, #AT91_PMC_V1 669 beq 1f 670 671#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL 672 /* Save PLLA settings. */ 673 ldr tmp2, [pmc, #AT91_PMC_PLL_UPDT] 674 bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID 675 str tmp2, [pmc, #AT91_PMC_PLL_UPDT] 676 677 /* save div. */ 678 mov tmp1, #0 679 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0] 680 bic tmp2, tmp2, #0xffffff00 681 orr tmp1, tmp1, tmp2 682 683 /* save mul. */ 684 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL1] 685 bic tmp2, tmp2, #0xffffff 686 orr tmp1, tmp1, tmp2 687 str tmp1, .saved_pllar 688 689 /* step 2. */ 690 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 691 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 692 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 693 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 694 695 /* step 3. */ 696 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 697 bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK 698 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL 699 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 700 701 /* step 4. */ 702 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 703 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 704 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 705 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 706 707 /* step 5. */ 708 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 709 bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL 710 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 711 712 /* step 7. */ 713 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 714 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 715 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 716 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 717 718 b 2f 719#endif 720 7211: /* Save PLLA setting and disable it */ 722 ldr tmp1, [pmc, #AT91_CKGR_PLLAR] 723 str tmp1, .saved_pllar 724 725 /* Disable PLLA. */ 726 mov tmp1, #AT91_PMC_PLLCOUNT 727 orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */ 728 str tmp1, [pmc, #AT91_CKGR_PLLAR] 7292: 730.endm 731 732.macro at91_plla_enable 733 ldr tmp2, .saved_pllar 734 ldr tmp3, .pmc_version 735 cmp tmp3, #AT91_PMC_V1 736 beq 4f 737 738#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL 739 /* step 1. */ 740 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 741 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 742 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 743 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 744 745 /* step 2. */ 746 ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA 747 str tmp1, [pmc, #AT91_PMC_PLL_ACR] 748 749 /* step 3. */ 750 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL1] 751 mov tmp3, tmp2 752 bic tmp3, tmp3, #0xffffff 753 orr tmp1, tmp1, tmp3 754 str tmp1, [pmc, #AT91_PMC_PLL_CTRL1] 755 756 /* step 8. */ 757 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 758 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 759 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 760 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 761 762 /* step 9. */ 763 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 764 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENLOCK 765 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL 766 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK 767 bic tmp1, tmp1, #0xff 768 mov tmp3, tmp2 769 bic tmp3, tmp3, #0xffffff00 770 orr tmp1, tmp1, tmp3 771 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 772 773 /* step 10. */ 774 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 775 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 776 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 777 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 778 779 /* step 11. */ 7803: ldr tmp1, [pmc, #AT91_PMC_PLL_ISR0] 781 tst tmp1, #0x1 782 beq 3b 783 b 2f 784#endif 785 786 /* Restore PLLA setting */ 7874: str tmp2, [pmc, #AT91_CKGR_PLLAR] 788 789 /* Enable PLLA. */ 790 tst tmp2, #(AT91_PMC_MUL & 0xff0000) 791 bne 1f 792 tst tmp2, #(AT91_PMC_MUL & ~0xff0000) 793 beq 2f 794 7951: ldr tmp1, [pmc, #AT91_PMC_SR] 796 tst tmp1, #AT91_PMC_LOCKA 797 beq 1b 7982: 799.endm 800 801/** 802 * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock 803 * 804 * Side effects: overwrites tmp1, tmp2 805 */ 806.macro at91_mckx_ps_enable 807#ifdef CONFIG_SOC_SAMA7 808 ldr pmc, .pmc_base 809 810 /* There are 4 MCKs we need to handle: MCK1..4 */ 811 mov tmp1, #1 812e_loop: cmp tmp1, #5 813 beq e_done 814 815 /* Write MCK ID to retrieve the settings. */ 816 str tmp1, [pmc, #AT91_PMC_MCR_V2] 817 ldr tmp2, [pmc, #AT91_PMC_MCR_V2] 818 819e_save_mck1: 820 cmp tmp1, #1 821 bne e_save_mck2 822 str tmp2, .saved_mck1 823 b e_ps 824 825e_save_mck2: 826 cmp tmp1, #2 827 bne e_save_mck3 828 str tmp2, .saved_mck2 829 b e_ps 830 831e_save_mck3: 832 cmp tmp1, #3 833 bne e_save_mck4 834 str tmp2, .saved_mck3 835 b e_ps 836 837e_save_mck4: 838 str tmp2, .saved_mck4 839 840e_ps: 841 /* Use CSS=MAINCK and DIV=1. */ 842 bic tmp2, tmp2, #AT91_PMC_MCR_V2_CSS 843 bic tmp2, tmp2, #AT91_PMC_MCR_V2_DIV 844 orr tmp2, tmp2, #AT91_PMC_MCR_V2_CSS_MAINCK 845 orr tmp2, tmp2, #AT91_PMC_MCR_V2_DIV1 846 str tmp2, [pmc, #AT91_PMC_MCR_V2] 847 848 wait_mckrdy tmp1 849 850 add tmp1, tmp1, #1 851 b e_loop 852 853e_done: 854#endif 855.endm 856 857/** 858 * at91_mckx_ps_restore: restore MCK1..4 settings 859 * 860 * Side effects: overwrites tmp1, tmp2 861 */ 862.macro at91_mckx_ps_restore 863#ifdef CONFIG_SOC_SAMA7 864 ldr pmc, .pmc_base 865 866 /* There are 4 MCKs we need to handle: MCK1..4 */ 867 mov tmp1, #1 868r_loop: cmp tmp1, #5 869 beq r_done 870 871r_save_mck1: 872 cmp tmp1, #1 873 bne r_save_mck2 874 ldr tmp2, .saved_mck1 875 b r_ps 876 877r_save_mck2: 878 cmp tmp1, #2 879 bne r_save_mck3 880 ldr tmp2, .saved_mck2 881 b r_ps 882 883r_save_mck3: 884 cmp tmp1, #3 885 bne r_save_mck4 886 ldr tmp2, .saved_mck3 887 b r_ps 888 889r_save_mck4: 890 ldr tmp2, .saved_mck4 891 892r_ps: 893 /* Write MCK ID to retrieve the settings. */ 894 str tmp1, [pmc, #AT91_PMC_MCR_V2] 895 ldr tmp3, [pmc, #AT91_PMC_MCR_V2] 896 897 /* We need to restore CSS and DIV. */ 898 bic tmp3, tmp3, #AT91_PMC_MCR_V2_CSS 899 bic tmp3, tmp3, #AT91_PMC_MCR_V2_DIV 900 orr tmp3, tmp3, tmp2 901 bic tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK 902 orr tmp3, tmp3, tmp1 903 orr tmp3, tmp3, #AT91_PMC_MCR_V2_CMD 904 str tmp2, [pmc, #AT91_PMC_MCR_V2] 905 906 wait_mckrdy tmp1 907 908 add tmp1, tmp1, #1 909 b r_loop 910r_done: 911#endif 912.endm 913 914.macro at91_ulp_mode 915 at91_mckx_ps_enable 916 917 ldr pmc, .pmc_base 918 ldr tmp2, .mckr_offset 919 ldr tmp3, .pm_mode 920 921 /* Save Master clock setting */ 922 ldr tmp1, [pmc, tmp2] 923 str tmp1, .saved_mckr 924 925 /* 926 * Set master clock source to: 927 * - MAINCK if using ULP0 fast variant 928 * - slow clock, otherwise 929 */ 930 bic tmp1, tmp1, #AT91_PMC_CSS 931 cmp tmp3, #AT91_PM_ULP0_FAST 932 bne save_mck 933 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN 934save_mck: 935 str tmp1, [pmc, tmp2] 936 937 mov tmp3, #0 938 wait_mckrdy tmp3 939 940 at91_plla_disable 941 942 /* Enable low power mode for 2.5V regulator. */ 943 at91_2_5V_reg_set_low_power 1 944 945 ldr tmp3, .pm_mode 946 cmp tmp3, #AT91_PM_ULP1 947 beq ulp1_mode 948 949 at91_pm_ulp0_mode 950 b ulp_exit 951 952ulp1_mode: 953 at91_pm_ulp1_mode 954 b ulp_exit 955 956ulp_exit: 957 /* Disable low power mode for 2.5V regulator. */ 958 at91_2_5V_reg_set_low_power 0 959 960 ldr pmc, .pmc_base 961 962 at91_plla_enable 963 964 /* 965 * Restore master clock setting 966 */ 967 ldr tmp1, .mckr_offset 968 ldr tmp2, .saved_mckr 969 str tmp2, [pmc, tmp1] 970 971 mov tmp3, #0 972 wait_mckrdy tmp3 973 974 at91_mckx_ps_restore 975.endm 976 977.macro at91_backup_mode 978 /* Switch the master clock source to slow clock. */ 979 ldr pmc, .pmc_base 980 ldr tmp2, .mckr_offset 981 ldr tmp1, [pmc, tmp2] 982 bic tmp1, tmp1, #AT91_PMC_CSS 983 str tmp1, [pmc, tmp2] 984 985 mov tmp3, #0 986 wait_mckrdy tmp3 987 988 /*BUMEN*/ 989 ldr r0, .sfrbu 990 mov tmp1, #0x1 991 str tmp1, [r0, #0x10] 992 993 /* Wait for it. */ 9941: ldr tmp1, [r0, #0x10] 995 tst tmp1, #0x1 996 beq 1b 997 998 /* Shutdown */ 999 ldr r0, .shdwc 1000 mov tmp1, #0xA5000000 1001 add tmp1, tmp1, #0x1 1002 at91_backup_set_lpm tmp1 1003 str tmp1, [r0, #0] 1004.endm 1005 1006/* 1007 * void at91_suspend_sram_fn(struct at91_pm_data*) 1008 * @input param: 1009 * @r0: base address of struct at91_pm_data 1010 */ 1011/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */ 1012 .align 3 1013ENTRY(at91_pm_suspend_in_sram) 1014 /* Save registers on stack */ 1015 stmfd sp!, {r4 - r12, lr} 1016 1017 /* Drain write buffer */ 1018 mov tmp1, #0 1019 mcr p15, 0, tmp1, c7, c10, 4 1020 1021 /* Flush tlb. */ 1022 mov r4, #0 1023 mcr p15, 0, r4, c8, c7, 0 1024 1025 ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] 1026 str tmp1, .mckr_offset 1027 ldr tmp1, [r0, #PM_DATA_PMC_VERSION] 1028 str tmp1, .pmc_version 1029 ldr tmp1, [r0, #PM_DATA_MEMCTRL] 1030 str tmp1, .memtype 1031 ldr tmp1, [r0, #PM_DATA_MODE] 1032 str tmp1, .pm_mode 1033 1034 /* 1035 * ldrne below are here to preload their address in the TLB as access 1036 * to RAM may be limited while in self-refresh. 1037 */ 1038 ldr tmp1, [r0, #PM_DATA_PMC] 1039 str tmp1, .pmc_base 1040 cmp tmp1, #0 1041 ldrne tmp2, [tmp1, #0] 1042 1043 ldr tmp1, [r0, #PM_DATA_RAMC0] 1044 str tmp1, .sramc_base 1045 cmp tmp1, #0 1046 ldrne tmp2, [tmp1, #0] 1047 1048 ldr tmp1, [r0, #PM_DATA_RAMC1] 1049 str tmp1, .sramc1_base 1050 cmp tmp1, #0 1051 ldrne tmp2, [tmp1, #0] 1052 1053#ifndef CONFIG_SOC_SAM_V4_V5 1054 /* ldrne below are here to preload their address in the TLB */ 1055 ldr tmp1, [r0, #PM_DATA_RAMC_PHY] 1056 str tmp1, .sramc_phy_base 1057 cmp tmp1, #0 1058 ldrne tmp2, [tmp1, #0] 1059 1060 ldr tmp1, [r0, #PM_DATA_SHDWC] 1061 str tmp1, .shdwc 1062 cmp tmp1, #0 1063 ldrne tmp2, [tmp1, #0] 1064 1065 ldr tmp1, [r0, #PM_DATA_SFRBU] 1066 str tmp1, .sfrbu 1067 cmp tmp1, #0 1068 ldrne tmp2, [tmp1, #0x10] 1069#endif 1070 1071 /* Active the self-refresh mode */ 1072 at91_sramc_self_refresh_ena 1073 1074 ldr r0, .pm_mode 1075 cmp r0, #AT91_PM_STANDBY 1076 beq standby 1077 cmp r0, #AT91_PM_BACKUP 1078 beq backup_mode 1079 1080 at91_ulp_mode 1081 b exit_suspend 1082 1083standby: 1084 /* Wait for interrupt */ 1085 ldr pmc, .pmc_base 1086 at91_cpu_idle 1087 b exit_suspend 1088 1089backup_mode: 1090 at91_backup_mode 1091 1092exit_suspend: 1093 /* Exit the self-refresh mode */ 1094 at91_sramc_self_refresh_dis 1095 1096 /* Restore registers, and return */ 1097 ldmfd sp!, {r4 - r12, pc} 1098ENDPROC(at91_pm_suspend_in_sram) 1099 1100.pmc_base: 1101 .word 0 1102.sramc_base: 1103 .word 0 1104.sramc1_base: 1105 .word 0 1106.sramc_phy_base: 1107 .word 0 1108.shdwc: 1109 .word 0 1110.sfrbu: 1111 .word 0 1112.memtype: 1113 .word 0 1114.pm_mode: 1115 .word 0 1116.mckr_offset: 1117 .word 0 1118.pmc_version: 1119 .word 0 1120.saved_mckr: 1121 .word 0 1122.saved_pllar: 1123 .word 0 1124.saved_sam9_lpr: 1125 .word 0 1126.saved_sam9_lpr1: 1127 .word 0 1128.saved_sam9_mdr: 1129 .word 0 1130.saved_sam9_mdr1: 1131 .word 0 1132.saved_osc_status: 1133 .word 0 1134#ifdef CONFIG_SOC_SAMA7 1135.saved_mck1: 1136 .word 0 1137.saved_mck2: 1138 .word 0 1139.saved_mck3: 1140 .word 0 1141.saved_mck4: 1142 .word 0 1143#endif 1144 1145ENTRY(at91_pm_suspend_in_sram_sz) 1146 .word .-at91_pm_suspend_in_sram 1147