1 /* 2 * AT91 Power Management 3 * 4 * Copyright (C) 2005 David Brownell 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 #ifndef __ARCH_ARM_MACH_AT91_PM 12 #define __ARCH_ARM_MACH_AT91_PM 13 14 #include <asm/proc-fns.h> 15 16 #include <mach/at91_ramc.h> 17 #include <mach/at91rm9200_sdramc.h> 18 19 extern void at91_pm_set_standby(void (*at91_standby)(void)); 20 21 /* 22 * The AT91RM9200 goes into self-refresh mode with this command, and will 23 * terminate self-refresh automatically on the next SDRAM access. 24 * 25 * Self-refresh mode is exited as soon as a memory access is made, but we don't 26 * know for sure when that happens. However, we need to restore the low-power 27 * mode if it was enabled before going idle. Restoring low-power mode while 28 * still in self-refresh is "not recommended", but seems to work. 29 */ 30 31 static inline void at91rm9200_standby(void) 32 { 33 u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR); 34 35 asm volatile( 36 "b 1f\n\t" 37 ".align 5\n\t" 38 "1: mcr p15, 0, %0, c7, c10, 4\n\t" 39 " str %0, [%1, %2]\n\t" 40 " str %3, [%1, %4]\n\t" 41 " mcr p15, 0, %0, c7, c0, 4\n\t" 42 " str %5, [%1, %2]" 43 : 44 : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR), 45 "r" (1), "r" (AT91RM9200_SDRAMC_SRR), 46 "r" (lpr)); 47 } 48 49 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 50 * remember. 51 */ 52 static inline void at91_ddr_standby(void) 53 { 54 /* Those two values allow us to delay self-refresh activation 55 * to the maximum. */ 56 u32 lpr0, lpr1 = 0; 57 u32 saved_lpr0, saved_lpr1 = 0; 58 59 if (at91_ramc_base[1]) { 60 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); 61 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; 62 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 63 } 64 65 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 66 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 67 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 68 69 /* self-refresh mode now */ 70 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 71 if (at91_ramc_base[1]) 72 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); 73 74 cpu_do_idle(); 75 76 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 77 if (at91_ramc_base[1]) 78 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); 79 } 80 81 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 82 * remember. 83 */ 84 static inline void at91sam9_sdram_standby(void) 85 { 86 u32 lpr0, lpr1 = 0; 87 u32 saved_lpr0, saved_lpr1 = 0; 88 89 if (at91_ramc_base[1]) { 90 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); 91 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; 92 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 93 } 94 95 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); 96 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; 97 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 98 99 /* self-refresh mode now */ 100 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); 101 if (at91_ramc_base[1]) 102 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); 103 104 cpu_do_idle(); 105 106 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); 107 if (at91_ramc_base[1]) 108 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); 109 } 110 111 #endif 112