1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * arch/arm/mach-at91/pm.c 4 * AT91 Power Management 5 * 6 * Copyright (C) 2005 David Brownell 7 */ 8 9 #include <linux/genalloc.h> 10 #include <linux/io.h> 11 #include <linux/of_address.h> 12 #include <linux/of.h> 13 #include <linux/of_fdt.h> 14 #include <linux/of_platform.h> 15 #include <linux/parser.h> 16 #include <linux/suspend.h> 17 18 #include <linux/clk.h> 19 #include <linux/clk/at91_pmc.h> 20 #include <linux/platform_data/atmel.h> 21 22 #include <asm/cacheflush.h> 23 #include <asm/fncpy.h> 24 #include <asm/system_misc.h> 25 #include <asm/suspend.h> 26 27 #include "generic.h" 28 #include "pm.h" 29 #include "sam_secure.h" 30 31 #define BACKUP_DDR_PHY_CALIBRATION (9) 32 33 /** 34 * struct at91_pm_bu - AT91 power management backup unit data structure 35 * @suspended: true if suspended to backup mode 36 * @reserved: reserved 37 * @canary: canary data for memory checking after exit from backup mode 38 * @resume: resume API 39 * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words 40 * of the memory 41 */ 42 struct at91_pm_bu { 43 int suspended; 44 unsigned long reserved; 45 phys_addr_t canary; 46 phys_addr_t resume; 47 unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION]; 48 }; 49 50 /** 51 * struct at91_pm_sfrbu_regs - registers mapping for SFRBU 52 * @pswbu: power switch BU control registers 53 */ 54 struct at91_pm_sfrbu_regs { 55 struct { 56 u32 key; 57 u32 ctrl; 58 u32 state; 59 u32 softsw; 60 } pswbu; 61 }; 62 63 /** 64 * enum at91_pm_eth_clk - Ethernet clock indexes 65 * @AT91_PM_ETH_PCLK: pclk index 66 * @AT91_PM_ETH_HCLK: hclk index 67 * @AT91_PM_ETH_MAX_CLK: max index 68 */ 69 enum at91_pm_eth_clk { 70 AT91_PM_ETH_PCLK, 71 AT91_PM_ETH_HCLK, 72 AT91_PM_ETH_MAX_CLK, 73 }; 74 75 /** 76 * enum at91_pm_eth - Ethernet controller indexes 77 * @AT91_PM_G_ETH: gigabit Ethernet controller index 78 * @AT91_PM_E_ETH: megabit Ethernet controller index 79 * @AT91_PM_MAX_ETH: max index 80 */ 81 enum at91_pm_eth { 82 AT91_PM_G_ETH, 83 AT91_PM_E_ETH, 84 AT91_PM_MAX_ETH, 85 }; 86 87 /** 88 * struct at91_pm_quirk_eth - AT91 PM Ethernet quirks 89 * @dev: Ethernet device 90 * @np: Ethernet device node 91 * @clks: Ethernet clocks 92 * @modes: power management mode that this quirk applies to 93 * @dns_modes: do not suspend modes: stop suspending if Ethernet is configured 94 * as wakeup source but buggy and no other wakeup source is 95 * available 96 */ 97 struct at91_pm_quirk_eth { 98 struct device *dev; 99 struct device_node *np; 100 struct clk_bulk_data clks[AT91_PM_ETH_MAX_CLK]; 101 u32 modes; 102 u32 dns_modes; 103 }; 104 105 /** 106 * struct at91_pm_quirks - AT91 PM quirks 107 * @eth: Ethernet quirks 108 */ 109 struct at91_pm_quirks { 110 struct at91_pm_quirk_eth eth[AT91_PM_MAX_ETH]; 111 }; 112 113 /** 114 * struct at91_soc_pm - AT91 SoC power management data structure 115 * @config_shdwc_ws: wakeup sources configuration function for SHDWC 116 * @config_pmc_ws: wakeup srouces configuration function for PMC 117 * @ws_ids: wakup sources of_device_id array 118 * @bu: backup unit mapped data (for backup mode) 119 * @quirks: PM quirks 120 * @data: PM data to be used on last phase of suspend 121 * @sfrbu_regs: SFRBU registers mapping 122 * @memcs: memory chip select 123 */ 124 struct at91_soc_pm { 125 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); 126 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); 127 const struct of_device_id *ws_ids; 128 struct at91_pm_bu *bu; 129 struct at91_pm_quirks quirks; 130 struct at91_pm_data data; 131 struct at91_pm_sfrbu_regs sfrbu_regs; 132 void *memcs; 133 }; 134 135 /** 136 * enum at91_pm_iomaps - IOs that needs to be mapped for different PM modes 137 * @AT91_PM_IOMAP_SHDWC: SHDWC controller 138 * @AT91_PM_IOMAP_SFRBU: SFRBU controller 139 * @AT91_PM_IOMAP_ETHC: Ethernet controller 140 */ 141 enum at91_pm_iomaps { 142 AT91_PM_IOMAP_SHDWC, 143 AT91_PM_IOMAP_SFRBU, 144 AT91_PM_IOMAP_ETHC, 145 }; 146 147 #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name) 148 149 static struct at91_soc_pm soc_pm = { 150 .data = { 151 .standby_mode = AT91_PM_STANDBY, 152 .suspend_mode = AT91_PM_ULP0, 153 }, 154 }; 155 156 static const match_table_t pm_modes __initconst = { 157 { AT91_PM_STANDBY, "standby" }, 158 { AT91_PM_ULP0, "ulp0" }, 159 { AT91_PM_ULP0_FAST, "ulp0-fast" }, 160 { AT91_PM_ULP1, "ulp1" }, 161 { AT91_PM_BACKUP, "backup" }, 162 { -1, NULL }, 163 }; 164 165 #define at91_ramc_read(id, field) \ 166 __raw_readl(soc_pm.data.ramc[id] + field) 167 168 #define at91_ramc_write(id, field, value) \ 169 __raw_writel(value, soc_pm.data.ramc[id] + field) 170 171 static int at91_pm_valid_state(suspend_state_t state) 172 { 173 switch (state) { 174 case PM_SUSPEND_ON: 175 case PM_SUSPEND_STANDBY: 176 case PM_SUSPEND_MEM: 177 return 1; 178 179 default: 180 return 0; 181 } 182 } 183 184 static int canary = 0xA5A5A5A5; 185 186 struct wakeup_source_info { 187 unsigned int pmc_fsmr_bit; 188 unsigned int shdwc_mr_bit; 189 bool set_polarity; 190 }; 191 192 static const struct wakeup_source_info ws_info[] = { 193 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true }, 194 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) }, 195 { .pmc_fsmr_bit = AT91_PMC_USBAL }, 196 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD }, 197 { .pmc_fsmr_bit = AT91_PMC_RTTAL }, 198 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE }, 199 }; 200 201 static const struct of_device_id sama5d2_ws_ids[] = { 202 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] }, 203 { .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] }, 204 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] }, 205 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, 206 { .compatible = "usb-ohci", .data = &ws_info[2] }, 207 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 208 { .compatible = "usb-ehci", .data = &ws_info[2] }, 209 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] }, 210 { /* sentinel */ } 211 }; 212 213 static const struct of_device_id sam9x60_ws_ids[] = { 214 { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] }, 215 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, 216 { .compatible = "usb-ohci", .data = &ws_info[2] }, 217 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 218 { .compatible = "usb-ehci", .data = &ws_info[2] }, 219 { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] }, 220 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] }, 221 { /* sentinel */ } 222 }; 223 224 static const struct of_device_id sama7g5_ws_ids[] = { 225 { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] }, 226 { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] }, 227 { .compatible = "usb-ohci", .data = &ws_info[2] }, 228 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 229 { .compatible = "usb-ehci", .data = &ws_info[2] }, 230 { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] }, 231 { .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] }, 232 { /* sentinel */ } 233 }; 234 235 static int at91_pm_config_ws(unsigned int pm_mode, bool set) 236 { 237 const struct wakeup_source_info *wsi; 238 const struct of_device_id *match; 239 struct platform_device *pdev; 240 struct device_node *np; 241 unsigned int mode = 0, polarity = 0, val = 0; 242 243 if (pm_mode != AT91_PM_ULP1) 244 return 0; 245 246 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids) 247 return -EPERM; 248 249 if (!set) { 250 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR); 251 return 0; 252 } 253 254 if (soc_pm.config_shdwc_ws) 255 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity); 256 257 /* SHDWC.MR */ 258 val = readl(soc_pm.data.shdwc + 0x04); 259 260 /* Loop through defined wakeup sources. */ 261 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) { 262 pdev = of_find_device_by_node(np); 263 if (!pdev) 264 continue; 265 266 if (device_may_wakeup(&pdev->dev)) { 267 wsi = match->data; 268 269 /* Check if enabled on SHDWC. */ 270 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit)) 271 goto put_device; 272 273 mode |= wsi->pmc_fsmr_bit; 274 if (wsi->set_polarity) 275 polarity |= wsi->pmc_fsmr_bit; 276 } 277 278 put_device: 279 put_device(&pdev->dev); 280 } 281 282 if (mode) { 283 if (soc_pm.config_pmc_ws) 284 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity); 285 } else { 286 pr_err("AT91: PM: no ULP1 wakeup sources found!"); 287 } 288 289 return mode ? 0 : -EPERM; 290 } 291 292 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode, 293 u32 *polarity) 294 { 295 u32 val; 296 297 /* SHDWC.WUIR */ 298 val = readl(shdwc + 0x0c); 299 *mode |= (val & 0x3ff); 300 *polarity |= ((val >> 16) & 0x3ff); 301 302 return 0; 303 } 304 305 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity) 306 { 307 writel(mode, pmc + AT91_PMC_FSMR); 308 writel(polarity, pmc + AT91_PMC_FSPR); 309 310 return 0; 311 } 312 313 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity) 314 { 315 writel(mode, pmc + AT91_PMC_FSMR); 316 317 return 0; 318 } 319 320 static bool at91_pm_eth_quirk_is_valid(struct at91_pm_quirk_eth *eth) 321 { 322 struct platform_device *pdev; 323 324 /* Interface NA in DT. */ 325 if (!eth->np) 326 return false; 327 328 /* No quirks for this interface and current suspend mode. */ 329 if (!(eth->modes & BIT(soc_pm.data.mode))) 330 return false; 331 332 if (!eth->dev) { 333 /* Driver not probed. */ 334 pdev = of_find_device_by_node(eth->np); 335 if (!pdev) 336 return false; 337 /* put_device(eth->dev) is called at the end of suspend. */ 338 eth->dev = &pdev->dev; 339 } 340 341 /* No quirks if device isn't a wakeup source. */ 342 if (!device_may_wakeup(eth->dev)) 343 return false; 344 345 return true; 346 } 347 348 static int at91_pm_config_quirks(bool suspend) 349 { 350 struct at91_pm_quirk_eth *eth; 351 int i, j, ret, tmp; 352 353 /* 354 * Ethernet IPs who's device_node pointers are stored into 355 * soc_pm.quirks.eth[].np cannot handle WoL packets while in ULP0, ULP1 356 * or both due to a hardware bug. If they receive WoL packets while in 357 * ULP0 or ULP1 IPs could stop working or the whole system could stop 358 * working. We cannot handle this scenario in the ethernet driver itself 359 * as the driver is common to multiple vendors and also we only know 360 * here, in this file, if we suspend to ULP0 or ULP1 mode. Thus handle 361 * these scenarios here, as quirks. 362 */ 363 for (i = 0; i < AT91_PM_MAX_ETH; i++) { 364 eth = &soc_pm.quirks.eth[i]; 365 366 if (!at91_pm_eth_quirk_is_valid(eth)) 367 continue; 368 369 /* 370 * For modes in dns_modes mask the system blocks if quirk is not 371 * applied but if applied the interface doesn't act at WoL 372 * events. Thus take care to avoid suspending if this interface 373 * is the only configured wakeup source. 374 */ 375 if (suspend && eth->dns_modes & BIT(soc_pm.data.mode)) { 376 int ws_count = 0; 377 #ifdef CONFIG_PM_SLEEP 378 struct wakeup_source *ws; 379 380 for_each_wakeup_source(ws) { 381 if (ws->dev == eth->dev) 382 continue; 383 384 ws_count++; 385 break; 386 } 387 #endif 388 389 /* 390 * Checking !ws is good for all platforms with issues 391 * even when both G_ETH and E_ETH are available as dns_modes 392 * is populated only on G_ETH interface. 393 */ 394 if (!ws_count) { 395 pr_err("AT91: PM: Ethernet cannot resume from WoL!"); 396 ret = -EPERM; 397 put_device(eth->dev); 398 eth->dev = NULL; 399 /* No need to revert clock settings for this eth. */ 400 i--; 401 goto clk_unconfigure; 402 } 403 } 404 405 if (suspend) { 406 clk_bulk_disable_unprepare(AT91_PM_ETH_MAX_CLK, eth->clks); 407 } else { 408 ret = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, 409 eth->clks); 410 if (ret) 411 goto clk_unconfigure; 412 /* 413 * Release the reference to eth->dev taken in 414 * at91_pm_eth_quirk_is_valid(). 415 */ 416 put_device(eth->dev); 417 eth->dev = NULL; 418 } 419 } 420 421 return 0; 422 423 clk_unconfigure: 424 /* 425 * In case of resume we reach this point if clk_prepare_enable() failed. 426 * we don't want to revert the previous clk_prepare_enable() for the 427 * other IP. 428 */ 429 for (j = i; j >= 0; j--) { 430 eth = &soc_pm.quirks.eth[j]; 431 if (suspend) { 432 if (!at91_pm_eth_quirk_is_valid(eth)) 433 continue; 434 435 tmp = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, eth->clks); 436 if (tmp) { 437 pr_err("AT91: PM: failed to enable %s clocks\n", 438 j == AT91_PM_G_ETH ? "geth" : "eth"); 439 } 440 } 441 442 /* 443 * Release the reference to eth->dev taken in 444 * at91_pm_eth_quirk_is_valid(). 445 */ 446 put_device(eth->dev); 447 eth->dev = NULL; 448 } 449 450 return ret; 451 } 452 453 /* 454 * Called after processes are frozen, but before we shutdown devices. 455 */ 456 static int at91_pm_begin(suspend_state_t state) 457 { 458 int ret; 459 460 switch (state) { 461 case PM_SUSPEND_MEM: 462 soc_pm.data.mode = soc_pm.data.suspend_mode; 463 break; 464 465 case PM_SUSPEND_STANDBY: 466 soc_pm.data.mode = soc_pm.data.standby_mode; 467 break; 468 469 default: 470 soc_pm.data.mode = -1; 471 } 472 473 ret = at91_pm_config_ws(soc_pm.data.mode, true); 474 if (ret) 475 return ret; 476 477 if (soc_pm.data.mode == AT91_PM_BACKUP) 478 soc_pm.bu->suspended = 1; 479 else if (soc_pm.bu) 480 soc_pm.bu->suspended = 0; 481 482 return 0; 483 } 484 485 /* 486 * Verify that all the clocks are correct before entering 487 * slow-clock mode. 488 */ 489 static int at91_pm_verify_clocks(void) 490 { 491 unsigned long scsr; 492 int i; 493 494 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR); 495 496 /* USB must not be using PLLB */ 497 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) { 498 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 499 return 0; 500 } 501 502 /* PCK0..PCK3 must be disabled, or configured to use clk32k */ 503 for (i = 0; i < 4; i++) { 504 u32 css; 505 506 if ((scsr & (AT91_PMC_PCK0 << i)) == 0) 507 continue; 508 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; 509 if (css != AT91_PMC_CSS_SLOW) { 510 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); 511 return 0; 512 } 513 } 514 515 return 1; 516 } 517 518 /* 519 * Call this from platform driver suspend() to see how deeply to suspend. 520 * For example, some controllers (like OHCI) need one of the PLL clocks 521 * in order to act as a wakeup source, and those are not available when 522 * going into slow clock mode. 523 * 524 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have 525 * the very same problem (but not using at91 main_clk), and it'd be better 526 * to add one generic API rather than lots of platform-specific ones. 527 */ 528 int at91_suspend_entering_slow_clock(void) 529 { 530 return (soc_pm.data.mode >= AT91_PM_ULP0); 531 } 532 EXPORT_SYMBOL(at91_suspend_entering_slow_clock); 533 534 static void (*at91_suspend_sram_fn)(struct at91_pm_data *); 535 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data); 536 extern u32 at91_pm_suspend_in_sram_sz; 537 538 static int at91_suspend_finish(unsigned long val) 539 { 540 unsigned char modified_gray_code[] = { 541 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d, 542 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b, 543 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 544 0x10, 0x11, 545 }; 546 unsigned int tmp, index; 547 int i; 548 549 if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) { 550 /* 551 * Bootloader will perform DDR recalibration and will try to 552 * restore the ZQ0SR0 with the value saved here. But the 553 * calibration is buggy and restoring some values from ZQ0SR0 554 * is forbidden and risky thus we need to provide processed 555 * values for these (modified gray code values). 556 */ 557 tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0); 558 559 /* Store pull-down output impedance select. */ 560 index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f; 561 soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index]; 562 563 /* Store pull-up output impedance select. */ 564 index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f; 565 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; 566 567 /* Store pull-down on-die termination impedance select. */ 568 index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f; 569 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; 570 571 /* Store pull-up on-die termination impedance select. */ 572 index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f; 573 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; 574 575 /* 576 * The 1st 8 words of memory might get corrupted in the process 577 * of DDR PHY recalibration; it is saved here in securam and it 578 * will be restored later, after recalibration, by bootloader 579 */ 580 for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++) 581 soc_pm.bu->ddr_phy_calibration[i] = 582 *((unsigned int *)soc_pm.memcs + (i - 1)); 583 } 584 585 flush_cache_all(); 586 outer_disable(); 587 588 at91_suspend_sram_fn(&soc_pm.data); 589 590 return 0; 591 } 592 593 static void at91_pm_switch_ba_to_vbat(void) 594 { 595 unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu); 596 unsigned int val; 597 598 /* Just for safety. */ 599 if (!soc_pm.data.sfrbu) 600 return; 601 602 val = readl(soc_pm.data.sfrbu + offset); 603 604 /* Already on VBAT. */ 605 if (!(val & soc_pm.sfrbu_regs.pswbu.state)) 606 return; 607 608 val &= ~soc_pm.sfrbu_regs.pswbu.softsw; 609 val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl; 610 writel(val, soc_pm.data.sfrbu + offset); 611 612 /* Wait for update. */ 613 val = readl(soc_pm.data.sfrbu + offset); 614 while (val & soc_pm.sfrbu_regs.pswbu.state) 615 val = readl(soc_pm.data.sfrbu + offset); 616 } 617 618 static void at91_pm_suspend(suspend_state_t state) 619 { 620 if (soc_pm.data.mode == AT91_PM_BACKUP) { 621 at91_pm_switch_ba_to_vbat(); 622 623 cpu_suspend(0, at91_suspend_finish); 624 625 /* The SRAM is lost between suspend cycles */ 626 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 627 &at91_pm_suspend_in_sram, 628 at91_pm_suspend_in_sram_sz); 629 } else { 630 at91_suspend_finish(0); 631 } 632 633 outer_resume(); 634 } 635 636 /* 637 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup' 638 * event sources; and reduces DRAM power. But otherwise it's identical to 639 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks. 640 * 641 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must 642 * suspend more deeply, the master clock switches to the clk32k and turns off 643 * the main oscillator 644 * 645 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh 646 */ 647 static int at91_pm_enter(suspend_state_t state) 648 { 649 int ret; 650 651 ret = at91_pm_config_quirks(true); 652 if (ret) 653 return ret; 654 655 switch (state) { 656 case PM_SUSPEND_MEM: 657 case PM_SUSPEND_STANDBY: 658 /* 659 * Ensure that clocks are in a valid state. 660 */ 661 if (soc_pm.data.mode >= AT91_PM_ULP0 && 662 !at91_pm_verify_clocks()) 663 goto error; 664 665 at91_pm_suspend(state); 666 667 break; 668 669 case PM_SUSPEND_ON: 670 cpu_do_idle(); 671 break; 672 673 default: 674 pr_debug("AT91: PM - bogus suspend state %d\n", state); 675 goto error; 676 } 677 678 error: 679 at91_pm_config_quirks(false); 680 return 0; 681 } 682 683 /* 684 * Called right prior to thawing processes. 685 */ 686 static void at91_pm_end(void) 687 { 688 at91_pm_config_ws(soc_pm.data.mode, false); 689 } 690 691 692 static const struct platform_suspend_ops at91_pm_ops = { 693 .valid = at91_pm_valid_state, 694 .begin = at91_pm_begin, 695 .enter = at91_pm_enter, 696 .end = at91_pm_end, 697 }; 698 699 static struct platform_device at91_cpuidle_device = { 700 .name = "cpuidle-at91", 701 }; 702 703 /* 704 * The AT91RM9200 goes into self-refresh mode with this command, and will 705 * terminate self-refresh automatically on the next SDRAM access. 706 * 707 * Self-refresh mode is exited as soon as a memory access is made, but we don't 708 * know for sure when that happens. However, we need to restore the low-power 709 * mode if it was enabled before going idle. Restoring low-power mode while 710 * still in self-refresh is "not recommended", but seems to work. 711 */ 712 static void at91rm9200_standby(void) 713 { 714 asm volatile( 715 "b 1f\n\t" 716 ".align 5\n\t" 717 "1: mcr p15, 0, %0, c7, c10, 4\n\t" 718 " str %2, [%1, %3]\n\t" 719 " mcr p15, 0, %0, c7, c0, 4\n\t" 720 : 721 : "r" (0), "r" (soc_pm.data.ramc[0]), 722 "r" (1), "r" (AT91_MC_SDRAMC_SRR)); 723 } 724 725 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 726 * remember. 727 */ 728 static void at91_ddr_standby(void) 729 { 730 /* Those two values allow us to delay self-refresh activation 731 * to the maximum. */ 732 u32 lpr0, lpr1 = 0; 733 u32 mdr, saved_mdr0, saved_mdr1 = 0; 734 u32 saved_lpr0, saved_lpr1 = 0; 735 736 /* LPDDR1 --> force DDR2 mode during self-refresh */ 737 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR); 738 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 739 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD; 740 mdr |= AT91_DDRSDRC_MD_DDR2; 741 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr); 742 } 743 744 if (soc_pm.data.ramc[1]) { 745 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); 746 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; 747 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 748 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR); 749 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 750 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD; 751 mdr |= AT91_DDRSDRC_MD_DDR2; 752 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr); 753 } 754 } 755 756 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 757 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 758 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 759 760 /* self-refresh mode now */ 761 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 762 if (soc_pm.data.ramc[1]) 763 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); 764 765 cpu_do_idle(); 766 767 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0); 768 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 769 if (soc_pm.data.ramc[1]) { 770 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1); 771 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); 772 } 773 } 774 775 static void sama5d3_ddr_standby(void) 776 { 777 u32 lpr0; 778 u32 saved_lpr0; 779 780 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 781 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 782 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN; 783 784 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 785 786 cpu_do_idle(); 787 788 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 789 } 790 791 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 792 * remember. 793 */ 794 static void at91sam9_sdram_standby(void) 795 { 796 u32 lpr0, lpr1 = 0; 797 u32 saved_lpr0, saved_lpr1 = 0; 798 799 if (soc_pm.data.ramc[1]) { 800 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); 801 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; 802 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 803 } 804 805 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); 806 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; 807 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 808 809 /* self-refresh mode now */ 810 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); 811 if (soc_pm.data.ramc[1]) 812 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); 813 814 cpu_do_idle(); 815 816 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); 817 if (soc_pm.data.ramc[1]) 818 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); 819 } 820 821 static void sama7g5_standby(void) 822 { 823 int pwrtmg, ratio; 824 825 pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL); 826 ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO); 827 828 /* 829 * Place RAM into self-refresh after a maximum idle clocks. The maximum 830 * idle clocks is configured by bootloader in 831 * UDDRC_PWRMGT.SELFREF_TO_X32. 832 */ 833 writel(pwrtmg | UDDRC_PWRCTL_SELFREF_EN, 834 soc_pm.data.ramc[0] + UDDRC_PWRCTL); 835 /* Divide CPU clock by 16. */ 836 writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO); 837 838 cpu_do_idle(); 839 840 /* Restore previous configuration. */ 841 writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO); 842 writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL); 843 } 844 845 struct ramc_info { 846 void (*idle)(void); 847 unsigned int memctrl; 848 }; 849 850 static const struct ramc_info ramc_infos[] __initconst = { 851 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC}, 852 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC}, 853 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 854 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 855 { .idle = sama7g5_standby, }, 856 }; 857 858 static const struct of_device_id ramc_ids[] __initconst = { 859 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] }, 860 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, 861 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, 862 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, 863 { .compatible = "microchip,sama7g5-uddrc", .data = &ramc_infos[4], }, 864 { /*sentinel*/ } 865 }; 866 867 static const struct of_device_id ramc_phy_ids[] __initconst = { 868 { .compatible = "microchip,sama7g5-ddr3phy", }, 869 { /* Sentinel. */ }, 870 }; 871 872 static __init int at91_dt_ramc(bool phy_mandatory) 873 { 874 struct device_node *np; 875 const struct of_device_id *of_id; 876 int idx = 0; 877 void *standby = NULL; 878 const struct ramc_info *ramc; 879 int ret; 880 881 for_each_matching_node_and_match(np, ramc_ids, &of_id) { 882 soc_pm.data.ramc[idx] = of_iomap(np, 0); 883 if (!soc_pm.data.ramc[idx]) { 884 pr_err("unable to map ramc[%d] cpu registers\n", idx); 885 ret = -ENOMEM; 886 of_node_put(np); 887 goto unmap_ramc; 888 } 889 890 ramc = of_id->data; 891 if (ramc) { 892 if (!standby) 893 standby = ramc->idle; 894 soc_pm.data.memctrl = ramc->memctrl; 895 } 896 897 idx++; 898 } 899 900 if (!idx) { 901 pr_err("unable to find compatible ram controller node in dtb\n"); 902 ret = -ENODEV; 903 goto unmap_ramc; 904 } 905 906 /* Lookup for DDR PHY node, if any. */ 907 for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) { 908 soc_pm.data.ramc_phy = of_iomap(np, 0); 909 if (!soc_pm.data.ramc_phy) { 910 pr_err("unable to map ramc phy cpu registers\n"); 911 ret = -ENOMEM; 912 of_node_put(np); 913 goto unmap_ramc; 914 } 915 } 916 917 if (phy_mandatory && !soc_pm.data.ramc_phy) { 918 pr_err("DDR PHY is mandatory!\n"); 919 ret = -ENODEV; 920 goto unmap_ramc; 921 } 922 923 if (!standby) { 924 pr_warn("ramc no standby function available\n"); 925 return 0; 926 } 927 928 at91_cpuidle_device.dev.platform_data = standby; 929 930 return 0; 931 932 unmap_ramc: 933 while (idx) 934 iounmap(soc_pm.data.ramc[--idx]); 935 936 return ret; 937 } 938 939 static void at91rm9200_idle(void) 940 { 941 /* 942 * Disable the processor clock. The processor will be automatically 943 * re-enabled by an interrupt or by a reset. 944 */ 945 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); 946 } 947 948 static void at91sam9_idle(void) 949 { 950 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); 951 cpu_do_idle(); 952 } 953 954 static void __init at91_pm_sram_init(void) 955 { 956 struct gen_pool *sram_pool; 957 phys_addr_t sram_pbase; 958 unsigned long sram_base; 959 struct device_node *node; 960 struct platform_device *pdev = NULL; 961 962 for_each_compatible_node(node, NULL, "mmio-sram") { 963 pdev = of_find_device_by_node(node); 964 if (pdev) { 965 of_node_put(node); 966 break; 967 } 968 } 969 970 if (!pdev) { 971 pr_warn("%s: failed to find sram device!\n", __func__); 972 return; 973 } 974 975 sram_pool = gen_pool_get(&pdev->dev, NULL); 976 if (!sram_pool) { 977 pr_warn("%s: sram pool unavailable!\n", __func__); 978 goto out_put_device; 979 } 980 981 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz); 982 if (!sram_base) { 983 pr_warn("%s: unable to alloc sram!\n", __func__); 984 goto out_put_device; 985 } 986 987 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); 988 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase, 989 at91_pm_suspend_in_sram_sz, false); 990 if (!at91_suspend_sram_fn) { 991 pr_warn("SRAM: Could not map\n"); 992 goto out_put_device; 993 } 994 995 /* Copy the pm suspend handler to SRAM */ 996 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 997 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); 998 return; 999 1000 out_put_device: 1001 put_device(&pdev->dev); 1002 return; 1003 } 1004 1005 static bool __init at91_is_pm_mode_active(int pm_mode) 1006 { 1007 return (soc_pm.data.standby_mode == pm_mode || 1008 soc_pm.data.suspend_mode == pm_mode); 1009 } 1010 1011 static int __init at91_pm_backup_scan_memcs(unsigned long node, 1012 const char *uname, int depth, 1013 void *data) 1014 { 1015 const char *type; 1016 const __be32 *reg; 1017 int *located = data; 1018 int size; 1019 1020 /* Memory node already located. */ 1021 if (*located) 1022 return 0; 1023 1024 type = of_get_flat_dt_prop(node, "device_type", NULL); 1025 1026 /* We are scanning "memory" nodes only. */ 1027 if (!type || strcmp(type, "memory")) 1028 return 0; 1029 1030 reg = of_get_flat_dt_prop(node, "reg", &size); 1031 if (reg) { 1032 soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg)); 1033 *located = 1; 1034 } 1035 1036 return 0; 1037 } 1038 1039 static int __init at91_pm_backup_init(void) 1040 { 1041 struct gen_pool *sram_pool; 1042 struct device_node *np; 1043 struct platform_device *pdev; 1044 int ret = -ENODEV, located = 0; 1045 1046 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) && 1047 !IS_ENABLED(CONFIG_SOC_SAMA7G5)) 1048 return -EPERM; 1049 1050 if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) 1051 return 0; 1052 1053 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); 1054 if (!np) 1055 return ret; 1056 1057 pdev = of_find_device_by_node(np); 1058 of_node_put(np); 1059 if (!pdev) { 1060 pr_warn("%s: failed to find securam device!\n", __func__); 1061 return ret; 1062 } 1063 1064 sram_pool = gen_pool_get(&pdev->dev, NULL); 1065 if (!sram_pool) { 1066 pr_warn("%s: securam pool unavailable!\n", __func__); 1067 goto securam_fail; 1068 } 1069 1070 soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); 1071 if (!soc_pm.bu) { 1072 pr_warn("%s: unable to alloc securam!\n", __func__); 1073 ret = -ENOMEM; 1074 goto securam_fail; 1075 } 1076 1077 soc_pm.bu->suspended = 0; 1078 soc_pm.bu->canary = __pa_symbol(&canary); 1079 soc_pm.bu->resume = __pa_symbol(cpu_resume); 1080 if (soc_pm.data.ramc_phy) { 1081 of_scan_flat_dt(at91_pm_backup_scan_memcs, &located); 1082 if (!located) 1083 goto securam_fail; 1084 } 1085 1086 return 0; 1087 1088 securam_fail: 1089 put_device(&pdev->dev); 1090 return ret; 1091 } 1092 1093 static void __init at91_pm_secure_init(void) 1094 { 1095 int suspend_mode; 1096 struct arm_smccc_res res; 1097 1098 suspend_mode = soc_pm.data.suspend_mode; 1099 1100 res = sam_smccc_call(SAMA5_SMC_SIP_SET_SUSPEND_MODE, 1101 suspend_mode, 0); 1102 if (res.a0 == 0) { 1103 pr_info("AT91: Secure PM: suspend mode set to %s\n", 1104 pm_modes[suspend_mode].pattern); 1105 return; 1106 } 1107 1108 pr_warn("AT91: Secure PM: %s mode not supported !\n", 1109 pm_modes[suspend_mode].pattern); 1110 1111 res = sam_smccc_call(SAMA5_SMC_SIP_GET_SUSPEND_MODE, 0, 0); 1112 if (res.a0 == 0) { 1113 pr_warn("AT91: Secure PM: failed to get default mode\n"); 1114 return; 1115 } 1116 1117 pr_info("AT91: Secure PM: using default suspend mode %s\n", 1118 pm_modes[suspend_mode].pattern); 1119 1120 soc_pm.data.suspend_mode = res.a1; 1121 } 1122 static const struct of_device_id atmel_shdwc_ids[] = { 1123 { .compatible = "atmel,sama5d2-shdwc" }, 1124 { .compatible = "microchip,sam9x60-shdwc" }, 1125 { .compatible = "microchip,sama7g5-shdwc" }, 1126 { /* sentinel. */ } 1127 }; 1128 1129 static const struct of_device_id gmac_ids[] __initconst = { 1130 { .compatible = "atmel,sama5d3-gem" }, 1131 { .compatible = "atmel,sama5d2-gem" }, 1132 { .compatible = "atmel,sama5d29-gem" }, 1133 { .compatible = "microchip,sama7g5-gem" }, 1134 { }, 1135 }; 1136 1137 static const struct of_device_id emac_ids[] __initconst = { 1138 { .compatible = "atmel,sama5d3-macb" }, 1139 { .compatible = "microchip,sama7g5-emac" }, 1140 { }, 1141 }; 1142 1143 /* 1144 * Replaces _mode_to_replace with a supported mode that doesn't depend 1145 * on controller pointed by _map_bitmask 1146 * @_maps: u32 array containing AT91_PM_IOMAP() flags and indexed by AT91 1147 * PM mode 1148 * @_map_bitmask: AT91_PM_IOMAP() bitmask; if _mode_to_replace depends on 1149 * controller represented by _map_bitmask, _mode_to_replace needs to be 1150 * updated 1151 * @_mode_to_replace: standby_mode or suspend_mode that need to be 1152 * updated 1153 * @_mode_to_check: standby_mode or suspend_mode; this is needed here 1154 * to avoid having standby_mode and suspend_mode set with the same AT91 1155 * PM mode 1156 */ 1157 #define AT91_PM_REPLACE_MODE(_maps, _map_bitmask, _mode_to_replace, \ 1158 _mode_to_check) \ 1159 do { \ 1160 if (((_maps)[(_mode_to_replace)]) & (_map_bitmask)) { \ 1161 int _mode_to_use, _mode_complementary; \ 1162 /* Use ULP0 if it doesn't need _map_bitmask. */ \ 1163 if (!((_maps)[AT91_PM_ULP0] & (_map_bitmask))) {\ 1164 _mode_to_use = AT91_PM_ULP0; \ 1165 _mode_complementary = AT91_PM_STANDBY; \ 1166 } else { \ 1167 _mode_to_use = AT91_PM_STANDBY; \ 1168 _mode_complementary = AT91_PM_STANDBY; \ 1169 } \ 1170 \ 1171 if ((_mode_to_check) != _mode_to_use) \ 1172 (_mode_to_replace) = _mode_to_use; \ 1173 else \ 1174 (_mode_to_replace) = _mode_complementary;\ 1175 } \ 1176 } while (0) 1177 1178 /* 1179 * Replaces standby and suspend modes with default supported modes: 1180 * ULP0 and STANDBY. 1181 * @_maps: u32 array indexed by AT91 PM mode containing AT91_PM_IOMAP() 1182 * flags 1183 * @_map: controller specific name; standby and suspend mode need to be 1184 * replaced in order to not depend on this controller 1185 */ 1186 #define AT91_PM_REPLACE_MODES(_maps, _map) \ 1187 do { \ 1188 AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\ 1189 (soc_pm.data.standby_mode), \ 1190 (soc_pm.data.suspend_mode)); \ 1191 AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\ 1192 (soc_pm.data.suspend_mode), \ 1193 (soc_pm.data.standby_mode)); \ 1194 } while (0) 1195 1196 static int __init at91_pm_get_eth_clks(struct device_node *np, 1197 struct clk_bulk_data *clks) 1198 { 1199 clks[AT91_PM_ETH_PCLK].clk = of_clk_get_by_name(np, "pclk"); 1200 if (IS_ERR(clks[AT91_PM_ETH_PCLK].clk)) 1201 return PTR_ERR(clks[AT91_PM_ETH_PCLK].clk); 1202 1203 clks[AT91_PM_ETH_HCLK].clk = of_clk_get_by_name(np, "hclk"); 1204 if (IS_ERR(clks[AT91_PM_ETH_HCLK].clk)) 1205 return PTR_ERR(clks[AT91_PM_ETH_HCLK].clk); 1206 1207 return 0; 1208 } 1209 1210 static int __init at91_pm_eth_clks_empty(struct clk_bulk_data *clks) 1211 { 1212 return IS_ERR(clks[AT91_PM_ETH_PCLK].clk) || 1213 IS_ERR(clks[AT91_PM_ETH_HCLK].clk); 1214 } 1215 1216 static void __init at91_pm_modes_init(const u32 *maps, int len) 1217 { 1218 struct at91_pm_quirk_eth *gmac = &soc_pm.quirks.eth[AT91_PM_G_ETH]; 1219 struct at91_pm_quirk_eth *emac = &soc_pm.quirks.eth[AT91_PM_E_ETH]; 1220 struct device_node *np; 1221 int ret; 1222 1223 ret = at91_pm_backup_init(); 1224 if (ret) { 1225 if (soc_pm.data.standby_mode == AT91_PM_BACKUP) 1226 soc_pm.data.standby_mode = AT91_PM_ULP0; 1227 if (soc_pm.data.suspend_mode == AT91_PM_BACKUP) 1228 soc_pm.data.suspend_mode = AT91_PM_ULP0; 1229 } 1230 1231 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || 1232 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) { 1233 np = of_find_matching_node(NULL, atmel_shdwc_ids); 1234 if (!np) { 1235 pr_warn("%s: failed to find shdwc!\n", __func__); 1236 AT91_PM_REPLACE_MODES(maps, SHDWC); 1237 } else { 1238 soc_pm.data.shdwc = of_iomap(np, 0); 1239 of_node_put(np); 1240 } 1241 } 1242 1243 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || 1244 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) { 1245 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); 1246 if (!np) { 1247 pr_warn("%s: failed to find sfrbu!\n", __func__); 1248 AT91_PM_REPLACE_MODES(maps, SFRBU); 1249 } else { 1250 soc_pm.data.sfrbu = of_iomap(np, 0); 1251 of_node_put(np); 1252 } 1253 } 1254 1255 if ((at91_is_pm_mode_active(AT91_PM_ULP1) || 1256 at91_is_pm_mode_active(AT91_PM_ULP0) || 1257 at91_is_pm_mode_active(AT91_PM_ULP0_FAST)) && 1258 (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(ETHC) || 1259 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(ETHC))) { 1260 np = of_find_matching_node(NULL, gmac_ids); 1261 if (!np) { 1262 np = of_find_matching_node(NULL, emac_ids); 1263 if (np) 1264 goto get_emac_clks; 1265 AT91_PM_REPLACE_MODES(maps, ETHC); 1266 goto unmap_unused_nodes; 1267 } else { 1268 gmac->np = np; 1269 at91_pm_get_eth_clks(np, gmac->clks); 1270 } 1271 1272 np = of_find_matching_node(NULL, emac_ids); 1273 if (!np) { 1274 if (at91_pm_eth_clks_empty(gmac->clks)) 1275 AT91_PM_REPLACE_MODES(maps, ETHC); 1276 } else { 1277 get_emac_clks: 1278 emac->np = np; 1279 ret = at91_pm_get_eth_clks(np, emac->clks); 1280 if (ret && at91_pm_eth_clks_empty(gmac->clks)) { 1281 of_node_put(gmac->np); 1282 of_node_put(emac->np); 1283 gmac->np = NULL; 1284 emac->np = NULL; 1285 } 1286 } 1287 } 1288 1289 unmap_unused_nodes: 1290 /* Unmap all unnecessary. */ 1291 if (soc_pm.data.shdwc && 1292 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || 1293 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) { 1294 iounmap(soc_pm.data.shdwc); 1295 soc_pm.data.shdwc = NULL; 1296 } 1297 1298 if (soc_pm.data.sfrbu && 1299 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || 1300 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) { 1301 iounmap(soc_pm.data.sfrbu); 1302 soc_pm.data.sfrbu = NULL; 1303 } 1304 1305 return; 1306 } 1307 1308 struct pmc_info { 1309 unsigned long uhp_udp_mask; 1310 unsigned long mckr; 1311 unsigned long version; 1312 }; 1313 1314 static const struct pmc_info pmc_infos[] __initconst = { 1315 { 1316 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP, 1317 .mckr = 0x30, 1318 .version = AT91_PMC_V1, 1319 }, 1320 1321 { 1322 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, 1323 .mckr = 0x30, 1324 .version = AT91_PMC_V1, 1325 }, 1326 { 1327 .uhp_udp_mask = AT91SAM926x_PMC_UHP, 1328 .mckr = 0x30, 1329 .version = AT91_PMC_V1, 1330 }, 1331 { .uhp_udp_mask = 0, 1332 .mckr = 0x30, 1333 .version = AT91_PMC_V1, 1334 }, 1335 { 1336 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, 1337 .mckr = 0x28, 1338 .version = AT91_PMC_V2, 1339 }, 1340 { 1341 .mckr = 0x28, 1342 .version = AT91_PMC_V2, 1343 }, 1344 1345 }; 1346 1347 static const struct of_device_id atmel_pmc_ids[] __initconst = { 1348 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] }, 1349 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] }, 1350 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] }, 1351 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] }, 1352 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] }, 1353 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] }, 1354 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] }, 1355 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] }, 1356 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] }, 1357 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, 1358 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, 1359 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, 1360 { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] }, 1361 { /* sentinel */ }, 1362 }; 1363 1364 static void __init at91_pm_modes_validate(const int *modes, int len) 1365 { 1366 u8 i, standby = 0, suspend = 0; 1367 int mode; 1368 1369 for (i = 0; i < len; i++) { 1370 if (standby && suspend) 1371 break; 1372 1373 if (modes[i] == soc_pm.data.standby_mode && !standby) { 1374 standby = 1; 1375 continue; 1376 } 1377 1378 if (modes[i] == soc_pm.data.suspend_mode && !suspend) { 1379 suspend = 1; 1380 continue; 1381 } 1382 } 1383 1384 if (!standby) { 1385 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY) 1386 mode = AT91_PM_ULP0; 1387 else 1388 mode = AT91_PM_STANDBY; 1389 1390 pr_warn("AT91: PM: %s mode not supported! Using %s.\n", 1391 pm_modes[soc_pm.data.standby_mode].pattern, 1392 pm_modes[mode].pattern); 1393 soc_pm.data.standby_mode = mode; 1394 } 1395 1396 if (!suspend) { 1397 if (soc_pm.data.standby_mode == AT91_PM_ULP0) 1398 mode = AT91_PM_STANDBY; 1399 else 1400 mode = AT91_PM_ULP0; 1401 1402 pr_warn("AT91: PM: %s mode not supported! Using %s.\n", 1403 pm_modes[soc_pm.data.suspend_mode].pattern, 1404 pm_modes[mode].pattern); 1405 soc_pm.data.suspend_mode = mode; 1406 } 1407 } 1408 1409 static void __init at91_pm_init(void (*pm_idle)(void)) 1410 { 1411 struct device_node *pmc_np; 1412 const struct of_device_id *of_id; 1413 const struct pmc_info *pmc; 1414 1415 if (at91_cpuidle_device.dev.platform_data) 1416 platform_device_register(&at91_cpuidle_device); 1417 1418 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id); 1419 soc_pm.data.pmc = of_iomap(pmc_np, 0); 1420 of_node_put(pmc_np); 1421 if (!soc_pm.data.pmc) { 1422 pr_err("AT91: PM not supported, PMC not found\n"); 1423 return; 1424 } 1425 1426 pmc = of_id->data; 1427 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask; 1428 soc_pm.data.pmc_mckr_offset = pmc->mckr; 1429 soc_pm.data.pmc_version = pmc->version; 1430 1431 if (pm_idle) 1432 arm_pm_idle = pm_idle; 1433 1434 at91_pm_sram_init(); 1435 1436 if (at91_suspend_sram_fn) { 1437 suspend_set_ops(&at91_pm_ops); 1438 pr_info("AT91: PM: standby: %s, suspend: %s\n", 1439 pm_modes[soc_pm.data.standby_mode].pattern, 1440 pm_modes[soc_pm.data.suspend_mode].pattern); 1441 } else { 1442 pr_info("AT91: PM not supported, due to no SRAM allocated\n"); 1443 } 1444 } 1445 1446 void __init at91rm9200_pm_init(void) 1447 { 1448 int ret; 1449 1450 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200)) 1451 return; 1452 1453 /* 1454 * Force STANDBY and ULP0 mode to avoid calling 1455 * at91_pm_modes_validate() which may increase booting time. 1456 * Platform supports anyway only STANDBY and ULP0 modes. 1457 */ 1458 soc_pm.data.standby_mode = AT91_PM_STANDBY; 1459 soc_pm.data.suspend_mode = AT91_PM_ULP0; 1460 1461 ret = at91_dt_ramc(false); 1462 if (ret) 1463 return; 1464 1465 /* 1466 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. 1467 */ 1468 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); 1469 1470 at91_pm_init(at91rm9200_idle); 1471 } 1472 1473 void __init sam9x60_pm_init(void) 1474 { 1475 static const int modes[] __initconst = { 1476 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, 1477 }; 1478 static const int iomaps[] __initconst = { 1479 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC), 1480 }; 1481 int ret; 1482 1483 if (!IS_ENABLED(CONFIG_SOC_SAM9X60)) 1484 return; 1485 1486 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1487 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1488 ret = at91_dt_ramc(false); 1489 if (ret) 1490 return; 1491 1492 at91_pm_init(NULL); 1493 1494 soc_pm.ws_ids = sam9x60_ws_ids; 1495 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; 1496 } 1497 1498 void __init at91sam9_pm_init(void) 1499 { 1500 int ret; 1501 1502 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9)) 1503 return; 1504 1505 /* 1506 * Force STANDBY and ULP0 mode to avoid calling 1507 * at91_pm_modes_validate() which may increase booting time. 1508 * Platform supports anyway only STANDBY and ULP0 modes. 1509 */ 1510 soc_pm.data.standby_mode = AT91_PM_STANDBY; 1511 soc_pm.data.suspend_mode = AT91_PM_ULP0; 1512 1513 ret = at91_dt_ramc(false); 1514 if (ret) 1515 return; 1516 1517 at91_pm_init(at91sam9_idle); 1518 } 1519 1520 void __init sama5_pm_init(void) 1521 { 1522 static const int modes[] __initconst = { 1523 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, 1524 }; 1525 static const u32 iomaps[] __initconst = { 1526 [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC), 1527 [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC), 1528 }; 1529 int ret; 1530 1531 if (!IS_ENABLED(CONFIG_SOC_SAMA5)) 1532 return; 1533 1534 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1535 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1536 ret = at91_dt_ramc(false); 1537 if (ret) 1538 return; 1539 1540 at91_pm_init(NULL); 1541 1542 /* Quirks applies to ULP0, ULP0 fast and ULP1 modes. */ 1543 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) | 1544 BIT(AT91_PM_ULP0_FAST) | 1545 BIT(AT91_PM_ULP1); 1546 /* Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup source. */ 1547 soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) | 1548 BIT(AT91_PM_ULP0_FAST); 1549 } 1550 1551 void __init sama5d2_pm_init(void) 1552 { 1553 static const int modes[] __initconst = { 1554 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, 1555 AT91_PM_BACKUP, 1556 }; 1557 static const u32 iomaps[] __initconst = { 1558 [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC), 1559 [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC), 1560 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC) | 1561 AT91_PM_IOMAP(ETHC), 1562 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) | 1563 AT91_PM_IOMAP(SFRBU), 1564 }; 1565 int ret; 1566 1567 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) 1568 return; 1569 1570 if (IS_ENABLED(CONFIG_ATMEL_SECURE_PM)) { 1571 pr_warn("AT91: Secure PM: ignoring standby mode\n"); 1572 at91_pm_secure_init(); 1573 return; 1574 } 1575 1576 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1577 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1578 ret = at91_dt_ramc(false); 1579 if (ret) 1580 return; 1581 1582 at91_pm_init(NULL); 1583 1584 soc_pm.ws_ids = sama5d2_ws_ids; 1585 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws; 1586 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws; 1587 1588 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); 1589 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); 1590 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); 1591 soc_pm.sfrbu_regs.pswbu.state = BIT(3); 1592 1593 /* Quirk applies to ULP0, ULP0 fast and ULP1 modes. */ 1594 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) | 1595 BIT(AT91_PM_ULP0_FAST) | 1596 BIT(AT91_PM_ULP1); 1597 /* 1598 * Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup 1599 * source. 1600 */ 1601 soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) | 1602 BIT(AT91_PM_ULP0_FAST); 1603 } 1604 1605 void __init sama7_pm_init(void) 1606 { 1607 static const int modes[] __initconst = { 1608 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP, 1609 }; 1610 static const u32 iomaps[] __initconst = { 1611 [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU), 1612 [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) | 1613 AT91_PM_IOMAP(SHDWC) | 1614 AT91_PM_IOMAP(ETHC), 1615 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) | 1616 AT91_PM_IOMAP(SHDWC), 1617 }; 1618 int ret; 1619 1620 if (!IS_ENABLED(CONFIG_SOC_SAMA7)) 1621 return; 1622 1623 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1624 1625 ret = at91_dt_ramc(true); 1626 if (ret) 1627 return; 1628 1629 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1630 at91_pm_init(NULL); 1631 1632 soc_pm.ws_ids = sama7g5_ws_ids; 1633 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; 1634 1635 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); 1636 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); 1637 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); 1638 soc_pm.sfrbu_regs.pswbu.state = BIT(2); 1639 1640 /* Quirks applies to ULP1 for both Ethernet interfaces. */ 1641 soc_pm.quirks.eth[AT91_PM_E_ETH].modes = BIT(AT91_PM_ULP1); 1642 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP1); 1643 } 1644 1645 static int __init at91_pm_modes_select(char *str) 1646 { 1647 char *s; 1648 substring_t args[MAX_OPT_ARGS]; 1649 int standby, suspend; 1650 1651 if (!str) 1652 return 0; 1653 1654 s = strsep(&str, ","); 1655 standby = match_token(s, pm_modes, args); 1656 if (standby < 0) 1657 return 0; 1658 1659 suspend = match_token(str, pm_modes, args); 1660 if (suspend < 0) 1661 return 0; 1662 1663 soc_pm.data.standby_mode = standby; 1664 soc_pm.data.suspend_mode = suspend; 1665 1666 return 0; 1667 } 1668 early_param("atmel.pm_modes", at91_pm_modes_select); 1669