1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * arch/arm/mach-at91/pm.c 4 * AT91 Power Management 5 * 6 * Copyright (C) 2005 David Brownell 7 */ 8 9 #include <linux/genalloc.h> 10 #include <linux/io.h> 11 #include <linux/of_address.h> 12 #include <linux/of.h> 13 #include <linux/of_fdt.h> 14 #include <linux/of_platform.h> 15 #include <linux/parser.h> 16 #include <linux/suspend.h> 17 18 #include <linux/clk/at91_pmc.h> 19 #include <linux/platform_data/atmel.h> 20 21 #include <soc/at91/pm.h> 22 23 #include <asm/cacheflush.h> 24 #include <asm/fncpy.h> 25 #include <asm/system_misc.h> 26 #include <asm/suspend.h> 27 28 #include "generic.h" 29 #include "pm.h" 30 31 #define BACKUP_DDR_PHY_CALIBRATION (9) 32 33 /** 34 * struct at91_pm_bu - AT91 power management backup unit data structure 35 * @suspended: true if suspended to backup mode 36 * @reserved: reserved 37 * @canary: canary data for memory checking after exit from backup mode 38 * @resume: resume API 39 * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words 40 * of the memory 41 */ 42 struct at91_pm_bu { 43 int suspended; 44 unsigned long reserved; 45 phys_addr_t canary; 46 phys_addr_t resume; 47 unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION]; 48 }; 49 50 /** 51 * struct at91_soc_pm - AT91 SoC power management data structure 52 * @config_shdwc_ws: wakeup sources configuration function for SHDWC 53 * @config_pmc_ws: wakeup srouces configuration function for PMC 54 * @ws_ids: wakup sources of_device_id array 55 * @data: PM data to be used on last phase of suspend 56 * @bu: backup unit mapped data (for backup mode) 57 * @memcs: memory chip select 58 */ 59 struct at91_soc_pm { 60 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); 61 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); 62 const struct of_device_id *ws_ids; 63 struct at91_pm_bu *bu; 64 struct at91_pm_data data; 65 void *memcs; 66 }; 67 68 /** 69 * enum at91_pm_iomaps: IOs that needs to be mapped for different PM modes 70 * @AT91_PM_IOMAP_SHDWC: SHDWC controller 71 * @AT91_PM_IOMAP_SFRBU: SFRBU controller 72 */ 73 enum at91_pm_iomaps { 74 AT91_PM_IOMAP_SHDWC, 75 AT91_PM_IOMAP_SFRBU, 76 }; 77 78 #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name) 79 80 static struct at91_soc_pm soc_pm = { 81 .data = { 82 .standby_mode = AT91_PM_STANDBY, 83 .suspend_mode = AT91_PM_ULP0, 84 }, 85 }; 86 87 static const match_table_t pm_modes __initconst = { 88 { AT91_PM_STANDBY, "standby" }, 89 { AT91_PM_ULP0, "ulp0" }, 90 { AT91_PM_ULP0_FAST, "ulp0-fast" }, 91 { AT91_PM_ULP1, "ulp1" }, 92 { AT91_PM_BACKUP, "backup" }, 93 { -1, NULL }, 94 }; 95 96 #define at91_ramc_read(id, field) \ 97 __raw_readl(soc_pm.data.ramc[id] + field) 98 99 #define at91_ramc_write(id, field, value) \ 100 __raw_writel(value, soc_pm.data.ramc[id] + field) 101 102 static int at91_pm_valid_state(suspend_state_t state) 103 { 104 switch (state) { 105 case PM_SUSPEND_ON: 106 case PM_SUSPEND_STANDBY: 107 case PM_SUSPEND_MEM: 108 return 1; 109 110 default: 111 return 0; 112 } 113 } 114 115 static int canary = 0xA5A5A5A5; 116 117 struct wakeup_source_info { 118 unsigned int pmc_fsmr_bit; 119 unsigned int shdwc_mr_bit; 120 bool set_polarity; 121 }; 122 123 static const struct wakeup_source_info ws_info[] = { 124 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true }, 125 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) }, 126 { .pmc_fsmr_bit = AT91_PMC_USBAL }, 127 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD }, 128 { .pmc_fsmr_bit = AT91_PMC_RTTAL }, 129 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE }, 130 }; 131 132 static const struct of_device_id sama5d2_ws_ids[] = { 133 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] }, 134 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] }, 135 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] }, 136 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, 137 { .compatible = "usb-ohci", .data = &ws_info[2] }, 138 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 139 { .compatible = "usb-ehci", .data = &ws_info[2] }, 140 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] }, 141 { /* sentinel */ } 142 }; 143 144 static const struct of_device_id sam9x60_ws_ids[] = { 145 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] }, 146 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, 147 { .compatible = "usb-ohci", .data = &ws_info[2] }, 148 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 149 { .compatible = "usb-ehci", .data = &ws_info[2] }, 150 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] }, 151 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] }, 152 { /* sentinel */ } 153 }; 154 155 static const struct of_device_id sama7g5_ws_ids[] = { 156 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] }, 157 { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] }, 158 { .compatible = "usb-ohci", .data = &ws_info[2] }, 159 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 160 { .compatible = "usb-ehci", .data = &ws_info[2] }, 161 { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] }, 162 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] }, 163 { /* sentinel */ } 164 }; 165 166 static int at91_pm_config_ws(unsigned int pm_mode, bool set) 167 { 168 const struct wakeup_source_info *wsi; 169 const struct of_device_id *match; 170 struct platform_device *pdev; 171 struct device_node *np; 172 unsigned int mode = 0, polarity = 0, val = 0; 173 174 if (pm_mode != AT91_PM_ULP1) 175 return 0; 176 177 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids) 178 return -EPERM; 179 180 if (!set) { 181 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR); 182 return 0; 183 } 184 185 if (soc_pm.config_shdwc_ws) 186 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity); 187 188 /* SHDWC.MR */ 189 val = readl(soc_pm.data.shdwc + 0x04); 190 191 /* Loop through defined wakeup sources. */ 192 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) { 193 pdev = of_find_device_by_node(np); 194 if (!pdev) 195 continue; 196 197 if (device_may_wakeup(&pdev->dev)) { 198 wsi = match->data; 199 200 /* Check if enabled on SHDWC. */ 201 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit)) 202 goto put_device; 203 204 mode |= wsi->pmc_fsmr_bit; 205 if (wsi->set_polarity) 206 polarity |= wsi->pmc_fsmr_bit; 207 } 208 209 put_device: 210 put_device(&pdev->dev); 211 } 212 213 if (mode) { 214 if (soc_pm.config_pmc_ws) 215 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity); 216 } else { 217 pr_err("AT91: PM: no ULP1 wakeup sources found!"); 218 } 219 220 return mode ? 0 : -EPERM; 221 } 222 223 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode, 224 u32 *polarity) 225 { 226 u32 val; 227 228 /* SHDWC.WUIR */ 229 val = readl(shdwc + 0x0c); 230 *mode |= (val & 0x3ff); 231 *polarity |= ((val >> 16) & 0x3ff); 232 233 return 0; 234 } 235 236 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity) 237 { 238 writel(mode, pmc + AT91_PMC_FSMR); 239 writel(polarity, pmc + AT91_PMC_FSPR); 240 241 return 0; 242 } 243 244 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity) 245 { 246 writel(mode, pmc + AT91_PMC_FSMR); 247 248 return 0; 249 } 250 251 /* 252 * Called after processes are frozen, but before we shutdown devices. 253 */ 254 static int at91_pm_begin(suspend_state_t state) 255 { 256 int ret; 257 258 switch (state) { 259 case PM_SUSPEND_MEM: 260 soc_pm.data.mode = soc_pm.data.suspend_mode; 261 break; 262 263 case PM_SUSPEND_STANDBY: 264 soc_pm.data.mode = soc_pm.data.standby_mode; 265 break; 266 267 default: 268 soc_pm.data.mode = -1; 269 } 270 271 ret = at91_pm_config_ws(soc_pm.data.mode, true); 272 if (ret) 273 return ret; 274 275 if (soc_pm.data.mode == AT91_PM_BACKUP) 276 soc_pm.bu->suspended = 1; 277 else if (soc_pm.bu) 278 soc_pm.bu->suspended = 0; 279 280 return 0; 281 } 282 283 /* 284 * Verify that all the clocks are correct before entering 285 * slow-clock mode. 286 */ 287 static int at91_pm_verify_clocks(void) 288 { 289 unsigned long scsr; 290 int i; 291 292 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR); 293 294 /* USB must not be using PLLB */ 295 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) { 296 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 297 return 0; 298 } 299 300 /* PCK0..PCK3 must be disabled, or configured to use clk32k */ 301 for (i = 0; i < 4; i++) { 302 u32 css; 303 304 if ((scsr & (AT91_PMC_PCK0 << i)) == 0) 305 continue; 306 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; 307 if (css != AT91_PMC_CSS_SLOW) { 308 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); 309 return 0; 310 } 311 } 312 313 return 1; 314 } 315 316 /* 317 * Call this from platform driver suspend() to see how deeply to suspend. 318 * For example, some controllers (like OHCI) need one of the PLL clocks 319 * in order to act as a wakeup source, and those are not available when 320 * going into slow clock mode. 321 * 322 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have 323 * the very same problem (but not using at91 main_clk), and it'd be better 324 * to add one generic API rather than lots of platform-specific ones. 325 */ 326 int at91_suspend_entering_slow_clock(void) 327 { 328 return (soc_pm.data.mode >= AT91_PM_ULP0); 329 } 330 EXPORT_SYMBOL(at91_suspend_entering_slow_clock); 331 332 static void (*at91_suspend_sram_fn)(struct at91_pm_data *); 333 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data); 334 extern u32 at91_pm_suspend_in_sram_sz; 335 336 static int at91_suspend_finish(unsigned long val) 337 { 338 int i; 339 340 if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) { 341 /* 342 * The 1st 8 words of memory might get corrupted in the process 343 * of DDR PHY recalibration; it is saved here in securam and it 344 * will be restored later, after recalibration, by bootloader 345 */ 346 for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++) 347 soc_pm.bu->ddr_phy_calibration[i] = 348 *((unsigned int *)soc_pm.memcs + (i - 1)); 349 } 350 351 flush_cache_all(); 352 outer_disable(); 353 354 at91_suspend_sram_fn(&soc_pm.data); 355 356 return 0; 357 } 358 359 static void at91_pm_suspend(suspend_state_t state) 360 { 361 if (soc_pm.data.mode == AT91_PM_BACKUP) { 362 cpu_suspend(0, at91_suspend_finish); 363 364 /* The SRAM is lost between suspend cycles */ 365 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 366 &at91_pm_suspend_in_sram, 367 at91_pm_suspend_in_sram_sz); 368 } else { 369 at91_suspend_finish(0); 370 } 371 372 outer_resume(); 373 } 374 375 /* 376 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup' 377 * event sources; and reduces DRAM power. But otherwise it's identical to 378 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks. 379 * 380 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must 381 * suspend more deeply, the master clock switches to the clk32k and turns off 382 * the main oscillator 383 * 384 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh 385 */ 386 static int at91_pm_enter(suspend_state_t state) 387 { 388 #ifdef CONFIG_PINCTRL_AT91 389 /* 390 * FIXME: this is needed to communicate between the pinctrl driver and 391 * the PM implementation in the machine. Possibly part of the PM 392 * implementation should be moved down into the pinctrl driver and get 393 * called as part of the generic suspend/resume path. 394 */ 395 at91_pinctrl_gpio_suspend(); 396 #endif 397 398 switch (state) { 399 case PM_SUSPEND_MEM: 400 case PM_SUSPEND_STANDBY: 401 /* 402 * Ensure that clocks are in a valid state. 403 */ 404 if (soc_pm.data.mode >= AT91_PM_ULP0 && 405 !at91_pm_verify_clocks()) 406 goto error; 407 408 at91_pm_suspend(state); 409 410 break; 411 412 case PM_SUSPEND_ON: 413 cpu_do_idle(); 414 break; 415 416 default: 417 pr_debug("AT91: PM - bogus suspend state %d\n", state); 418 goto error; 419 } 420 421 error: 422 #ifdef CONFIG_PINCTRL_AT91 423 at91_pinctrl_gpio_resume(); 424 #endif 425 return 0; 426 } 427 428 /* 429 * Called right prior to thawing processes. 430 */ 431 static void at91_pm_end(void) 432 { 433 at91_pm_config_ws(soc_pm.data.mode, false); 434 } 435 436 437 static const struct platform_suspend_ops at91_pm_ops = { 438 .valid = at91_pm_valid_state, 439 .begin = at91_pm_begin, 440 .enter = at91_pm_enter, 441 .end = at91_pm_end, 442 }; 443 444 static struct platform_device at91_cpuidle_device = { 445 .name = "cpuidle-at91", 446 }; 447 448 /* 449 * The AT91RM9200 goes into self-refresh mode with this command, and will 450 * terminate self-refresh automatically on the next SDRAM access. 451 * 452 * Self-refresh mode is exited as soon as a memory access is made, but we don't 453 * know for sure when that happens. However, we need to restore the low-power 454 * mode if it was enabled before going idle. Restoring low-power mode while 455 * still in self-refresh is "not recommended", but seems to work. 456 */ 457 static void at91rm9200_standby(void) 458 { 459 asm volatile( 460 "b 1f\n\t" 461 ".align 5\n\t" 462 "1: mcr p15, 0, %0, c7, c10, 4\n\t" 463 " str %2, [%1, %3]\n\t" 464 " mcr p15, 0, %0, c7, c0, 4\n\t" 465 : 466 : "r" (0), "r" (soc_pm.data.ramc[0]), 467 "r" (1), "r" (AT91_MC_SDRAMC_SRR)); 468 } 469 470 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 471 * remember. 472 */ 473 static void at91_ddr_standby(void) 474 { 475 /* Those two values allow us to delay self-refresh activation 476 * to the maximum. */ 477 u32 lpr0, lpr1 = 0; 478 u32 mdr, saved_mdr0, saved_mdr1 = 0; 479 u32 saved_lpr0, saved_lpr1 = 0; 480 481 /* LPDDR1 --> force DDR2 mode during self-refresh */ 482 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR); 483 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 484 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD; 485 mdr |= AT91_DDRSDRC_MD_DDR2; 486 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr); 487 } 488 489 if (soc_pm.data.ramc[1]) { 490 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); 491 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; 492 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 493 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR); 494 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 495 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD; 496 mdr |= AT91_DDRSDRC_MD_DDR2; 497 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr); 498 } 499 } 500 501 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 502 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 503 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 504 505 /* self-refresh mode now */ 506 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 507 if (soc_pm.data.ramc[1]) 508 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); 509 510 cpu_do_idle(); 511 512 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0); 513 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 514 if (soc_pm.data.ramc[1]) { 515 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1); 516 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); 517 } 518 } 519 520 static void sama5d3_ddr_standby(void) 521 { 522 u32 lpr0; 523 u32 saved_lpr0; 524 525 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 526 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 527 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN; 528 529 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 530 531 cpu_do_idle(); 532 533 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 534 } 535 536 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 537 * remember. 538 */ 539 static void at91sam9_sdram_standby(void) 540 { 541 u32 lpr0, lpr1 = 0; 542 u32 saved_lpr0, saved_lpr1 = 0; 543 544 if (soc_pm.data.ramc[1]) { 545 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); 546 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; 547 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 548 } 549 550 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); 551 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; 552 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 553 554 /* self-refresh mode now */ 555 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); 556 if (soc_pm.data.ramc[1]) 557 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); 558 559 cpu_do_idle(); 560 561 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); 562 if (soc_pm.data.ramc[1]) 563 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); 564 } 565 566 struct ramc_info { 567 void (*idle)(void); 568 unsigned int memctrl; 569 }; 570 571 static const struct ramc_info ramc_infos[] __initconst = { 572 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC}, 573 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC}, 574 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 575 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 576 }; 577 578 static const struct of_device_id ramc_ids[] __initconst = { 579 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] }, 580 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, 581 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, 582 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, 583 { .compatible = "microchip,sama7g5-uddrc", }, 584 { /*sentinel*/ } 585 }; 586 587 static const struct of_device_id ramc_phy_ids[] __initconst = { 588 { .compatible = "microchip,sama7g5-ddr3phy", }, 589 { /* Sentinel. */ }, 590 }; 591 592 static __init void at91_dt_ramc(bool phy_mandatory) 593 { 594 struct device_node *np; 595 const struct of_device_id *of_id; 596 int idx = 0; 597 void *standby = NULL; 598 const struct ramc_info *ramc; 599 600 for_each_matching_node_and_match(np, ramc_ids, &of_id) { 601 soc_pm.data.ramc[idx] = of_iomap(np, 0); 602 if (!soc_pm.data.ramc[idx]) 603 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx); 604 605 ramc = of_id->data; 606 if (ramc) { 607 if (!standby) 608 standby = ramc->idle; 609 soc_pm.data.memctrl = ramc->memctrl; 610 } 611 612 idx++; 613 } 614 615 if (!idx) 616 panic(pr_fmt("unable to find compatible ram controller node in dtb\n")); 617 618 /* Lookup for DDR PHY node, if any. */ 619 for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) { 620 soc_pm.data.ramc_phy = of_iomap(np, 0); 621 if (!soc_pm.data.ramc_phy) 622 panic(pr_fmt("unable to map ramc phy cpu registers\n")); 623 } 624 625 if (phy_mandatory && !soc_pm.data.ramc_phy) 626 panic(pr_fmt("DDR PHY is mandatory!\n")); 627 628 if (!standby) { 629 pr_warn("ramc no standby function available\n"); 630 return; 631 } 632 633 at91_cpuidle_device.dev.platform_data = standby; 634 } 635 636 static void at91rm9200_idle(void) 637 { 638 /* 639 * Disable the processor clock. The processor will be automatically 640 * re-enabled by an interrupt or by a reset. 641 */ 642 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); 643 } 644 645 static void at91sam9_idle(void) 646 { 647 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); 648 cpu_do_idle(); 649 } 650 651 static void __init at91_pm_sram_init(void) 652 { 653 struct gen_pool *sram_pool; 654 phys_addr_t sram_pbase; 655 unsigned long sram_base; 656 struct device_node *node; 657 struct platform_device *pdev = NULL; 658 659 for_each_compatible_node(node, NULL, "mmio-sram") { 660 pdev = of_find_device_by_node(node); 661 if (pdev) { 662 of_node_put(node); 663 break; 664 } 665 } 666 667 if (!pdev) { 668 pr_warn("%s: failed to find sram device!\n", __func__); 669 return; 670 } 671 672 sram_pool = gen_pool_get(&pdev->dev, NULL); 673 if (!sram_pool) { 674 pr_warn("%s: sram pool unavailable!\n", __func__); 675 goto out_put_device; 676 } 677 678 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz); 679 if (!sram_base) { 680 pr_warn("%s: unable to alloc sram!\n", __func__); 681 goto out_put_device; 682 } 683 684 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); 685 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase, 686 at91_pm_suspend_in_sram_sz, false); 687 if (!at91_suspend_sram_fn) { 688 pr_warn("SRAM: Could not map\n"); 689 goto out_put_device; 690 } 691 692 /* Copy the pm suspend handler to SRAM */ 693 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 694 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); 695 return; 696 697 out_put_device: 698 put_device(&pdev->dev); 699 return; 700 } 701 702 static bool __init at91_is_pm_mode_active(int pm_mode) 703 { 704 return (soc_pm.data.standby_mode == pm_mode || 705 soc_pm.data.suspend_mode == pm_mode); 706 } 707 708 static int __init at91_pm_backup_scan_memcs(unsigned long node, 709 const char *uname, int depth, 710 void *data) 711 { 712 const char *type; 713 const __be32 *reg; 714 int *located = data; 715 int size; 716 717 /* Memory node already located. */ 718 if (*located) 719 return 0; 720 721 type = of_get_flat_dt_prop(node, "device_type", NULL); 722 723 /* We are scanning "memory" nodes only. */ 724 if (!type || strcmp(type, "memory")) 725 return 0; 726 727 reg = of_get_flat_dt_prop(node, "reg", &size); 728 if (reg) { 729 soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg)); 730 *located = 1; 731 } 732 733 return 0; 734 } 735 736 static int __init at91_pm_backup_init(void) 737 { 738 struct gen_pool *sram_pool; 739 struct device_node *np; 740 struct platform_device *pdev; 741 int ret = -ENODEV, located = 0; 742 743 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) && 744 !IS_ENABLED(CONFIG_SOC_SAMA7G5)) 745 return -EPERM; 746 747 if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) 748 return 0; 749 750 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); 751 if (!np) 752 return ret; 753 754 pdev = of_find_device_by_node(np); 755 of_node_put(np); 756 if (!pdev) { 757 pr_warn("%s: failed to find securam device!\n", __func__); 758 return ret; 759 } 760 761 sram_pool = gen_pool_get(&pdev->dev, NULL); 762 if (!sram_pool) { 763 pr_warn("%s: securam pool unavailable!\n", __func__); 764 goto securam_fail; 765 } 766 767 soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); 768 if (!soc_pm.bu) { 769 pr_warn("%s: unable to alloc securam!\n", __func__); 770 ret = -ENOMEM; 771 goto securam_fail; 772 } 773 774 soc_pm.bu->suspended = 0; 775 soc_pm.bu->canary = __pa_symbol(&canary); 776 soc_pm.bu->resume = __pa_symbol(cpu_resume); 777 if (soc_pm.data.ramc_phy) { 778 of_scan_flat_dt(at91_pm_backup_scan_memcs, &located); 779 if (!located) 780 goto securam_fail; 781 782 /* DDR3PHY_ZQ0SR0 */ 783 soc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy + 784 0x188); 785 } 786 787 return 0; 788 789 securam_fail: 790 put_device(&pdev->dev); 791 return ret; 792 } 793 794 static const struct of_device_id atmel_shdwc_ids[] = { 795 { .compatible = "atmel,sama5d2-shdwc" }, 796 { .compatible = "microchip,sam9x60-shdwc" }, 797 { .compatible = "microchip,sama7g5-shdwc" }, 798 { /* sentinel. */ } 799 }; 800 801 static void __init at91_pm_modes_init(const u32 *maps, int len) 802 { 803 struct device_node *np; 804 int ret, mode; 805 806 ret = at91_pm_backup_init(); 807 if (ret) { 808 if (soc_pm.data.standby_mode == AT91_PM_BACKUP) 809 soc_pm.data.standby_mode = AT91_PM_ULP0; 810 if (soc_pm.data.suspend_mode == AT91_PM_BACKUP) 811 soc_pm.data.suspend_mode = AT91_PM_ULP0; 812 } 813 814 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || 815 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) { 816 np = of_find_matching_node(NULL, atmel_shdwc_ids); 817 if (!np) { 818 pr_warn("%s: failed to find shdwc!\n", __func__); 819 820 /* Use ULP0 if it doesn't needs SHDWC.*/ 821 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC))) 822 mode = AT91_PM_ULP0; 823 else 824 mode = AT91_PM_STANDBY; 825 826 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC)) 827 soc_pm.data.standby_mode = mode; 828 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) 829 soc_pm.data.suspend_mode = mode; 830 } else { 831 soc_pm.data.shdwc = of_iomap(np, 0); 832 of_node_put(np); 833 } 834 } 835 836 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || 837 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) { 838 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); 839 if (!np) { 840 pr_warn("%s: failed to find sfrbu!\n", __func__); 841 842 /* 843 * Use ULP0 if it doesn't need SHDWC or if SHDWC 844 * was already located. 845 */ 846 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) || 847 soc_pm.data.shdwc) 848 mode = AT91_PM_ULP0; 849 else 850 mode = AT91_PM_STANDBY; 851 852 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU)) 853 soc_pm.data.standby_mode = mode; 854 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) 855 soc_pm.data.suspend_mode = mode; 856 } else { 857 soc_pm.data.sfrbu = of_iomap(np, 0); 858 of_node_put(np); 859 } 860 } 861 862 /* Unmap all unnecessary. */ 863 if (soc_pm.data.shdwc && 864 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || 865 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) { 866 iounmap(soc_pm.data.shdwc); 867 soc_pm.data.shdwc = NULL; 868 } 869 870 if (soc_pm.data.sfrbu && 871 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || 872 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) { 873 iounmap(soc_pm.data.sfrbu); 874 soc_pm.data.sfrbu = NULL; 875 } 876 877 return; 878 } 879 880 struct pmc_info { 881 unsigned long uhp_udp_mask; 882 unsigned long mckr; 883 unsigned long version; 884 }; 885 886 static const struct pmc_info pmc_infos[] __initconst = { 887 { 888 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP, 889 .mckr = 0x30, 890 .version = AT91_PMC_V1, 891 }, 892 893 { 894 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, 895 .mckr = 0x30, 896 .version = AT91_PMC_V1, 897 }, 898 { 899 .uhp_udp_mask = AT91SAM926x_PMC_UHP, 900 .mckr = 0x30, 901 .version = AT91_PMC_V1, 902 }, 903 { .uhp_udp_mask = 0, 904 .mckr = 0x30, 905 .version = AT91_PMC_V1, 906 }, 907 { 908 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, 909 .mckr = 0x28, 910 .version = AT91_PMC_V2, 911 }, 912 { 913 .mckr = 0x28, 914 .version = AT91_PMC_V2, 915 }, 916 917 }; 918 919 static const struct of_device_id atmel_pmc_ids[] __initconst = { 920 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] }, 921 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] }, 922 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] }, 923 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] }, 924 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] }, 925 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] }, 926 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] }, 927 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] }, 928 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] }, 929 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, 930 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, 931 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, 932 { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] }, 933 { /* sentinel */ }, 934 }; 935 936 static void __init at91_pm_modes_validate(const int *modes, int len) 937 { 938 u8 i, standby = 0, suspend = 0; 939 int mode; 940 941 for (i = 0; i < len; i++) { 942 if (standby && suspend) 943 break; 944 945 if (modes[i] == soc_pm.data.standby_mode && !standby) { 946 standby = 1; 947 continue; 948 } 949 950 if (modes[i] == soc_pm.data.suspend_mode && !suspend) { 951 suspend = 1; 952 continue; 953 } 954 } 955 956 if (!standby) { 957 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY) 958 mode = AT91_PM_ULP0; 959 else 960 mode = AT91_PM_STANDBY; 961 962 pr_warn("AT91: PM: %s mode not supported! Using %s.\n", 963 pm_modes[soc_pm.data.standby_mode].pattern, 964 pm_modes[mode].pattern); 965 soc_pm.data.standby_mode = mode; 966 } 967 968 if (!suspend) { 969 if (soc_pm.data.standby_mode == AT91_PM_ULP0) 970 mode = AT91_PM_STANDBY; 971 else 972 mode = AT91_PM_ULP0; 973 974 pr_warn("AT91: PM: %s mode not supported! Using %s.\n", 975 pm_modes[soc_pm.data.suspend_mode].pattern, 976 pm_modes[mode].pattern); 977 soc_pm.data.suspend_mode = mode; 978 } 979 } 980 981 static void __init at91_pm_init(void (*pm_idle)(void)) 982 { 983 struct device_node *pmc_np; 984 const struct of_device_id *of_id; 985 const struct pmc_info *pmc; 986 987 if (at91_cpuidle_device.dev.platform_data) 988 platform_device_register(&at91_cpuidle_device); 989 990 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id); 991 soc_pm.data.pmc = of_iomap(pmc_np, 0); 992 of_node_put(pmc_np); 993 if (!soc_pm.data.pmc) { 994 pr_err("AT91: PM not supported, PMC not found\n"); 995 return; 996 } 997 998 pmc = of_id->data; 999 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask; 1000 soc_pm.data.pmc_mckr_offset = pmc->mckr; 1001 soc_pm.data.pmc_version = pmc->version; 1002 1003 if (pm_idle) 1004 arm_pm_idle = pm_idle; 1005 1006 at91_pm_sram_init(); 1007 1008 if (at91_suspend_sram_fn) { 1009 suspend_set_ops(&at91_pm_ops); 1010 pr_info("AT91: PM: standby: %s, suspend: %s\n", 1011 pm_modes[soc_pm.data.standby_mode].pattern, 1012 pm_modes[soc_pm.data.suspend_mode].pattern); 1013 } else { 1014 pr_info("AT91: PM not supported, due to no SRAM allocated\n"); 1015 } 1016 } 1017 1018 void __init at91rm9200_pm_init(void) 1019 { 1020 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200)) 1021 return; 1022 1023 /* 1024 * Force STANDBY and ULP0 mode to avoid calling 1025 * at91_pm_modes_validate() which may increase booting time. 1026 * Platform supports anyway only STANDBY and ULP0 modes. 1027 */ 1028 soc_pm.data.standby_mode = AT91_PM_STANDBY; 1029 soc_pm.data.suspend_mode = AT91_PM_ULP0; 1030 1031 at91_dt_ramc(false); 1032 1033 /* 1034 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. 1035 */ 1036 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); 1037 1038 at91_pm_init(at91rm9200_idle); 1039 } 1040 1041 void __init sam9x60_pm_init(void) 1042 { 1043 static const int modes[] __initconst = { 1044 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, 1045 }; 1046 static const int iomaps[] __initconst = { 1047 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC), 1048 }; 1049 1050 if (!IS_ENABLED(CONFIG_SOC_SAM9X60)) 1051 return; 1052 1053 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1054 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1055 at91_dt_ramc(false); 1056 at91_pm_init(NULL); 1057 1058 soc_pm.ws_ids = sam9x60_ws_ids; 1059 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; 1060 } 1061 1062 void __init at91sam9_pm_init(void) 1063 { 1064 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9)) 1065 return; 1066 1067 /* 1068 * Force STANDBY and ULP0 mode to avoid calling 1069 * at91_pm_modes_validate() which may increase booting time. 1070 * Platform supports anyway only STANDBY and ULP0 modes. 1071 */ 1072 soc_pm.data.standby_mode = AT91_PM_STANDBY; 1073 soc_pm.data.suspend_mode = AT91_PM_ULP0; 1074 1075 at91_dt_ramc(false); 1076 at91_pm_init(at91sam9_idle); 1077 } 1078 1079 void __init sama5_pm_init(void) 1080 { 1081 static const int modes[] __initconst = { 1082 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, 1083 }; 1084 1085 if (!IS_ENABLED(CONFIG_SOC_SAMA5)) 1086 return; 1087 1088 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1089 at91_dt_ramc(false); 1090 at91_pm_init(NULL); 1091 } 1092 1093 void __init sama5d2_pm_init(void) 1094 { 1095 static const int modes[] __initconst = { 1096 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, 1097 AT91_PM_BACKUP, 1098 }; 1099 static const u32 iomaps[] __initconst = { 1100 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC), 1101 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) | 1102 AT91_PM_IOMAP(SFRBU), 1103 }; 1104 1105 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) 1106 return; 1107 1108 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1109 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1110 at91_dt_ramc(false); 1111 at91_pm_init(NULL); 1112 1113 soc_pm.ws_ids = sama5d2_ws_ids; 1114 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws; 1115 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws; 1116 } 1117 1118 void __init sama7_pm_init(void) 1119 { 1120 static const int modes[] __initconst = { 1121 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP, 1122 }; 1123 static const u32 iomaps[] __initconst = { 1124 [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU), 1125 [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) | 1126 AT91_PM_IOMAP(SHDWC), 1127 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) | 1128 AT91_PM_IOMAP(SHDWC), 1129 }; 1130 1131 if (!IS_ENABLED(CONFIG_SOC_SAMA7)) 1132 return; 1133 1134 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1135 1136 at91_dt_ramc(true); 1137 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1138 at91_pm_init(NULL); 1139 1140 soc_pm.ws_ids = sama7g5_ws_ids; 1141 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; 1142 } 1143 1144 static int __init at91_pm_modes_select(char *str) 1145 { 1146 char *s; 1147 substring_t args[MAX_OPT_ARGS]; 1148 int standby, suspend; 1149 1150 if (!str) 1151 return 0; 1152 1153 s = strsep(&str, ","); 1154 standby = match_token(s, pm_modes, args); 1155 if (standby < 0) 1156 return 0; 1157 1158 suspend = match_token(str, pm_modes, args); 1159 if (suspend < 0) 1160 return 0; 1161 1162 soc_pm.data.standby_mode = standby; 1163 soc_pm.data.suspend_mode = suspend; 1164 1165 return 0; 1166 } 1167 early_param("atmel.pm_modes", at91_pm_modes_select); 1168