1 /* 2 * arch/arm/mach-at91/pm.c 3 * AT91 Power Management 4 * 5 * Copyright (C) 2005 David Brownell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13 #include <linux/genalloc.h> 14 #include <linux/io.h> 15 #include <linux/of_address.h> 16 #include <linux/of.h> 17 #include <linux/of_platform.h> 18 #include <linux/parser.h> 19 #include <linux/suspend.h> 20 21 #include <linux/clk/at91_pmc.h> 22 23 #include <asm/cacheflush.h> 24 #include <asm/fncpy.h> 25 #include <asm/system_misc.h> 26 #include <asm/suspend.h> 27 28 #include "generic.h" 29 #include "pm.h" 30 31 /* 32 * FIXME: this is needed to communicate between the pinctrl driver and 33 * the PM implementation in the machine. Possibly part of the PM 34 * implementation should be moved down into the pinctrl driver and get 35 * called as part of the generic suspend/resume path. 36 */ 37 #ifdef CONFIG_PINCTRL_AT91 38 extern void at91_pinctrl_gpio_suspend(void); 39 extern void at91_pinctrl_gpio_resume(void); 40 #endif 41 42 static const match_table_t pm_modes __initconst = { 43 { AT91_PM_STANDBY, "standby" }, 44 { AT91_PM_ULP0, "ulp0" }, 45 { AT91_PM_ULP1, "ulp1" }, 46 { AT91_PM_BACKUP, "backup" }, 47 { -1, NULL }, 48 }; 49 50 static struct at91_pm_data pm_data = { 51 .standby_mode = AT91_PM_STANDBY, 52 .suspend_mode = AT91_PM_ULP0, 53 }; 54 55 #define at91_ramc_read(id, field) \ 56 __raw_readl(pm_data.ramc[id] + field) 57 58 #define at91_ramc_write(id, field, value) \ 59 __raw_writel(value, pm_data.ramc[id] + field) 60 61 static int at91_pm_valid_state(suspend_state_t state) 62 { 63 switch (state) { 64 case PM_SUSPEND_ON: 65 case PM_SUSPEND_STANDBY: 66 case PM_SUSPEND_MEM: 67 return 1; 68 69 default: 70 return 0; 71 } 72 } 73 74 static int canary = 0xA5A5A5A5; 75 76 static struct at91_pm_bu { 77 int suspended; 78 unsigned long reserved; 79 phys_addr_t canary; 80 phys_addr_t resume; 81 } *pm_bu; 82 83 struct wakeup_source_info { 84 unsigned int pmc_fsmr_bit; 85 unsigned int shdwc_mr_bit; 86 bool set_polarity; 87 }; 88 89 static const struct wakeup_source_info ws_info[] = { 90 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true }, 91 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) }, 92 { .pmc_fsmr_bit = AT91_PMC_USBAL }, 93 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD }, 94 }; 95 96 static const struct of_device_id sama5d2_ws_ids[] = { 97 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] }, 98 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] }, 99 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] }, 100 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, 101 { .compatible = "usb-ohci", .data = &ws_info[2] }, 102 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 103 { .compatible = "usb-ehci", .data = &ws_info[2] }, 104 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] }, 105 { /* sentinel */ } 106 }; 107 108 static int at91_pm_config_ws(unsigned int pm_mode, bool set) 109 { 110 const struct wakeup_source_info *wsi; 111 const struct of_device_id *match; 112 struct platform_device *pdev; 113 struct device_node *np; 114 unsigned int mode = 0, polarity = 0, val = 0; 115 116 if (pm_mode != AT91_PM_ULP1) 117 return 0; 118 119 if (!pm_data.pmc || !pm_data.shdwc) 120 return -EPERM; 121 122 if (!set) { 123 writel(mode, pm_data.pmc + AT91_PMC_FSMR); 124 return 0; 125 } 126 127 /* SHDWC.WUIR */ 128 val = readl(pm_data.shdwc + 0x0c); 129 mode |= (val & 0x3ff); 130 polarity |= ((val >> 16) & 0x3ff); 131 132 /* SHDWC.MR */ 133 val = readl(pm_data.shdwc + 0x04); 134 135 /* Loop through defined wakeup sources. */ 136 for_each_matching_node_and_match(np, sama5d2_ws_ids, &match) { 137 pdev = of_find_device_by_node(np); 138 if (!pdev) 139 continue; 140 141 if (device_may_wakeup(&pdev->dev)) { 142 wsi = match->data; 143 144 /* Check if enabled on SHDWC. */ 145 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit)) 146 goto put_device; 147 148 mode |= wsi->pmc_fsmr_bit; 149 if (wsi->set_polarity) 150 polarity |= wsi->pmc_fsmr_bit; 151 } 152 153 put_device: 154 put_device(&pdev->dev); 155 } 156 157 if (mode) { 158 writel(mode, pm_data.pmc + AT91_PMC_FSMR); 159 writel(polarity, pm_data.pmc + AT91_PMC_FSPR); 160 } else { 161 pr_err("AT91: PM: no ULP1 wakeup sources found!"); 162 } 163 164 return mode ? 0 : -EPERM; 165 } 166 167 /* 168 * Called after processes are frozen, but before we shutdown devices. 169 */ 170 static int at91_pm_begin(suspend_state_t state) 171 { 172 switch (state) { 173 case PM_SUSPEND_MEM: 174 pm_data.mode = pm_data.suspend_mode; 175 break; 176 177 case PM_SUSPEND_STANDBY: 178 pm_data.mode = pm_data.standby_mode; 179 break; 180 181 default: 182 pm_data.mode = -1; 183 } 184 185 return at91_pm_config_ws(pm_data.mode, true); 186 } 187 188 /* 189 * Verify that all the clocks are correct before entering 190 * slow-clock mode. 191 */ 192 static int at91_pm_verify_clocks(void) 193 { 194 unsigned long scsr; 195 int i; 196 197 scsr = readl(pm_data.pmc + AT91_PMC_SCSR); 198 199 /* USB must not be using PLLB */ 200 if ((scsr & pm_data.uhp_udp_mask) != 0) { 201 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 202 return 0; 203 } 204 205 /* PCK0..PCK3 must be disabled, or configured to use clk32k */ 206 for (i = 0; i < 4; i++) { 207 u32 css; 208 209 if ((scsr & (AT91_PMC_PCK0 << i)) == 0) 210 continue; 211 css = readl(pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; 212 if (css != AT91_PMC_CSS_SLOW) { 213 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); 214 return 0; 215 } 216 } 217 218 return 1; 219 } 220 221 /* 222 * Call this from platform driver suspend() to see how deeply to suspend. 223 * For example, some controllers (like OHCI) need one of the PLL clocks 224 * in order to act as a wakeup source, and those are not available when 225 * going into slow clock mode. 226 * 227 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have 228 * the very same problem (but not using at91 main_clk), and it'd be better 229 * to add one generic API rather than lots of platform-specific ones. 230 */ 231 int at91_suspend_entering_slow_clock(void) 232 { 233 return (pm_data.mode >= AT91_PM_ULP0); 234 } 235 EXPORT_SYMBOL(at91_suspend_entering_slow_clock); 236 237 static void (*at91_suspend_sram_fn)(struct at91_pm_data *); 238 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data); 239 extern u32 at91_pm_suspend_in_sram_sz; 240 241 static int at91_suspend_finish(unsigned long val) 242 { 243 flush_cache_all(); 244 outer_disable(); 245 246 at91_suspend_sram_fn(&pm_data); 247 248 return 0; 249 } 250 251 static void at91_pm_suspend(suspend_state_t state) 252 { 253 if (pm_data.mode == AT91_PM_BACKUP) { 254 pm_bu->suspended = 1; 255 256 cpu_suspend(0, at91_suspend_finish); 257 258 /* The SRAM is lost between suspend cycles */ 259 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 260 &at91_pm_suspend_in_sram, 261 at91_pm_suspend_in_sram_sz); 262 } else { 263 at91_suspend_finish(0); 264 } 265 266 outer_resume(); 267 } 268 269 /* 270 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup' 271 * event sources; and reduces DRAM power. But otherwise it's identical to 272 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks. 273 * 274 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must 275 * suspend more deeply, the master clock switches to the clk32k and turns off 276 * the main oscillator 277 * 278 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh 279 */ 280 static int at91_pm_enter(suspend_state_t state) 281 { 282 #ifdef CONFIG_PINCTRL_AT91 283 at91_pinctrl_gpio_suspend(); 284 #endif 285 286 switch (state) { 287 case PM_SUSPEND_MEM: 288 case PM_SUSPEND_STANDBY: 289 /* 290 * Ensure that clocks are in a valid state. 291 */ 292 if (pm_data.mode >= AT91_PM_ULP0 && 293 !at91_pm_verify_clocks()) 294 goto error; 295 296 at91_pm_suspend(state); 297 298 break; 299 300 case PM_SUSPEND_ON: 301 cpu_do_idle(); 302 break; 303 304 default: 305 pr_debug("AT91: PM - bogus suspend state %d\n", state); 306 goto error; 307 } 308 309 error: 310 #ifdef CONFIG_PINCTRL_AT91 311 at91_pinctrl_gpio_resume(); 312 #endif 313 return 0; 314 } 315 316 /* 317 * Called right prior to thawing processes. 318 */ 319 static void at91_pm_end(void) 320 { 321 at91_pm_config_ws(pm_data.mode, false); 322 } 323 324 325 static const struct platform_suspend_ops at91_pm_ops = { 326 .valid = at91_pm_valid_state, 327 .begin = at91_pm_begin, 328 .enter = at91_pm_enter, 329 .end = at91_pm_end, 330 }; 331 332 static struct platform_device at91_cpuidle_device = { 333 .name = "cpuidle-at91", 334 }; 335 336 /* 337 * The AT91RM9200 goes into self-refresh mode with this command, and will 338 * terminate self-refresh automatically on the next SDRAM access. 339 * 340 * Self-refresh mode is exited as soon as a memory access is made, but we don't 341 * know for sure when that happens. However, we need to restore the low-power 342 * mode if it was enabled before going idle. Restoring low-power mode while 343 * still in self-refresh is "not recommended", but seems to work. 344 */ 345 static void at91rm9200_standby(void) 346 { 347 asm volatile( 348 "b 1f\n\t" 349 ".align 5\n\t" 350 "1: mcr p15, 0, %0, c7, c10, 4\n\t" 351 " str %2, [%1, %3]\n\t" 352 " mcr p15, 0, %0, c7, c0, 4\n\t" 353 : 354 : "r" (0), "r" (pm_data.ramc[0]), 355 "r" (1), "r" (AT91_MC_SDRAMC_SRR)); 356 } 357 358 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 359 * remember. 360 */ 361 static void at91_ddr_standby(void) 362 { 363 /* Those two values allow us to delay self-refresh activation 364 * to the maximum. */ 365 u32 lpr0, lpr1 = 0; 366 u32 mdr, saved_mdr0, saved_mdr1 = 0; 367 u32 saved_lpr0, saved_lpr1 = 0; 368 369 /* LPDDR1 --> force DDR2 mode during self-refresh */ 370 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR); 371 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 372 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD; 373 mdr |= AT91_DDRSDRC_MD_DDR2; 374 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr); 375 } 376 377 if (pm_data.ramc[1]) { 378 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); 379 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; 380 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 381 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR); 382 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 383 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD; 384 mdr |= AT91_DDRSDRC_MD_DDR2; 385 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr); 386 } 387 } 388 389 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 390 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 391 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 392 393 /* self-refresh mode now */ 394 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 395 if (pm_data.ramc[1]) 396 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); 397 398 cpu_do_idle(); 399 400 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0); 401 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 402 if (pm_data.ramc[1]) { 403 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1); 404 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); 405 } 406 } 407 408 static void sama5d3_ddr_standby(void) 409 { 410 u32 lpr0; 411 u32 saved_lpr0; 412 413 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 414 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 415 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN; 416 417 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 418 419 cpu_do_idle(); 420 421 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 422 } 423 424 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 425 * remember. 426 */ 427 static void at91sam9_sdram_standby(void) 428 { 429 u32 lpr0, lpr1 = 0; 430 u32 saved_lpr0, saved_lpr1 = 0; 431 432 if (pm_data.ramc[1]) { 433 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); 434 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; 435 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 436 } 437 438 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); 439 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; 440 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 441 442 /* self-refresh mode now */ 443 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); 444 if (pm_data.ramc[1]) 445 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); 446 447 cpu_do_idle(); 448 449 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); 450 if (pm_data.ramc[1]) 451 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); 452 } 453 454 struct ramc_info { 455 void (*idle)(void); 456 unsigned int memctrl; 457 }; 458 459 static const struct ramc_info ramc_infos[] __initconst = { 460 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC}, 461 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC}, 462 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 463 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 464 }; 465 466 static const struct of_device_id ramc_ids[] __initconst = { 467 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] }, 468 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, 469 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, 470 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, 471 { /*sentinel*/ } 472 }; 473 474 static __init void at91_dt_ramc(void) 475 { 476 struct device_node *np; 477 const struct of_device_id *of_id; 478 int idx = 0; 479 void *standby = NULL; 480 const struct ramc_info *ramc; 481 482 for_each_matching_node_and_match(np, ramc_ids, &of_id) { 483 pm_data.ramc[idx] = of_iomap(np, 0); 484 if (!pm_data.ramc[idx]) 485 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx); 486 487 ramc = of_id->data; 488 if (!standby) 489 standby = ramc->idle; 490 pm_data.memctrl = ramc->memctrl; 491 492 idx++; 493 } 494 495 if (!idx) 496 panic(pr_fmt("unable to find compatible ram controller node in dtb\n")); 497 498 if (!standby) { 499 pr_warn("ramc no standby function available\n"); 500 return; 501 } 502 503 at91_cpuidle_device.dev.platform_data = standby; 504 } 505 506 static void at91rm9200_idle(void) 507 { 508 /* 509 * Disable the processor clock. The processor will be automatically 510 * re-enabled by an interrupt or by a reset. 511 */ 512 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR); 513 } 514 515 static void at91sam9_idle(void) 516 { 517 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR); 518 cpu_do_idle(); 519 } 520 521 static void __init at91_pm_sram_init(void) 522 { 523 struct gen_pool *sram_pool; 524 phys_addr_t sram_pbase; 525 unsigned long sram_base; 526 struct device_node *node; 527 struct platform_device *pdev = NULL; 528 529 for_each_compatible_node(node, NULL, "mmio-sram") { 530 pdev = of_find_device_by_node(node); 531 if (pdev) { 532 of_node_put(node); 533 break; 534 } 535 } 536 537 if (!pdev) { 538 pr_warn("%s: failed to find sram device!\n", __func__); 539 return; 540 } 541 542 sram_pool = gen_pool_get(&pdev->dev, NULL); 543 if (!sram_pool) { 544 pr_warn("%s: sram pool unavailable!\n", __func__); 545 return; 546 } 547 548 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz); 549 if (!sram_base) { 550 pr_warn("%s: unable to alloc sram!\n", __func__); 551 return; 552 } 553 554 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); 555 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase, 556 at91_pm_suspend_in_sram_sz, false); 557 if (!at91_suspend_sram_fn) { 558 pr_warn("SRAM: Could not map\n"); 559 return; 560 } 561 562 /* Copy the pm suspend handler to SRAM */ 563 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 564 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); 565 } 566 567 static bool __init at91_is_pm_mode_active(int pm_mode) 568 { 569 return (pm_data.standby_mode == pm_mode || 570 pm_data.suspend_mode == pm_mode); 571 } 572 573 static int __init at91_pm_backup_init(void) 574 { 575 struct gen_pool *sram_pool; 576 struct device_node *np; 577 struct platform_device *pdev = NULL; 578 int ret = -ENODEV; 579 580 if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) 581 return 0; 582 583 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); 584 if (!np) { 585 pr_warn("%s: failed to find sfrbu!\n", __func__); 586 return ret; 587 } 588 589 pm_data.sfrbu = of_iomap(np, 0); 590 of_node_put(np); 591 592 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); 593 if (!np) 594 goto securam_fail; 595 596 pdev = of_find_device_by_node(np); 597 of_node_put(np); 598 if (!pdev) { 599 pr_warn("%s: failed to find securam device!\n", __func__); 600 goto securam_fail; 601 } 602 603 sram_pool = gen_pool_get(&pdev->dev, NULL); 604 if (!sram_pool) { 605 pr_warn("%s: securam pool unavailable!\n", __func__); 606 goto securam_fail; 607 } 608 609 pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); 610 if (!pm_bu) { 611 pr_warn("%s: unable to alloc securam!\n", __func__); 612 ret = -ENOMEM; 613 goto securam_fail; 614 } 615 616 pm_bu->suspended = 0; 617 pm_bu->canary = __pa_symbol(&canary); 618 pm_bu->resume = __pa_symbol(cpu_resume); 619 620 return 0; 621 622 securam_fail: 623 iounmap(pm_data.sfrbu); 624 pm_data.sfrbu = NULL; 625 return ret; 626 } 627 628 static void __init at91_pm_use_default_mode(int pm_mode) 629 { 630 if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP) 631 return; 632 633 if (pm_data.standby_mode == pm_mode) 634 pm_data.standby_mode = AT91_PM_ULP0; 635 if (pm_data.suspend_mode == pm_mode) 636 pm_data.suspend_mode = AT91_PM_ULP0; 637 } 638 639 static void __init at91_pm_modes_init(void) 640 { 641 struct device_node *np; 642 int ret; 643 644 if (!at91_is_pm_mode_active(AT91_PM_BACKUP) && 645 !at91_is_pm_mode_active(AT91_PM_ULP1)) 646 return; 647 648 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc"); 649 if (!np) { 650 pr_warn("%s: failed to find shdwc!\n", __func__); 651 goto ulp1_default; 652 } 653 654 pm_data.shdwc = of_iomap(np, 0); 655 of_node_put(np); 656 657 ret = at91_pm_backup_init(); 658 if (ret) { 659 if (!at91_is_pm_mode_active(AT91_PM_ULP1)) 660 goto unmap; 661 else 662 goto backup_default; 663 } 664 665 return; 666 667 unmap: 668 iounmap(pm_data.shdwc); 669 pm_data.shdwc = NULL; 670 ulp1_default: 671 at91_pm_use_default_mode(AT91_PM_ULP1); 672 backup_default: 673 at91_pm_use_default_mode(AT91_PM_BACKUP); 674 } 675 676 struct pmc_info { 677 unsigned long uhp_udp_mask; 678 }; 679 680 static const struct pmc_info pmc_infos[] __initconst = { 681 { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP }, 682 { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP }, 683 { .uhp_udp_mask = AT91SAM926x_PMC_UHP }, 684 { .uhp_udp_mask = 0 }, 685 }; 686 687 static const struct of_device_id atmel_pmc_ids[] __initconst = { 688 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] }, 689 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] }, 690 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] }, 691 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] }, 692 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] }, 693 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] }, 694 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] }, 695 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] }, 696 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] }, 697 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, 698 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, 699 { /* sentinel */ }, 700 }; 701 702 static void __init at91_pm_init(void (*pm_idle)(void)) 703 { 704 struct device_node *pmc_np; 705 const struct of_device_id *of_id; 706 const struct pmc_info *pmc; 707 708 if (at91_cpuidle_device.dev.platform_data) 709 platform_device_register(&at91_cpuidle_device); 710 711 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id); 712 pm_data.pmc = of_iomap(pmc_np, 0); 713 if (!pm_data.pmc) { 714 pr_err("AT91: PM not supported, PMC not found\n"); 715 return; 716 } 717 718 pmc = of_id->data; 719 pm_data.uhp_udp_mask = pmc->uhp_udp_mask; 720 721 if (pm_idle) 722 arm_pm_idle = pm_idle; 723 724 at91_pm_sram_init(); 725 726 if (at91_suspend_sram_fn) { 727 suspend_set_ops(&at91_pm_ops); 728 pr_info("AT91: PM: standby: %s, suspend: %s\n", 729 pm_modes[pm_data.standby_mode].pattern, 730 pm_modes[pm_data.suspend_mode].pattern); 731 } else { 732 pr_info("AT91: PM not supported, due to no SRAM allocated\n"); 733 } 734 } 735 736 void __init at91rm9200_pm_init(void) 737 { 738 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200)) 739 return; 740 741 at91_dt_ramc(); 742 743 /* 744 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. 745 */ 746 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); 747 748 at91_pm_init(at91rm9200_idle); 749 } 750 751 void __init at91sam9_pm_init(void) 752 { 753 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9)) 754 return; 755 756 at91_dt_ramc(); 757 at91_pm_init(at91sam9_idle); 758 } 759 760 void __init sama5_pm_init(void) 761 { 762 if (!IS_ENABLED(CONFIG_SOC_SAMA5)) 763 return; 764 765 at91_dt_ramc(); 766 at91_pm_init(NULL); 767 } 768 769 void __init sama5d2_pm_init(void) 770 { 771 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) 772 return; 773 774 at91_pm_modes_init(); 775 sama5_pm_init(); 776 } 777 778 static int __init at91_pm_modes_select(char *str) 779 { 780 char *s; 781 substring_t args[MAX_OPT_ARGS]; 782 int standby, suspend; 783 784 if (!str) 785 return 0; 786 787 s = strsep(&str, ","); 788 standby = match_token(s, pm_modes, args); 789 if (standby < 0) 790 return 0; 791 792 suspend = match_token(str, pm_modes, args); 793 if (suspend < 0) 794 return 0; 795 796 pm_data.standby_mode = standby; 797 pm_data.suspend_mode = suspend; 798 799 return 0; 800 } 801 early_param("atmel.pm_modes", at91_pm_modes_select); 802