xref: /openbmc/linux/arch/arm/mach-at91/pm.c (revision c4f7ac64)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * arch/arm/mach-at91/pm.c
4  * AT91 Power Management
5  *
6  * Copyright (C) 2005 David Brownell
7  */
8 
9 #include <linux/genalloc.h>
10 #include <linux/io.h>
11 #include <linux/of_address.h>
12 #include <linux/of.h>
13 #include <linux/of_platform.h>
14 #include <linux/parser.h>
15 #include <linux/suspend.h>
16 
17 #include <linux/clk/at91_pmc.h>
18 #include <linux/platform_data/atmel.h>
19 
20 #include <soc/at91/pm.h>
21 
22 #include <asm/cacheflush.h>
23 #include <asm/fncpy.h>
24 #include <asm/system_misc.h>
25 #include <asm/suspend.h>
26 
27 #include "generic.h"
28 #include "pm.h"
29 
30 struct at91_soc_pm {
31 	int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
32 	int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
33 	const struct of_device_id *ws_ids;
34 	struct at91_pm_data data;
35 };
36 
37 static struct at91_soc_pm soc_pm = {
38 	.data = {
39 		.standby_mode = AT91_PM_STANDBY,
40 		.suspend_mode = AT91_PM_ULP0,
41 	},
42 };
43 
44 static const match_table_t pm_modes __initconst = {
45 	{ AT91_PM_STANDBY,	"standby" },
46 	{ AT91_PM_ULP0,		"ulp0" },
47 	{ AT91_PM_ULP0_FAST,    "ulp0-fast" },
48 	{ AT91_PM_ULP1,		"ulp1" },
49 	{ AT91_PM_BACKUP,	"backup" },
50 	{ -1, NULL },
51 };
52 
53 #define at91_ramc_read(id, field) \
54 	__raw_readl(soc_pm.data.ramc[id] + field)
55 
56 #define at91_ramc_write(id, field, value) \
57 	__raw_writel(value, soc_pm.data.ramc[id] + field)
58 
59 static int at91_pm_valid_state(suspend_state_t state)
60 {
61 	switch (state) {
62 		case PM_SUSPEND_ON:
63 		case PM_SUSPEND_STANDBY:
64 		case PM_SUSPEND_MEM:
65 			return 1;
66 
67 		default:
68 			return 0;
69 	}
70 }
71 
72 static int canary = 0xA5A5A5A5;
73 
74 static struct at91_pm_bu {
75 	int suspended;
76 	unsigned long reserved;
77 	phys_addr_t canary;
78 	phys_addr_t resume;
79 } *pm_bu;
80 
81 struct wakeup_source_info {
82 	unsigned int pmc_fsmr_bit;
83 	unsigned int shdwc_mr_bit;
84 	bool set_polarity;
85 };
86 
87 static const struct wakeup_source_info ws_info[] = {
88 	{ .pmc_fsmr_bit = AT91_PMC_FSTT(10),	.set_polarity = true },
89 	{ .pmc_fsmr_bit = AT91_PMC_RTCAL,	.shdwc_mr_bit = BIT(17) },
90 	{ .pmc_fsmr_bit = AT91_PMC_USBAL },
91 	{ .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
92 	{ .pmc_fsmr_bit = AT91_PMC_RTTAL },
93 	{ .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
94 };
95 
96 static const struct of_device_id sama5d2_ws_ids[] = {
97 	{ .compatible = "atmel,sama5d2-gem",		.data = &ws_info[0] },
98 	{ .compatible = "atmel,at91rm9200-rtc",		.data = &ws_info[1] },
99 	{ .compatible = "atmel,sama5d3-udc",		.data = &ws_info[2] },
100 	{ .compatible = "atmel,at91rm9200-ohci",	.data = &ws_info[2] },
101 	{ .compatible = "usb-ohci",			.data = &ws_info[2] },
102 	{ .compatible = "atmel,at91sam9g45-ehci",	.data = &ws_info[2] },
103 	{ .compatible = "usb-ehci",			.data = &ws_info[2] },
104 	{ .compatible = "atmel,sama5d2-sdhci",		.data = &ws_info[3] },
105 	{ /* sentinel */ }
106 };
107 
108 static const struct of_device_id sam9x60_ws_ids[] = {
109 	{ .compatible = "atmel,at91sam9x5-rtc",		.data = &ws_info[1] },
110 	{ .compatible = "atmel,at91rm9200-ohci",	.data = &ws_info[2] },
111 	{ .compatible = "usb-ohci",			.data = &ws_info[2] },
112 	{ .compatible = "atmel,at91sam9g45-ehci",	.data = &ws_info[2] },
113 	{ .compatible = "usb-ehci",			.data = &ws_info[2] },
114 	{ .compatible = "atmel,at91sam9260-rtt",	.data = &ws_info[4] },
115 	{ .compatible = "cdns,sam9x60-macb",		.data = &ws_info[5] },
116 	{ /* sentinel */ }
117 };
118 
119 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
120 {
121 	const struct wakeup_source_info *wsi;
122 	const struct of_device_id *match;
123 	struct platform_device *pdev;
124 	struct device_node *np;
125 	unsigned int mode = 0, polarity = 0, val = 0;
126 
127 	if (pm_mode != AT91_PM_ULP1)
128 		return 0;
129 
130 	if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
131 		return -EPERM;
132 
133 	if (!set) {
134 		writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
135 		return 0;
136 	}
137 
138 	if (soc_pm.config_shdwc_ws)
139 		soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
140 
141 	/* SHDWC.MR */
142 	val = readl(soc_pm.data.shdwc + 0x04);
143 
144 	/* Loop through defined wakeup sources. */
145 	for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
146 		pdev = of_find_device_by_node(np);
147 		if (!pdev)
148 			continue;
149 
150 		if (device_may_wakeup(&pdev->dev)) {
151 			wsi = match->data;
152 
153 			/* Check if enabled on SHDWC. */
154 			if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
155 				goto put_device;
156 
157 			mode |= wsi->pmc_fsmr_bit;
158 			if (wsi->set_polarity)
159 				polarity |= wsi->pmc_fsmr_bit;
160 		}
161 
162 put_device:
163 		put_device(&pdev->dev);
164 	}
165 
166 	if (mode) {
167 		if (soc_pm.config_pmc_ws)
168 			soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
169 	} else {
170 		pr_err("AT91: PM: no ULP1 wakeup sources found!");
171 	}
172 
173 	return mode ? 0 : -EPERM;
174 }
175 
176 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
177 					u32 *polarity)
178 {
179 	u32 val;
180 
181 	/* SHDWC.WUIR */
182 	val = readl(shdwc + 0x0c);
183 	*mode |= (val & 0x3ff);
184 	*polarity |= ((val >> 16) & 0x3ff);
185 
186 	return 0;
187 }
188 
189 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
190 {
191 	writel(mode, pmc + AT91_PMC_FSMR);
192 	writel(polarity, pmc + AT91_PMC_FSPR);
193 
194 	return 0;
195 }
196 
197 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
198 {
199 	writel(mode, pmc + AT91_PMC_FSMR);
200 
201 	return 0;
202 }
203 
204 /*
205  * Called after processes are frozen, but before we shutdown devices.
206  */
207 static int at91_pm_begin(suspend_state_t state)
208 {
209 	switch (state) {
210 	case PM_SUSPEND_MEM:
211 		soc_pm.data.mode = soc_pm.data.suspend_mode;
212 		break;
213 
214 	case PM_SUSPEND_STANDBY:
215 		soc_pm.data.mode = soc_pm.data.standby_mode;
216 		break;
217 
218 	default:
219 		soc_pm.data.mode = -1;
220 	}
221 
222 	return at91_pm_config_ws(soc_pm.data.mode, true);
223 }
224 
225 /*
226  * Verify that all the clocks are correct before entering
227  * slow-clock mode.
228  */
229 static int at91_pm_verify_clocks(void)
230 {
231 	unsigned long scsr;
232 	int i;
233 
234 	scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
235 
236 	/* USB must not be using PLLB */
237 	if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
238 		pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
239 		return 0;
240 	}
241 
242 	/* PCK0..PCK3 must be disabled, or configured to use clk32k */
243 	for (i = 0; i < 4; i++) {
244 		u32 css;
245 
246 		if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
247 			continue;
248 		css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
249 		if (css != AT91_PMC_CSS_SLOW) {
250 			pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
251 			return 0;
252 		}
253 	}
254 
255 	return 1;
256 }
257 
258 /*
259  * Call this from platform driver suspend() to see how deeply to suspend.
260  * For example, some controllers (like OHCI) need one of the PLL clocks
261  * in order to act as a wakeup source, and those are not available when
262  * going into slow clock mode.
263  *
264  * REVISIT: generalize as clk_will_be_available(clk)?  Other platforms have
265  * the very same problem (but not using at91 main_clk), and it'd be better
266  * to add one generic API rather than lots of platform-specific ones.
267  */
268 int at91_suspend_entering_slow_clock(void)
269 {
270 	return (soc_pm.data.mode >= AT91_PM_ULP0);
271 }
272 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
273 
274 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
275 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
276 extern u32 at91_pm_suspend_in_sram_sz;
277 
278 static int at91_suspend_finish(unsigned long val)
279 {
280 	flush_cache_all();
281 	outer_disable();
282 
283 	at91_suspend_sram_fn(&soc_pm.data);
284 
285 	return 0;
286 }
287 
288 static void at91_pm_suspend(suspend_state_t state)
289 {
290 	if (soc_pm.data.mode == AT91_PM_BACKUP) {
291 		pm_bu->suspended = 1;
292 
293 		cpu_suspend(0, at91_suspend_finish);
294 
295 		/* The SRAM is lost between suspend cycles */
296 		at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
297 					     &at91_pm_suspend_in_sram,
298 					     at91_pm_suspend_in_sram_sz);
299 	} else {
300 		at91_suspend_finish(0);
301 	}
302 
303 	outer_resume();
304 }
305 
306 /*
307  * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
308  * event sources; and reduces DRAM power.  But otherwise it's identical to
309  * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
310  *
311  * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
312  * suspend more deeply, the master clock switches to the clk32k and turns off
313  * the main oscillator
314  *
315  * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
316  */
317 static int at91_pm_enter(suspend_state_t state)
318 {
319 #ifdef CONFIG_PINCTRL_AT91
320 	/*
321 	 * FIXME: this is needed to communicate between the pinctrl driver and
322 	 * the PM implementation in the machine. Possibly part of the PM
323 	 * implementation should be moved down into the pinctrl driver and get
324 	 * called as part of the generic suspend/resume path.
325 	 */
326 	at91_pinctrl_gpio_suspend();
327 #endif
328 
329 	switch (state) {
330 	case PM_SUSPEND_MEM:
331 	case PM_SUSPEND_STANDBY:
332 		/*
333 		 * Ensure that clocks are in a valid state.
334 		 */
335 		if (soc_pm.data.mode >= AT91_PM_ULP0 &&
336 		    !at91_pm_verify_clocks())
337 			goto error;
338 
339 		at91_pm_suspend(state);
340 
341 		break;
342 
343 	case PM_SUSPEND_ON:
344 		cpu_do_idle();
345 		break;
346 
347 	default:
348 		pr_debug("AT91: PM - bogus suspend state %d\n", state);
349 		goto error;
350 	}
351 
352 error:
353 #ifdef CONFIG_PINCTRL_AT91
354 	at91_pinctrl_gpio_resume();
355 #endif
356 	return 0;
357 }
358 
359 /*
360  * Called right prior to thawing processes.
361  */
362 static void at91_pm_end(void)
363 {
364 	at91_pm_config_ws(soc_pm.data.mode, false);
365 }
366 
367 
368 static const struct platform_suspend_ops at91_pm_ops = {
369 	.valid	= at91_pm_valid_state,
370 	.begin	= at91_pm_begin,
371 	.enter	= at91_pm_enter,
372 	.end	= at91_pm_end,
373 };
374 
375 static struct platform_device at91_cpuidle_device = {
376 	.name = "cpuidle-at91",
377 };
378 
379 /*
380  * The AT91RM9200 goes into self-refresh mode with this command, and will
381  * terminate self-refresh automatically on the next SDRAM access.
382  *
383  * Self-refresh mode is exited as soon as a memory access is made, but we don't
384  * know for sure when that happens. However, we need to restore the low-power
385  * mode if it was enabled before going idle. Restoring low-power mode while
386  * still in self-refresh is "not recommended", but seems to work.
387  */
388 static void at91rm9200_standby(void)
389 {
390 	asm volatile(
391 		"b    1f\n\t"
392 		".align    5\n\t"
393 		"1:  mcr    p15, 0, %0, c7, c10, 4\n\t"
394 		"    str    %2, [%1, %3]\n\t"
395 		"    mcr    p15, 0, %0, c7, c0, 4\n\t"
396 		:
397 		: "r" (0), "r" (soc_pm.data.ramc[0]),
398 		  "r" (1), "r" (AT91_MC_SDRAMC_SRR));
399 }
400 
401 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
402  * remember.
403  */
404 static void at91_ddr_standby(void)
405 {
406 	/* Those two values allow us to delay self-refresh activation
407 	 * to the maximum. */
408 	u32 lpr0, lpr1 = 0;
409 	u32 mdr, saved_mdr0, saved_mdr1 = 0;
410 	u32 saved_lpr0, saved_lpr1 = 0;
411 
412 	/* LPDDR1 --> force DDR2 mode during self-refresh */
413 	saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
414 	if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
415 		mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
416 		mdr |= AT91_DDRSDRC_MD_DDR2;
417 		at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
418 	}
419 
420 	if (soc_pm.data.ramc[1]) {
421 		saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
422 		lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
423 		lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
424 		saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
425 		if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
426 			mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
427 			mdr |= AT91_DDRSDRC_MD_DDR2;
428 			at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
429 		}
430 	}
431 
432 	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
433 	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
434 	lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
435 
436 	/* self-refresh mode now */
437 	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
438 	if (soc_pm.data.ramc[1])
439 		at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
440 
441 	cpu_do_idle();
442 
443 	at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
444 	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
445 	if (soc_pm.data.ramc[1]) {
446 		at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
447 		at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
448 	}
449 }
450 
451 static void sama5d3_ddr_standby(void)
452 {
453 	u32 lpr0;
454 	u32 saved_lpr0;
455 
456 	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
457 	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
458 	lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
459 
460 	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
461 
462 	cpu_do_idle();
463 
464 	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
465 }
466 
467 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
468  * remember.
469  */
470 static void at91sam9_sdram_standby(void)
471 {
472 	u32 lpr0, lpr1 = 0;
473 	u32 saved_lpr0, saved_lpr1 = 0;
474 
475 	if (soc_pm.data.ramc[1]) {
476 		saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
477 		lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
478 		lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
479 	}
480 
481 	saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
482 	lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
483 	lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
484 
485 	/* self-refresh mode now */
486 	at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
487 	if (soc_pm.data.ramc[1])
488 		at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
489 
490 	cpu_do_idle();
491 
492 	at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
493 	if (soc_pm.data.ramc[1])
494 		at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
495 }
496 
497 struct ramc_info {
498 	void (*idle)(void);
499 	unsigned int memctrl;
500 };
501 
502 static const struct ramc_info ramc_infos[] __initconst = {
503 	{ .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
504 	{ .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
505 	{ .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
506 	{ .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
507 };
508 
509 static const struct of_device_id ramc_ids[] __initconst = {
510 	{ .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
511 	{ .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
512 	{ .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
513 	{ .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
514 	{ /*sentinel*/ }
515 };
516 
517 static __init void at91_dt_ramc(void)
518 {
519 	struct device_node *np;
520 	const struct of_device_id *of_id;
521 	int idx = 0;
522 	void *standby = NULL;
523 	const struct ramc_info *ramc;
524 
525 	for_each_matching_node_and_match(np, ramc_ids, &of_id) {
526 		soc_pm.data.ramc[idx] = of_iomap(np, 0);
527 		if (!soc_pm.data.ramc[idx])
528 			panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
529 
530 		ramc = of_id->data;
531 		if (!standby)
532 			standby = ramc->idle;
533 		soc_pm.data.memctrl = ramc->memctrl;
534 
535 		idx++;
536 	}
537 
538 	if (!idx)
539 		panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
540 
541 	if (!standby) {
542 		pr_warn("ramc no standby function available\n");
543 		return;
544 	}
545 
546 	at91_cpuidle_device.dev.platform_data = standby;
547 }
548 
549 static void at91rm9200_idle(void)
550 {
551 	/*
552 	 * Disable the processor clock.  The processor will be automatically
553 	 * re-enabled by an interrupt or by a reset.
554 	 */
555 	writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
556 }
557 
558 static void at91sam9_idle(void)
559 {
560 	writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
561 	cpu_do_idle();
562 }
563 
564 static void __init at91_pm_sram_init(void)
565 {
566 	struct gen_pool *sram_pool;
567 	phys_addr_t sram_pbase;
568 	unsigned long sram_base;
569 	struct device_node *node;
570 	struct platform_device *pdev = NULL;
571 
572 	for_each_compatible_node(node, NULL, "mmio-sram") {
573 		pdev = of_find_device_by_node(node);
574 		if (pdev) {
575 			of_node_put(node);
576 			break;
577 		}
578 	}
579 
580 	if (!pdev) {
581 		pr_warn("%s: failed to find sram device!\n", __func__);
582 		return;
583 	}
584 
585 	sram_pool = gen_pool_get(&pdev->dev, NULL);
586 	if (!sram_pool) {
587 		pr_warn("%s: sram pool unavailable!\n", __func__);
588 		goto out_put_device;
589 	}
590 
591 	sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
592 	if (!sram_base) {
593 		pr_warn("%s: unable to alloc sram!\n", __func__);
594 		goto out_put_device;
595 	}
596 
597 	sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
598 	at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
599 					at91_pm_suspend_in_sram_sz, false);
600 	if (!at91_suspend_sram_fn) {
601 		pr_warn("SRAM: Could not map\n");
602 		goto out_put_device;
603 	}
604 
605 	/* Copy the pm suspend handler to SRAM */
606 	at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
607 			&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
608 	return;
609 
610 out_put_device:
611 	put_device(&pdev->dev);
612 	return;
613 }
614 
615 static bool __init at91_is_pm_mode_active(int pm_mode)
616 {
617 	return (soc_pm.data.standby_mode == pm_mode ||
618 		soc_pm.data.suspend_mode == pm_mode);
619 }
620 
621 static int __init at91_pm_backup_init(void)
622 {
623 	struct gen_pool *sram_pool;
624 	struct device_node *np;
625 	struct platform_device *pdev = NULL;
626 	int ret = -ENODEV;
627 
628 	if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
629 		return -EPERM;
630 
631 	if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
632 		return 0;
633 
634 	np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
635 	if (!np) {
636 		pr_warn("%s: failed to find sfrbu!\n", __func__);
637 		return ret;
638 	}
639 
640 	soc_pm.data.sfrbu = of_iomap(np, 0);
641 	of_node_put(np);
642 
643 	np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
644 	if (!np)
645 		goto securam_fail_no_ref_dev;
646 
647 	pdev = of_find_device_by_node(np);
648 	of_node_put(np);
649 	if (!pdev) {
650 		pr_warn("%s: failed to find securam device!\n", __func__);
651 		goto securam_fail_no_ref_dev;
652 	}
653 
654 	sram_pool = gen_pool_get(&pdev->dev, NULL);
655 	if (!sram_pool) {
656 		pr_warn("%s: securam pool unavailable!\n", __func__);
657 		goto securam_fail;
658 	}
659 
660 	pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
661 	if (!pm_bu) {
662 		pr_warn("%s: unable to alloc securam!\n", __func__);
663 		ret = -ENOMEM;
664 		goto securam_fail;
665 	}
666 
667 	pm_bu->suspended = 0;
668 	pm_bu->canary = __pa_symbol(&canary);
669 	pm_bu->resume = __pa_symbol(cpu_resume);
670 
671 	return 0;
672 
673 securam_fail:
674 	put_device(&pdev->dev);
675 securam_fail_no_ref_dev:
676 	iounmap(soc_pm.data.sfrbu);
677 	soc_pm.data.sfrbu = NULL;
678 	return ret;
679 }
680 
681 static void __init at91_pm_use_default_mode(int pm_mode)
682 {
683 	if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP)
684 		return;
685 
686 	if (soc_pm.data.standby_mode == pm_mode)
687 		soc_pm.data.standby_mode = AT91_PM_ULP0;
688 	if (soc_pm.data.suspend_mode == pm_mode)
689 		soc_pm.data.suspend_mode = AT91_PM_ULP0;
690 }
691 
692 static const struct of_device_id atmel_shdwc_ids[] = {
693 	{ .compatible = "atmel,sama5d2-shdwc" },
694 	{ .compatible = "microchip,sam9x60-shdwc" },
695 	{ /* sentinel. */ }
696 };
697 
698 static void __init at91_pm_modes_init(void)
699 {
700 	struct device_node *np;
701 	int ret;
702 
703 	if (!at91_is_pm_mode_active(AT91_PM_BACKUP) &&
704 	    !at91_is_pm_mode_active(AT91_PM_ULP1))
705 		return;
706 
707 	np = of_find_matching_node(NULL, atmel_shdwc_ids);
708 	if (!np) {
709 		pr_warn("%s: failed to find shdwc!\n", __func__);
710 		goto ulp1_default;
711 	}
712 
713 	soc_pm.data.shdwc = of_iomap(np, 0);
714 	of_node_put(np);
715 
716 	ret = at91_pm_backup_init();
717 	if (ret) {
718 		if (!at91_is_pm_mode_active(AT91_PM_ULP1))
719 			goto unmap;
720 		else
721 			goto backup_default;
722 	}
723 
724 	return;
725 
726 unmap:
727 	iounmap(soc_pm.data.shdwc);
728 	soc_pm.data.shdwc = NULL;
729 ulp1_default:
730 	at91_pm_use_default_mode(AT91_PM_ULP1);
731 backup_default:
732 	at91_pm_use_default_mode(AT91_PM_BACKUP);
733 }
734 
735 struct pmc_info {
736 	unsigned long uhp_udp_mask;
737 	unsigned long mckr;
738 	unsigned long version;
739 };
740 
741 static const struct pmc_info pmc_infos[] __initconst = {
742 	{
743 		.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
744 		.mckr = 0x30,
745 		.version = AT91_PMC_V1,
746 	},
747 
748 	{
749 		.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
750 		.mckr = 0x30,
751 		.version = AT91_PMC_V1,
752 	},
753 	{
754 		.uhp_udp_mask = AT91SAM926x_PMC_UHP,
755 		.mckr = 0x30,
756 		.version = AT91_PMC_V1,
757 	},
758 	{	.uhp_udp_mask = 0,
759 		.mckr = 0x30,
760 		.version = AT91_PMC_V1,
761 	},
762 	{
763 		.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
764 		.mckr = 0x28,
765 		.version = AT91_PMC_V2,
766 	},
767 };
768 
769 static const struct of_device_id atmel_pmc_ids[] __initconst = {
770 	{ .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
771 	{ .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
772 	{ .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
773 	{ .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
774 	{ .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
775 	{ .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
776 	{ .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
777 	{ .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
778 	{ .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
779 	{ .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
780 	{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
781 	{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
782 	{ /* sentinel */ },
783 };
784 
785 static void __init at91_pm_modes_validate(const int *modes, int len)
786 {
787 	u8 i, standby = 0, suspend = 0;
788 	int mode;
789 
790 	for (i = 0; i < len; i++) {
791 		if (standby && suspend)
792 			break;
793 
794 		if (modes[i] == soc_pm.data.standby_mode && !standby) {
795 			standby = 1;
796 			continue;
797 		}
798 
799 		if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
800 			suspend = 1;
801 			continue;
802 		}
803 	}
804 
805 	if (!standby) {
806 		if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
807 			mode = AT91_PM_ULP0;
808 		else
809 			mode = AT91_PM_STANDBY;
810 
811 		pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
812 			pm_modes[soc_pm.data.standby_mode].pattern,
813 			pm_modes[mode].pattern);
814 		soc_pm.data.standby_mode = mode;
815 	}
816 
817 	if (!suspend) {
818 		if (soc_pm.data.standby_mode == AT91_PM_ULP0)
819 			mode = AT91_PM_STANDBY;
820 		else
821 			mode = AT91_PM_ULP0;
822 
823 		pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
824 			pm_modes[soc_pm.data.suspend_mode].pattern,
825 			pm_modes[mode].pattern);
826 		soc_pm.data.suspend_mode = mode;
827 	}
828 }
829 
830 static void __init at91_pm_init(void (*pm_idle)(void))
831 {
832 	struct device_node *pmc_np;
833 	const struct of_device_id *of_id;
834 	const struct pmc_info *pmc;
835 
836 	if (at91_cpuidle_device.dev.platform_data)
837 		platform_device_register(&at91_cpuidle_device);
838 
839 	pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
840 	soc_pm.data.pmc = of_iomap(pmc_np, 0);
841 	of_node_put(pmc_np);
842 	if (!soc_pm.data.pmc) {
843 		pr_err("AT91: PM not supported, PMC not found\n");
844 		return;
845 	}
846 
847 	pmc = of_id->data;
848 	soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
849 	soc_pm.data.pmc_mckr_offset = pmc->mckr;
850 	soc_pm.data.pmc_version = pmc->version;
851 
852 	if (pm_idle)
853 		arm_pm_idle = pm_idle;
854 
855 	at91_pm_sram_init();
856 
857 	if (at91_suspend_sram_fn) {
858 		suspend_set_ops(&at91_pm_ops);
859 		pr_info("AT91: PM: standby: %s, suspend: %s\n",
860 			pm_modes[soc_pm.data.standby_mode].pattern,
861 			pm_modes[soc_pm.data.suspend_mode].pattern);
862 	} else {
863 		pr_info("AT91: PM not supported, due to no SRAM allocated\n");
864 	}
865 }
866 
867 void __init at91rm9200_pm_init(void)
868 {
869 	if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
870 		return;
871 
872 	/*
873 	 * Force STANDBY and ULP0 mode to avoid calling
874 	 * at91_pm_modes_validate() which may increase booting time.
875 	 * Platform supports anyway only STANDBY and ULP0 modes.
876 	 */
877 	soc_pm.data.standby_mode = AT91_PM_STANDBY;
878 	soc_pm.data.suspend_mode = AT91_PM_ULP0;
879 
880 	at91_dt_ramc();
881 
882 	/*
883 	 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
884 	 */
885 	at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
886 
887 	at91_pm_init(at91rm9200_idle);
888 }
889 
890 void __init sam9x60_pm_init(void)
891 {
892 	static const int modes[] __initconst = {
893 		AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
894 	};
895 
896 	if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
897 		return;
898 
899 	at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
900 	at91_pm_modes_init();
901 	at91_dt_ramc();
902 	at91_pm_init(NULL);
903 
904 	soc_pm.ws_ids = sam9x60_ws_ids;
905 	soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
906 }
907 
908 void __init at91sam9_pm_init(void)
909 {
910 	if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
911 		return;
912 
913 	/*
914 	 * Force STANDBY and ULP0 mode to avoid calling
915 	 * at91_pm_modes_validate() which may increase booting time.
916 	 * Platform supports anyway only STANDBY and ULP0 modes.
917 	 */
918 	soc_pm.data.standby_mode = AT91_PM_STANDBY;
919 	soc_pm.data.suspend_mode = AT91_PM_ULP0;
920 
921 	at91_dt_ramc();
922 	at91_pm_init(at91sam9_idle);
923 }
924 
925 void __init sama5_pm_init(void)
926 {
927 	static const int modes[] __initconst = {
928 		AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
929 	};
930 
931 	if (!IS_ENABLED(CONFIG_SOC_SAMA5))
932 		return;
933 
934 	at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
935 	at91_dt_ramc();
936 	at91_pm_init(NULL);
937 }
938 
939 void __init sama5d2_pm_init(void)
940 {
941 	static const int modes[] __initconst = {
942 		AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
943 		AT91_PM_BACKUP,
944 	};
945 
946 	if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
947 		return;
948 
949 	at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
950 	at91_pm_modes_init();
951 	at91_dt_ramc();
952 	at91_pm_init(NULL);
953 
954 	soc_pm.ws_ids = sama5d2_ws_ids;
955 	soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
956 	soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
957 }
958 
959 static int __init at91_pm_modes_select(char *str)
960 {
961 	char *s;
962 	substring_t args[MAX_OPT_ARGS];
963 	int standby, suspend;
964 
965 	if (!str)
966 		return 0;
967 
968 	s = strsep(&str, ",");
969 	standby = match_token(s, pm_modes, args);
970 	if (standby < 0)
971 		return 0;
972 
973 	suspend = match_token(str, pm_modes, args);
974 	if (suspend < 0)
975 		return 0;
976 
977 	soc_pm.data.standby_mode = standby;
978 	soc_pm.data.suspend_mode = suspend;
979 
980 	return 0;
981 }
982 early_param("atmel.pm_modes", at91_pm_modes_select);
983