1 /* 2 * arch/arm/mach-at91/pm.c 3 * AT91 Power Management 4 * 5 * Copyright (C) 2005 David Brownell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13 #include <linux/gpio.h> 14 #include <linux/suspend.h> 15 #include <linux/sched.h> 16 #include <linux/proc_fs.h> 17 #include <linux/genalloc.h> 18 #include <linux/interrupt.h> 19 #include <linux/sysfs.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <linux/of_address.h> 24 #include <linux/platform_device.h> 25 #include <linux/platform_data/atmel.h> 26 #include <linux/io.h> 27 #include <linux/clk/at91_pmc.h> 28 29 #include <asm/irq.h> 30 #include <linux/atomic.h> 31 #include <asm/mach/time.h> 32 #include <asm/mach/irq.h> 33 #include <asm/fncpy.h> 34 #include <asm/cacheflush.h> 35 #include <asm/system_misc.h> 36 37 #include "generic.h" 38 #include "pm.h" 39 40 static void __iomem *pmc; 41 42 /* 43 * FIXME: this is needed to communicate between the pinctrl driver and 44 * the PM implementation in the machine. Possibly part of the PM 45 * implementation should be moved down into the pinctrl driver and get 46 * called as part of the generic suspend/resume path. 47 */ 48 #ifdef CONFIG_PINCTRL_AT91 49 extern void at91_pinctrl_gpio_suspend(void); 50 extern void at91_pinctrl_gpio_resume(void); 51 #endif 52 53 static struct { 54 unsigned long uhp_udp_mask; 55 int memctrl; 56 } at91_pm_data; 57 58 static void __iomem *at91_ramc_base[2]; 59 60 static int at91_pm_valid_state(suspend_state_t state) 61 { 62 switch (state) { 63 case PM_SUSPEND_ON: 64 case PM_SUSPEND_STANDBY: 65 case PM_SUSPEND_MEM: 66 return 1; 67 68 default: 69 return 0; 70 } 71 } 72 73 74 static suspend_state_t target_state; 75 76 /* 77 * Called after processes are frozen, but before we shutdown devices. 78 */ 79 static int at91_pm_begin(suspend_state_t state) 80 { 81 target_state = state; 82 return 0; 83 } 84 85 /* 86 * Verify that all the clocks are correct before entering 87 * slow-clock mode. 88 */ 89 static int at91_pm_verify_clocks(void) 90 { 91 unsigned long scsr; 92 int i; 93 94 scsr = readl(pmc + AT91_PMC_SCSR); 95 96 /* USB must not be using PLLB */ 97 if ((scsr & at91_pm_data.uhp_udp_mask) != 0) { 98 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 99 return 0; 100 } 101 102 /* PCK0..PCK3 must be disabled, or configured to use clk32k */ 103 for (i = 0; i < 4; i++) { 104 u32 css; 105 106 if ((scsr & (AT91_PMC_PCK0 << i)) == 0) 107 continue; 108 css = readl(pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; 109 if (css != AT91_PMC_CSS_SLOW) { 110 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); 111 return 0; 112 } 113 } 114 115 return 1; 116 } 117 118 /* 119 * Call this from platform driver suspend() to see how deeply to suspend. 120 * For example, some controllers (like OHCI) need one of the PLL clocks 121 * in order to act as a wakeup source, and those are not available when 122 * going into slow clock mode. 123 * 124 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have 125 * the very same problem (but not using at91 main_clk), and it'd be better 126 * to add one generic API rather than lots of platform-specific ones. 127 */ 128 int at91_suspend_entering_slow_clock(void) 129 { 130 return (target_state == PM_SUSPEND_MEM); 131 } 132 EXPORT_SYMBOL(at91_suspend_entering_slow_clock); 133 134 static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0, 135 void __iomem *ramc1, int memctrl); 136 137 extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0, 138 void __iomem *ramc1, int memctrl); 139 extern u32 at91_pm_suspend_in_sram_sz; 140 141 static void at91_pm_suspend(suspend_state_t state) 142 { 143 unsigned int pm_data = at91_pm_data.memctrl; 144 145 pm_data |= (state == PM_SUSPEND_MEM) ? 146 AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0; 147 148 flush_cache_all(); 149 outer_disable(); 150 151 at91_suspend_sram_fn(pmc, at91_ramc_base[0], 152 at91_ramc_base[1], pm_data); 153 154 outer_resume(); 155 } 156 157 static int at91_pm_enter(suspend_state_t state) 158 { 159 #ifdef CONFIG_PINCTRL_AT91 160 at91_pinctrl_gpio_suspend(); 161 #endif 162 switch (state) { 163 /* 164 * Suspend-to-RAM is like STANDBY plus slow clock mode, so 165 * drivers must suspend more deeply, the master clock switches 166 * to the clk32k and turns off the main oscillator 167 */ 168 case PM_SUSPEND_MEM: 169 /* 170 * Ensure that clocks are in a valid state. 171 */ 172 if (!at91_pm_verify_clocks()) 173 goto error; 174 175 at91_pm_suspend(state); 176 177 break; 178 179 /* 180 * STANDBY mode has *all* drivers suspended; ignores irqs not 181 * marked as 'wakeup' event sources; and reduces DRAM power. 182 * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and 183 * nothing fancy done with main or cpu clocks. 184 */ 185 case PM_SUSPEND_STANDBY: 186 at91_pm_suspend(state); 187 break; 188 189 case PM_SUSPEND_ON: 190 cpu_do_idle(); 191 break; 192 193 default: 194 pr_debug("AT91: PM - bogus suspend state %d\n", state); 195 goto error; 196 } 197 198 error: 199 target_state = PM_SUSPEND_ON; 200 201 #ifdef CONFIG_PINCTRL_AT91 202 at91_pinctrl_gpio_resume(); 203 #endif 204 return 0; 205 } 206 207 /* 208 * Called right prior to thawing processes. 209 */ 210 static void at91_pm_end(void) 211 { 212 target_state = PM_SUSPEND_ON; 213 } 214 215 216 static const struct platform_suspend_ops at91_pm_ops = { 217 .valid = at91_pm_valid_state, 218 .begin = at91_pm_begin, 219 .enter = at91_pm_enter, 220 .end = at91_pm_end, 221 }; 222 223 static struct platform_device at91_cpuidle_device = { 224 .name = "cpuidle-at91", 225 }; 226 227 static void at91_pm_set_standby(void (*at91_standby)(void)) 228 { 229 if (at91_standby) 230 at91_cpuidle_device.dev.platform_data = at91_standby; 231 } 232 233 /* 234 * The AT91RM9200 goes into self-refresh mode with this command, and will 235 * terminate self-refresh automatically on the next SDRAM access. 236 * 237 * Self-refresh mode is exited as soon as a memory access is made, but we don't 238 * know for sure when that happens. However, we need to restore the low-power 239 * mode if it was enabled before going idle. Restoring low-power mode while 240 * still in self-refresh is "not recommended", but seems to work. 241 */ 242 static void at91rm9200_standby(void) 243 { 244 u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR); 245 246 asm volatile( 247 "b 1f\n\t" 248 ".align 5\n\t" 249 "1: mcr p15, 0, %0, c7, c10, 4\n\t" 250 " str %0, [%1, %2]\n\t" 251 " str %3, [%1, %4]\n\t" 252 " mcr p15, 0, %0, c7, c0, 4\n\t" 253 " str %5, [%1, %2]" 254 : 255 : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR), 256 "r" (1), "r" (AT91_MC_SDRAMC_SRR), 257 "r" (lpr)); 258 } 259 260 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 261 * remember. 262 */ 263 static void at91_ddr_standby(void) 264 { 265 /* Those two values allow us to delay self-refresh activation 266 * to the maximum. */ 267 u32 lpr0, lpr1 = 0; 268 u32 saved_lpr0, saved_lpr1 = 0; 269 270 if (at91_ramc_base[1]) { 271 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); 272 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; 273 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 274 } 275 276 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 277 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 278 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 279 280 /* self-refresh mode now */ 281 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 282 if (at91_ramc_base[1]) 283 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); 284 285 cpu_do_idle(); 286 287 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 288 if (at91_ramc_base[1]) 289 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); 290 } 291 292 static void sama5d3_ddr_standby(void) 293 { 294 u32 lpr0; 295 u32 saved_lpr0; 296 297 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 298 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 299 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN; 300 301 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 302 303 cpu_do_idle(); 304 305 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 306 } 307 308 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 309 * remember. 310 */ 311 static void at91sam9_sdram_standby(void) 312 { 313 u32 lpr0, lpr1 = 0; 314 u32 saved_lpr0, saved_lpr1 = 0; 315 316 if (at91_ramc_base[1]) { 317 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); 318 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; 319 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 320 } 321 322 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); 323 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; 324 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 325 326 /* self-refresh mode now */ 327 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); 328 if (at91_ramc_base[1]) 329 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); 330 331 cpu_do_idle(); 332 333 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); 334 if (at91_ramc_base[1]) 335 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); 336 } 337 338 static const struct of_device_id const ramc_ids[] __initconst = { 339 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby }, 340 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby }, 341 { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby }, 342 { .compatible = "atmel,sama5d3-ddramc", .data = sama5d3_ddr_standby }, 343 { /*sentinel*/ } 344 }; 345 346 static __init void at91_dt_ramc(void) 347 { 348 struct device_node *np; 349 const struct of_device_id *of_id; 350 int idx = 0; 351 const void *standby = NULL; 352 353 for_each_matching_node_and_match(np, ramc_ids, &of_id) { 354 at91_ramc_base[idx] = of_iomap(np, 0); 355 if (!at91_ramc_base[idx]) 356 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx); 357 358 if (!standby) 359 standby = of_id->data; 360 361 idx++; 362 } 363 364 if (!idx) 365 panic(pr_fmt("unable to find compatible ram controller node in dtb\n")); 366 367 if (!standby) { 368 pr_warn("ramc no standby function available\n"); 369 return; 370 } 371 372 at91_pm_set_standby(standby); 373 } 374 375 static void at91rm9200_idle(void) 376 { 377 /* 378 * Disable the processor clock. The processor will be automatically 379 * re-enabled by an interrupt or by a reset. 380 */ 381 writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR); 382 } 383 384 static void at91sam9_idle(void) 385 { 386 writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR); 387 cpu_do_idle(); 388 } 389 390 static void __init at91_pm_sram_init(void) 391 { 392 struct gen_pool *sram_pool; 393 phys_addr_t sram_pbase; 394 unsigned long sram_base; 395 struct device_node *node; 396 struct platform_device *pdev = NULL; 397 398 for_each_compatible_node(node, NULL, "mmio-sram") { 399 pdev = of_find_device_by_node(node); 400 if (pdev) { 401 of_node_put(node); 402 break; 403 } 404 } 405 406 if (!pdev) { 407 pr_warn("%s: failed to find sram device!\n", __func__); 408 return; 409 } 410 411 sram_pool = gen_pool_get(&pdev->dev, NULL); 412 if (!sram_pool) { 413 pr_warn("%s: sram pool unavailable!\n", __func__); 414 return; 415 } 416 417 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz); 418 if (!sram_base) { 419 pr_warn("%s: unable to alloc sram!\n", __func__); 420 return; 421 } 422 423 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); 424 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase, 425 at91_pm_suspend_in_sram_sz, false); 426 if (!at91_suspend_sram_fn) { 427 pr_warn("SRAM: Could not map\n"); 428 return; 429 } 430 431 /* Copy the pm suspend handler to SRAM */ 432 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 433 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); 434 } 435 436 static const struct of_device_id atmel_pmc_ids[] __initconst = { 437 { .compatible = "atmel,at91rm9200-pmc" }, 438 { .compatible = "atmel,at91sam9260-pmc" }, 439 { .compatible = "atmel,at91sam9g45-pmc" }, 440 { .compatible = "atmel,at91sam9n12-pmc" }, 441 { .compatible = "atmel,at91sam9x5-pmc" }, 442 { .compatible = "atmel,sama5d3-pmc" }, 443 { .compatible = "atmel,sama5d2-pmc" }, 444 { /* sentinel */ }, 445 }; 446 447 static void __init at91_pm_init(void (*pm_idle)(void)) 448 { 449 struct device_node *pmc_np; 450 451 if (at91_cpuidle_device.dev.platform_data) 452 platform_device_register(&at91_cpuidle_device); 453 454 pmc_np = of_find_matching_node(NULL, atmel_pmc_ids); 455 pmc = of_iomap(pmc_np, 0); 456 if (!pmc) { 457 pr_err("AT91: PM not supported, PMC not found\n"); 458 return; 459 } 460 461 if (pm_idle) 462 arm_pm_idle = pm_idle; 463 464 at91_pm_sram_init(); 465 466 if (at91_suspend_sram_fn) 467 suspend_set_ops(&at91_pm_ops); 468 else 469 pr_info("AT91: PM not supported, due to no SRAM allocated\n"); 470 } 471 472 void __init at91rm9200_pm_init(void) 473 { 474 at91_dt_ramc(); 475 476 /* 477 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. 478 */ 479 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); 480 481 at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP; 482 at91_pm_data.memctrl = AT91_MEMCTRL_MC; 483 484 at91_pm_init(at91rm9200_idle); 485 } 486 487 void __init at91sam9260_pm_init(void) 488 { 489 at91_dt_ramc(); 490 at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC; 491 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; 492 at91_pm_init(at91sam9_idle); 493 } 494 495 void __init at91sam9g45_pm_init(void) 496 { 497 at91_dt_ramc(); 498 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP; 499 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; 500 at91_pm_init(at91sam9_idle); 501 } 502 503 void __init at91sam9x5_pm_init(void) 504 { 505 at91_dt_ramc(); 506 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; 507 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; 508 at91_pm_init(at91sam9_idle); 509 } 510 511 void __init sama5_pm_init(void) 512 { 513 at91_dt_ramc(); 514 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; 515 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; 516 at91_pm_init(NULL); 517 } 518