1 /* 2 * arch/arm/mach-at91/pm.c 3 * AT91 Power Management 4 * 5 * Copyright (C) 2005 David Brownell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13 #include <linux/gpio.h> 14 #include <linux/suspend.h> 15 #include <linux/sched.h> 16 #include <linux/proc_fs.h> 17 #include <linux/genalloc.h> 18 #include <linux/interrupt.h> 19 #include <linux/sysfs.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <linux/of_address.h> 24 #include <linux/platform_device.h> 25 #include <linux/io.h> 26 #include <linux/clk/at91_pmc.h> 27 28 #include <asm/irq.h> 29 #include <linux/atomic.h> 30 #include <asm/mach/time.h> 31 #include <asm/mach/irq.h> 32 33 #include <mach/cpu.h> 34 #include <mach/hardware.h> 35 36 #include "generic.h" 37 #include "pm.h" 38 39 static struct { 40 unsigned long uhp_udp_mask; 41 int memctrl; 42 } at91_pm_data; 43 44 static void (*at91_pm_standby)(void); 45 void __iomem *at91_ramc_base[2]; 46 47 static int at91_pm_valid_state(suspend_state_t state) 48 { 49 switch (state) { 50 case PM_SUSPEND_ON: 51 case PM_SUSPEND_STANDBY: 52 case PM_SUSPEND_MEM: 53 return 1; 54 55 default: 56 return 0; 57 } 58 } 59 60 61 static suspend_state_t target_state; 62 63 /* 64 * Called after processes are frozen, but before we shutdown devices. 65 */ 66 static int at91_pm_begin(suspend_state_t state) 67 { 68 target_state = state; 69 return 0; 70 } 71 72 /* 73 * Verify that all the clocks are correct before entering 74 * slow-clock mode. 75 */ 76 static int at91_pm_verify_clocks(void) 77 { 78 unsigned long scsr; 79 int i; 80 81 scsr = at91_pmc_read(AT91_PMC_SCSR); 82 83 /* USB must not be using PLLB */ 84 if ((scsr & at91_pm_data.uhp_udp_mask) != 0) { 85 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 86 return 0; 87 } 88 89 /* PCK0..PCK3 must be disabled, or configured to use clk32k */ 90 for (i = 0; i < 4; i++) { 91 u32 css; 92 93 if ((scsr & (AT91_PMC_PCK0 << i)) == 0) 94 continue; 95 96 css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS; 97 if (css != AT91_PMC_CSS_SLOW) { 98 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); 99 return 0; 100 } 101 } 102 103 return 1; 104 } 105 106 /* 107 * Call this from platform driver suspend() to see how deeply to suspend. 108 * For example, some controllers (like OHCI) need one of the PLL clocks 109 * in order to act as a wakeup source, and those are not available when 110 * going into slow clock mode. 111 * 112 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have 113 * the very same problem (but not using at91 main_clk), and it'd be better 114 * to add one generic API rather than lots of platform-specific ones. 115 */ 116 int at91_suspend_entering_slow_clock(void) 117 { 118 return (target_state == PM_SUSPEND_MEM); 119 } 120 EXPORT_SYMBOL(at91_suspend_entering_slow_clock); 121 122 123 static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0, 124 void __iomem *ramc1, int memctrl); 125 126 #ifdef CONFIG_AT91_SLOW_CLOCK 127 extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0, 128 void __iomem *ramc1, int memctrl); 129 extern u32 at91_slow_clock_sz; 130 #endif 131 132 static int at91_pm_enter(suspend_state_t state) 133 { 134 at91_pinctrl_gpio_suspend(); 135 136 switch (state) { 137 /* 138 * Suspend-to-RAM is like STANDBY plus slow clock mode, so 139 * drivers must suspend more deeply: only the master clock 140 * controller may be using the main oscillator. 141 */ 142 case PM_SUSPEND_MEM: 143 /* 144 * Ensure that clocks are in a valid state. 145 */ 146 if (!at91_pm_verify_clocks()) 147 goto error; 148 149 /* 150 * Enter slow clock mode by switching over to clk32k and 151 * turning off the main oscillator; reverse on wakeup. 152 */ 153 if (slow_clock) { 154 #ifdef CONFIG_AT91_SLOW_CLOCK 155 /* copy slow_clock handler to SRAM, and call it */ 156 memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz); 157 #endif 158 slow_clock(at91_pmc_base, at91_ramc_base[0], 159 at91_ramc_base[1], 160 at91_pm_data.memctrl); 161 break; 162 } else { 163 pr_info("AT91: PM - no slow clock mode enabled ...\n"); 164 /* FALLTHROUGH leaving master clock alone */ 165 } 166 167 /* 168 * STANDBY mode has *all* drivers suspended; ignores irqs not 169 * marked as 'wakeup' event sources; and reduces DRAM power. 170 * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and 171 * nothing fancy done with main or cpu clocks. 172 */ 173 case PM_SUSPEND_STANDBY: 174 /* 175 * NOTE: the Wait-for-Interrupt instruction needs to be 176 * in icache so no SDRAM accesses are needed until the 177 * wakeup IRQ occurs and self-refresh is terminated. 178 * For ARM 926 based chips, this requirement is weaker 179 * as at91sam9 can access a RAM in self-refresh mode. 180 */ 181 if (at91_pm_standby) 182 at91_pm_standby(); 183 break; 184 185 case PM_SUSPEND_ON: 186 cpu_do_idle(); 187 break; 188 189 default: 190 pr_debug("AT91: PM - bogus suspend state %d\n", state); 191 goto error; 192 } 193 194 error: 195 target_state = PM_SUSPEND_ON; 196 197 at91_pinctrl_gpio_resume(); 198 return 0; 199 } 200 201 /* 202 * Called right prior to thawing processes. 203 */ 204 static void at91_pm_end(void) 205 { 206 target_state = PM_SUSPEND_ON; 207 } 208 209 210 static const struct platform_suspend_ops at91_pm_ops = { 211 .valid = at91_pm_valid_state, 212 .begin = at91_pm_begin, 213 .enter = at91_pm_enter, 214 .end = at91_pm_end, 215 }; 216 217 static struct platform_device at91_cpuidle_device = { 218 .name = "cpuidle-at91", 219 }; 220 221 void at91_pm_set_standby(void (*at91_standby)(void)) 222 { 223 if (at91_standby) { 224 at91_cpuidle_device.dev.platform_data = at91_standby; 225 at91_pm_standby = at91_standby; 226 } 227 } 228 229 static const struct of_device_id ramc_ids[] __initconst = { 230 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby }, 231 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby }, 232 { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby }, 233 { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby }, 234 { /*sentinel*/ } 235 }; 236 237 static __init void at91_dt_ramc(void) 238 { 239 struct device_node *np; 240 const struct of_device_id *of_id; 241 int idx = 0; 242 const void *standby = NULL; 243 244 for_each_matching_node_and_match(np, ramc_ids, &of_id) { 245 at91_ramc_base[idx] = of_iomap(np, 0); 246 if (!at91_ramc_base[idx]) 247 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx); 248 249 if (!standby) 250 standby = of_id->data; 251 252 idx++; 253 } 254 255 if (!idx) 256 panic(pr_fmt("unable to find compatible ram controller node in dtb\n")); 257 258 if (!standby) { 259 pr_warn("ramc no standby function available\n"); 260 return; 261 } 262 263 at91_pm_set_standby(standby); 264 } 265 266 #ifdef CONFIG_AT91_SLOW_CLOCK 267 static void __init at91_pm_sram_init(void) 268 { 269 struct gen_pool *sram_pool; 270 phys_addr_t sram_pbase; 271 unsigned long sram_base; 272 struct device_node *node; 273 struct platform_device *pdev = NULL; 274 275 for_each_compatible_node(node, NULL, "mmio-sram") { 276 pdev = of_find_device_by_node(node); 277 if (pdev) { 278 of_node_put(node); 279 break; 280 } 281 } 282 283 if (!pdev) { 284 pr_warn("%s: failed to find sram device!\n", __func__); 285 return; 286 } 287 288 sram_pool = dev_get_gen_pool(&pdev->dev); 289 if (!sram_pool) { 290 pr_warn("%s: sram pool unavailable!\n", __func__); 291 return; 292 } 293 294 sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz); 295 if (!sram_base) { 296 pr_warn("%s: unable to alloc ocram!\n", __func__); 297 return; 298 } 299 300 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); 301 slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false); 302 } 303 #endif 304 305 306 static void __init at91_pm_init(void) 307 { 308 #ifdef CONFIG_AT91_SLOW_CLOCK 309 at91_pm_sram_init(); 310 #endif 311 312 pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : "")); 313 314 if (at91_cpuidle_device.dev.platform_data) 315 platform_device_register(&at91_cpuidle_device); 316 317 suspend_set_ops(&at91_pm_ops); 318 } 319 320 void __init at91rm9200_pm_init(void) 321 { 322 at91_dt_ramc(); 323 324 /* 325 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. 326 */ 327 at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0); 328 329 at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP; 330 at91_pm_data.memctrl = AT91_MEMCTRL_MC; 331 332 at91_pm_init(); 333 } 334 335 void __init at91sam9260_pm_init(void) 336 { 337 at91_dt_ramc(); 338 at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC; 339 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; 340 return at91_pm_init(); 341 } 342 343 void __init at91sam9g45_pm_init(void) 344 { 345 at91_dt_ramc(); 346 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP; 347 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; 348 return at91_pm_init(); 349 } 350 351 void __init at91sam9x5_pm_init(void) 352 { 353 at91_dt_ramc(); 354 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; 355 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; 356 return at91_pm_init(); 357 } 358