1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * arch/arm/mach-at91/pm.c 4 * AT91 Power Management 5 * 6 * Copyright (C) 2005 David Brownell 7 */ 8 9 #include <linux/genalloc.h> 10 #include <linux/io.h> 11 #include <linux/of_address.h> 12 #include <linux/of.h> 13 #include <linux/of_fdt.h> 14 #include <linux/of_platform.h> 15 #include <linux/parser.h> 16 #include <linux/suspend.h> 17 18 #include <linux/clk/at91_pmc.h> 19 #include <linux/platform_data/atmel.h> 20 21 #include <soc/at91/pm.h> 22 23 #include <asm/cacheflush.h> 24 #include <asm/fncpy.h> 25 #include <asm/system_misc.h> 26 #include <asm/suspend.h> 27 28 #include "generic.h" 29 #include "pm.h" 30 31 #define BACKUP_DDR_PHY_CALIBRATION (9) 32 33 /** 34 * struct at91_pm_bu - AT91 power management backup unit data structure 35 * @suspended: true if suspended to backup mode 36 * @reserved: reserved 37 * @canary: canary data for memory checking after exit from backup mode 38 * @resume: resume API 39 * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words 40 * of the memory 41 */ 42 struct at91_pm_bu { 43 int suspended; 44 unsigned long reserved; 45 phys_addr_t canary; 46 phys_addr_t resume; 47 unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION]; 48 }; 49 50 /* 51 * struct at91_pm_sfrbu_offsets: registers mapping for SFRBU 52 * @pswbu: power switch BU control registers 53 */ 54 struct at91_pm_sfrbu_regs { 55 struct { 56 u32 key; 57 u32 ctrl; 58 u32 state; 59 u32 softsw; 60 } pswbu; 61 }; 62 63 /** 64 * struct at91_soc_pm - AT91 SoC power management data structure 65 * @config_shdwc_ws: wakeup sources configuration function for SHDWC 66 * @config_pmc_ws: wakeup srouces configuration function for PMC 67 * @ws_ids: wakup sources of_device_id array 68 * @data: PM data to be used on last phase of suspend 69 * @sfrbu_regs: SFRBU registers mapping 70 * @bu: backup unit mapped data (for backup mode) 71 * @memcs: memory chip select 72 */ 73 struct at91_soc_pm { 74 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); 75 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); 76 const struct of_device_id *ws_ids; 77 struct at91_pm_bu *bu; 78 struct at91_pm_data data; 79 struct at91_pm_sfrbu_regs sfrbu_regs; 80 void *memcs; 81 }; 82 83 /** 84 * enum at91_pm_iomaps: IOs that needs to be mapped for different PM modes 85 * @AT91_PM_IOMAP_SHDWC: SHDWC controller 86 * @AT91_PM_IOMAP_SFRBU: SFRBU controller 87 */ 88 enum at91_pm_iomaps { 89 AT91_PM_IOMAP_SHDWC, 90 AT91_PM_IOMAP_SFRBU, 91 }; 92 93 #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name) 94 95 static struct at91_soc_pm soc_pm = { 96 .data = { 97 .standby_mode = AT91_PM_STANDBY, 98 .suspend_mode = AT91_PM_ULP0, 99 }, 100 }; 101 102 static const match_table_t pm_modes __initconst = { 103 { AT91_PM_STANDBY, "standby" }, 104 { AT91_PM_ULP0, "ulp0" }, 105 { AT91_PM_ULP0_FAST, "ulp0-fast" }, 106 { AT91_PM_ULP1, "ulp1" }, 107 { AT91_PM_BACKUP, "backup" }, 108 { -1, NULL }, 109 }; 110 111 #define at91_ramc_read(id, field) \ 112 __raw_readl(soc_pm.data.ramc[id] + field) 113 114 #define at91_ramc_write(id, field, value) \ 115 __raw_writel(value, soc_pm.data.ramc[id] + field) 116 117 static int at91_pm_valid_state(suspend_state_t state) 118 { 119 switch (state) { 120 case PM_SUSPEND_ON: 121 case PM_SUSPEND_STANDBY: 122 case PM_SUSPEND_MEM: 123 return 1; 124 125 default: 126 return 0; 127 } 128 } 129 130 static int canary = 0xA5A5A5A5; 131 132 struct wakeup_source_info { 133 unsigned int pmc_fsmr_bit; 134 unsigned int shdwc_mr_bit; 135 bool set_polarity; 136 }; 137 138 static const struct wakeup_source_info ws_info[] = { 139 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true }, 140 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) }, 141 { .pmc_fsmr_bit = AT91_PMC_USBAL }, 142 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD }, 143 { .pmc_fsmr_bit = AT91_PMC_RTTAL }, 144 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE }, 145 }; 146 147 static const struct of_device_id sama5d2_ws_ids[] = { 148 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] }, 149 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] }, 150 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] }, 151 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, 152 { .compatible = "usb-ohci", .data = &ws_info[2] }, 153 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 154 { .compatible = "usb-ehci", .data = &ws_info[2] }, 155 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] }, 156 { /* sentinel */ } 157 }; 158 159 static const struct of_device_id sam9x60_ws_ids[] = { 160 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] }, 161 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, 162 { .compatible = "usb-ohci", .data = &ws_info[2] }, 163 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 164 { .compatible = "usb-ehci", .data = &ws_info[2] }, 165 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] }, 166 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] }, 167 { /* sentinel */ } 168 }; 169 170 static const struct of_device_id sama7g5_ws_ids[] = { 171 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] }, 172 { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] }, 173 { .compatible = "usb-ohci", .data = &ws_info[2] }, 174 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 175 { .compatible = "usb-ehci", .data = &ws_info[2] }, 176 { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] }, 177 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] }, 178 { /* sentinel */ } 179 }; 180 181 static int at91_pm_config_ws(unsigned int pm_mode, bool set) 182 { 183 const struct wakeup_source_info *wsi; 184 const struct of_device_id *match; 185 struct platform_device *pdev; 186 struct device_node *np; 187 unsigned int mode = 0, polarity = 0, val = 0; 188 189 if (pm_mode != AT91_PM_ULP1) 190 return 0; 191 192 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids) 193 return -EPERM; 194 195 if (!set) { 196 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR); 197 return 0; 198 } 199 200 if (soc_pm.config_shdwc_ws) 201 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity); 202 203 /* SHDWC.MR */ 204 val = readl(soc_pm.data.shdwc + 0x04); 205 206 /* Loop through defined wakeup sources. */ 207 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) { 208 pdev = of_find_device_by_node(np); 209 if (!pdev) 210 continue; 211 212 if (device_may_wakeup(&pdev->dev)) { 213 wsi = match->data; 214 215 /* Check if enabled on SHDWC. */ 216 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit)) 217 goto put_device; 218 219 mode |= wsi->pmc_fsmr_bit; 220 if (wsi->set_polarity) 221 polarity |= wsi->pmc_fsmr_bit; 222 } 223 224 put_device: 225 put_device(&pdev->dev); 226 } 227 228 if (mode) { 229 if (soc_pm.config_pmc_ws) 230 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity); 231 } else { 232 pr_err("AT91: PM: no ULP1 wakeup sources found!"); 233 } 234 235 return mode ? 0 : -EPERM; 236 } 237 238 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode, 239 u32 *polarity) 240 { 241 u32 val; 242 243 /* SHDWC.WUIR */ 244 val = readl(shdwc + 0x0c); 245 *mode |= (val & 0x3ff); 246 *polarity |= ((val >> 16) & 0x3ff); 247 248 return 0; 249 } 250 251 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity) 252 { 253 writel(mode, pmc + AT91_PMC_FSMR); 254 writel(polarity, pmc + AT91_PMC_FSPR); 255 256 return 0; 257 } 258 259 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity) 260 { 261 writel(mode, pmc + AT91_PMC_FSMR); 262 263 return 0; 264 } 265 266 /* 267 * Called after processes are frozen, but before we shutdown devices. 268 */ 269 static int at91_pm_begin(suspend_state_t state) 270 { 271 int ret; 272 273 switch (state) { 274 case PM_SUSPEND_MEM: 275 soc_pm.data.mode = soc_pm.data.suspend_mode; 276 break; 277 278 case PM_SUSPEND_STANDBY: 279 soc_pm.data.mode = soc_pm.data.standby_mode; 280 break; 281 282 default: 283 soc_pm.data.mode = -1; 284 } 285 286 ret = at91_pm_config_ws(soc_pm.data.mode, true); 287 if (ret) 288 return ret; 289 290 if (soc_pm.data.mode == AT91_PM_BACKUP) 291 soc_pm.bu->suspended = 1; 292 else if (soc_pm.bu) 293 soc_pm.bu->suspended = 0; 294 295 return 0; 296 } 297 298 /* 299 * Verify that all the clocks are correct before entering 300 * slow-clock mode. 301 */ 302 static int at91_pm_verify_clocks(void) 303 { 304 unsigned long scsr; 305 int i; 306 307 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR); 308 309 /* USB must not be using PLLB */ 310 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) { 311 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 312 return 0; 313 } 314 315 /* PCK0..PCK3 must be disabled, or configured to use clk32k */ 316 for (i = 0; i < 4; i++) { 317 u32 css; 318 319 if ((scsr & (AT91_PMC_PCK0 << i)) == 0) 320 continue; 321 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; 322 if (css != AT91_PMC_CSS_SLOW) { 323 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); 324 return 0; 325 } 326 } 327 328 return 1; 329 } 330 331 /* 332 * Call this from platform driver suspend() to see how deeply to suspend. 333 * For example, some controllers (like OHCI) need one of the PLL clocks 334 * in order to act as a wakeup source, and those are not available when 335 * going into slow clock mode. 336 * 337 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have 338 * the very same problem (but not using at91 main_clk), and it'd be better 339 * to add one generic API rather than lots of platform-specific ones. 340 */ 341 int at91_suspend_entering_slow_clock(void) 342 { 343 return (soc_pm.data.mode >= AT91_PM_ULP0); 344 } 345 EXPORT_SYMBOL(at91_suspend_entering_slow_clock); 346 347 static void (*at91_suspend_sram_fn)(struct at91_pm_data *); 348 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data); 349 extern u32 at91_pm_suspend_in_sram_sz; 350 351 static int at91_suspend_finish(unsigned long val) 352 { 353 int i; 354 355 if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) { 356 /* 357 * The 1st 8 words of memory might get corrupted in the process 358 * of DDR PHY recalibration; it is saved here in securam and it 359 * will be restored later, after recalibration, by bootloader 360 */ 361 for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++) 362 soc_pm.bu->ddr_phy_calibration[i] = 363 *((unsigned int *)soc_pm.memcs + (i - 1)); 364 } 365 366 flush_cache_all(); 367 outer_disable(); 368 369 at91_suspend_sram_fn(&soc_pm.data); 370 371 return 0; 372 } 373 374 static void at91_pm_switch_ba_to_vbat(void) 375 { 376 unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu); 377 unsigned int val; 378 379 /* Just for safety. */ 380 if (!soc_pm.data.sfrbu) 381 return; 382 383 val = readl(soc_pm.data.sfrbu + offset); 384 385 /* Already on VBAT. */ 386 if (!(val & soc_pm.sfrbu_regs.pswbu.state)) 387 return; 388 389 val &= ~soc_pm.sfrbu_regs.pswbu.softsw; 390 val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl; 391 writel(val, soc_pm.data.sfrbu + offset); 392 393 /* Wait for update. */ 394 val = readl(soc_pm.data.sfrbu + offset); 395 while (val & soc_pm.sfrbu_regs.pswbu.state) 396 val = readl(soc_pm.data.sfrbu + offset); 397 } 398 399 static void at91_pm_suspend(suspend_state_t state) 400 { 401 if (soc_pm.data.mode == AT91_PM_BACKUP) { 402 at91_pm_switch_ba_to_vbat(); 403 404 cpu_suspend(0, at91_suspend_finish); 405 406 /* The SRAM is lost between suspend cycles */ 407 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 408 &at91_pm_suspend_in_sram, 409 at91_pm_suspend_in_sram_sz); 410 } else { 411 at91_suspend_finish(0); 412 } 413 414 outer_resume(); 415 } 416 417 /* 418 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup' 419 * event sources; and reduces DRAM power. But otherwise it's identical to 420 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks. 421 * 422 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must 423 * suspend more deeply, the master clock switches to the clk32k and turns off 424 * the main oscillator 425 * 426 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh 427 */ 428 static int at91_pm_enter(suspend_state_t state) 429 { 430 #ifdef CONFIG_PINCTRL_AT91 431 /* 432 * FIXME: this is needed to communicate between the pinctrl driver and 433 * the PM implementation in the machine. Possibly part of the PM 434 * implementation should be moved down into the pinctrl driver and get 435 * called as part of the generic suspend/resume path. 436 */ 437 at91_pinctrl_gpio_suspend(); 438 #endif 439 440 switch (state) { 441 case PM_SUSPEND_MEM: 442 case PM_SUSPEND_STANDBY: 443 /* 444 * Ensure that clocks are in a valid state. 445 */ 446 if (soc_pm.data.mode >= AT91_PM_ULP0 && 447 !at91_pm_verify_clocks()) 448 goto error; 449 450 at91_pm_suspend(state); 451 452 break; 453 454 case PM_SUSPEND_ON: 455 cpu_do_idle(); 456 break; 457 458 default: 459 pr_debug("AT91: PM - bogus suspend state %d\n", state); 460 goto error; 461 } 462 463 error: 464 #ifdef CONFIG_PINCTRL_AT91 465 at91_pinctrl_gpio_resume(); 466 #endif 467 return 0; 468 } 469 470 /* 471 * Called right prior to thawing processes. 472 */ 473 static void at91_pm_end(void) 474 { 475 at91_pm_config_ws(soc_pm.data.mode, false); 476 } 477 478 479 static const struct platform_suspend_ops at91_pm_ops = { 480 .valid = at91_pm_valid_state, 481 .begin = at91_pm_begin, 482 .enter = at91_pm_enter, 483 .end = at91_pm_end, 484 }; 485 486 static struct platform_device at91_cpuidle_device = { 487 .name = "cpuidle-at91", 488 }; 489 490 /* 491 * The AT91RM9200 goes into self-refresh mode with this command, and will 492 * terminate self-refresh automatically on the next SDRAM access. 493 * 494 * Self-refresh mode is exited as soon as a memory access is made, but we don't 495 * know for sure when that happens. However, we need to restore the low-power 496 * mode if it was enabled before going idle. Restoring low-power mode while 497 * still in self-refresh is "not recommended", but seems to work. 498 */ 499 static void at91rm9200_standby(void) 500 { 501 asm volatile( 502 "b 1f\n\t" 503 ".align 5\n\t" 504 "1: mcr p15, 0, %0, c7, c10, 4\n\t" 505 " str %2, [%1, %3]\n\t" 506 " mcr p15, 0, %0, c7, c0, 4\n\t" 507 : 508 : "r" (0), "r" (soc_pm.data.ramc[0]), 509 "r" (1), "r" (AT91_MC_SDRAMC_SRR)); 510 } 511 512 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 513 * remember. 514 */ 515 static void at91_ddr_standby(void) 516 { 517 /* Those two values allow us to delay self-refresh activation 518 * to the maximum. */ 519 u32 lpr0, lpr1 = 0; 520 u32 mdr, saved_mdr0, saved_mdr1 = 0; 521 u32 saved_lpr0, saved_lpr1 = 0; 522 523 /* LPDDR1 --> force DDR2 mode during self-refresh */ 524 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR); 525 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 526 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD; 527 mdr |= AT91_DDRSDRC_MD_DDR2; 528 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr); 529 } 530 531 if (soc_pm.data.ramc[1]) { 532 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); 533 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; 534 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 535 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR); 536 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 537 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD; 538 mdr |= AT91_DDRSDRC_MD_DDR2; 539 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr); 540 } 541 } 542 543 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 544 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 545 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 546 547 /* self-refresh mode now */ 548 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 549 if (soc_pm.data.ramc[1]) 550 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); 551 552 cpu_do_idle(); 553 554 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0); 555 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 556 if (soc_pm.data.ramc[1]) { 557 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1); 558 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); 559 } 560 } 561 562 static void sama5d3_ddr_standby(void) 563 { 564 u32 lpr0; 565 u32 saved_lpr0; 566 567 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 568 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 569 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN; 570 571 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 572 573 cpu_do_idle(); 574 575 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 576 } 577 578 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 579 * remember. 580 */ 581 static void at91sam9_sdram_standby(void) 582 { 583 u32 lpr0, lpr1 = 0; 584 u32 saved_lpr0, saved_lpr1 = 0; 585 586 if (soc_pm.data.ramc[1]) { 587 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); 588 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; 589 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 590 } 591 592 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); 593 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; 594 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 595 596 /* self-refresh mode now */ 597 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); 598 if (soc_pm.data.ramc[1]) 599 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); 600 601 cpu_do_idle(); 602 603 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); 604 if (soc_pm.data.ramc[1]) 605 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); 606 } 607 608 struct ramc_info { 609 void (*idle)(void); 610 unsigned int memctrl; 611 }; 612 613 static const struct ramc_info ramc_infos[] __initconst = { 614 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC}, 615 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC}, 616 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 617 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 618 }; 619 620 static const struct of_device_id ramc_ids[] __initconst = { 621 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] }, 622 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, 623 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, 624 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, 625 { .compatible = "microchip,sama7g5-uddrc", }, 626 { /*sentinel*/ } 627 }; 628 629 static const struct of_device_id ramc_phy_ids[] __initconst = { 630 { .compatible = "microchip,sama7g5-ddr3phy", }, 631 { /* Sentinel. */ }, 632 }; 633 634 static __init int at91_dt_ramc(bool phy_mandatory) 635 { 636 struct device_node *np; 637 const struct of_device_id *of_id; 638 int idx = 0; 639 void *standby = NULL; 640 const struct ramc_info *ramc; 641 int ret; 642 643 for_each_matching_node_and_match(np, ramc_ids, &of_id) { 644 soc_pm.data.ramc[idx] = of_iomap(np, 0); 645 if (!soc_pm.data.ramc[idx]) { 646 pr_err("unable to map ramc[%d] cpu registers\n", idx); 647 ret = -ENOMEM; 648 of_node_put(np); 649 goto unmap_ramc; 650 } 651 652 ramc = of_id->data; 653 if (ramc) { 654 if (!standby) 655 standby = ramc->idle; 656 soc_pm.data.memctrl = ramc->memctrl; 657 } 658 659 idx++; 660 } 661 662 if (!idx) { 663 pr_err("unable to find compatible ram controller node in dtb\n"); 664 ret = -ENODEV; 665 goto unmap_ramc; 666 } 667 668 /* Lookup for DDR PHY node, if any. */ 669 for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) { 670 soc_pm.data.ramc_phy = of_iomap(np, 0); 671 if (!soc_pm.data.ramc_phy) { 672 pr_err("unable to map ramc phy cpu registers\n"); 673 ret = -ENOMEM; 674 of_node_put(np); 675 goto unmap_ramc; 676 } 677 } 678 679 if (phy_mandatory && !soc_pm.data.ramc_phy) { 680 pr_err("DDR PHY is mandatory!\n"); 681 ret = -ENODEV; 682 goto unmap_ramc; 683 } 684 685 if (!standby) { 686 pr_warn("ramc no standby function available\n"); 687 return 0; 688 } 689 690 at91_cpuidle_device.dev.platform_data = standby; 691 692 return 0; 693 694 unmap_ramc: 695 while (idx) 696 iounmap(soc_pm.data.ramc[--idx]); 697 698 return ret; 699 } 700 701 static void at91rm9200_idle(void) 702 { 703 /* 704 * Disable the processor clock. The processor will be automatically 705 * re-enabled by an interrupt or by a reset. 706 */ 707 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); 708 } 709 710 static void at91sam9_idle(void) 711 { 712 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); 713 cpu_do_idle(); 714 } 715 716 static void __init at91_pm_sram_init(void) 717 { 718 struct gen_pool *sram_pool; 719 phys_addr_t sram_pbase; 720 unsigned long sram_base; 721 struct device_node *node; 722 struct platform_device *pdev = NULL; 723 724 for_each_compatible_node(node, NULL, "mmio-sram") { 725 pdev = of_find_device_by_node(node); 726 if (pdev) { 727 of_node_put(node); 728 break; 729 } 730 } 731 732 if (!pdev) { 733 pr_warn("%s: failed to find sram device!\n", __func__); 734 return; 735 } 736 737 sram_pool = gen_pool_get(&pdev->dev, NULL); 738 if (!sram_pool) { 739 pr_warn("%s: sram pool unavailable!\n", __func__); 740 goto out_put_device; 741 } 742 743 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz); 744 if (!sram_base) { 745 pr_warn("%s: unable to alloc sram!\n", __func__); 746 goto out_put_device; 747 } 748 749 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); 750 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase, 751 at91_pm_suspend_in_sram_sz, false); 752 if (!at91_suspend_sram_fn) { 753 pr_warn("SRAM: Could not map\n"); 754 goto out_put_device; 755 } 756 757 /* Copy the pm suspend handler to SRAM */ 758 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 759 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); 760 return; 761 762 out_put_device: 763 put_device(&pdev->dev); 764 return; 765 } 766 767 static bool __init at91_is_pm_mode_active(int pm_mode) 768 { 769 return (soc_pm.data.standby_mode == pm_mode || 770 soc_pm.data.suspend_mode == pm_mode); 771 } 772 773 static int __init at91_pm_backup_scan_memcs(unsigned long node, 774 const char *uname, int depth, 775 void *data) 776 { 777 const char *type; 778 const __be32 *reg; 779 int *located = data; 780 int size; 781 782 /* Memory node already located. */ 783 if (*located) 784 return 0; 785 786 type = of_get_flat_dt_prop(node, "device_type", NULL); 787 788 /* We are scanning "memory" nodes only. */ 789 if (!type || strcmp(type, "memory")) 790 return 0; 791 792 reg = of_get_flat_dt_prop(node, "reg", &size); 793 if (reg) { 794 soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg)); 795 *located = 1; 796 } 797 798 return 0; 799 } 800 801 static int __init at91_pm_backup_init(void) 802 { 803 struct gen_pool *sram_pool; 804 struct device_node *np; 805 struct platform_device *pdev; 806 int ret = -ENODEV, located = 0; 807 808 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) && 809 !IS_ENABLED(CONFIG_SOC_SAMA7G5)) 810 return -EPERM; 811 812 if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) 813 return 0; 814 815 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); 816 if (!np) 817 return ret; 818 819 pdev = of_find_device_by_node(np); 820 of_node_put(np); 821 if (!pdev) { 822 pr_warn("%s: failed to find securam device!\n", __func__); 823 return ret; 824 } 825 826 sram_pool = gen_pool_get(&pdev->dev, NULL); 827 if (!sram_pool) { 828 pr_warn("%s: securam pool unavailable!\n", __func__); 829 goto securam_fail; 830 } 831 832 soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); 833 if (!soc_pm.bu) { 834 pr_warn("%s: unable to alloc securam!\n", __func__); 835 ret = -ENOMEM; 836 goto securam_fail; 837 } 838 839 soc_pm.bu->suspended = 0; 840 soc_pm.bu->canary = __pa_symbol(&canary); 841 soc_pm.bu->resume = __pa_symbol(cpu_resume); 842 if (soc_pm.data.ramc_phy) { 843 of_scan_flat_dt(at91_pm_backup_scan_memcs, &located); 844 if (!located) 845 goto securam_fail; 846 847 /* DDR3PHY_ZQ0SR0 */ 848 soc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy + 849 0x188); 850 } 851 852 return 0; 853 854 securam_fail: 855 put_device(&pdev->dev); 856 return ret; 857 } 858 859 static const struct of_device_id atmel_shdwc_ids[] = { 860 { .compatible = "atmel,sama5d2-shdwc" }, 861 { .compatible = "microchip,sam9x60-shdwc" }, 862 { .compatible = "microchip,sama7g5-shdwc" }, 863 { /* sentinel. */ } 864 }; 865 866 static void __init at91_pm_modes_init(const u32 *maps, int len) 867 { 868 struct device_node *np; 869 int ret, mode; 870 871 ret = at91_pm_backup_init(); 872 if (ret) { 873 if (soc_pm.data.standby_mode == AT91_PM_BACKUP) 874 soc_pm.data.standby_mode = AT91_PM_ULP0; 875 if (soc_pm.data.suspend_mode == AT91_PM_BACKUP) 876 soc_pm.data.suspend_mode = AT91_PM_ULP0; 877 } 878 879 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || 880 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) { 881 np = of_find_matching_node(NULL, atmel_shdwc_ids); 882 if (!np) { 883 pr_warn("%s: failed to find shdwc!\n", __func__); 884 885 /* Use ULP0 if it doesn't needs SHDWC.*/ 886 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC))) 887 mode = AT91_PM_ULP0; 888 else 889 mode = AT91_PM_STANDBY; 890 891 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC)) 892 soc_pm.data.standby_mode = mode; 893 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) 894 soc_pm.data.suspend_mode = mode; 895 } else { 896 soc_pm.data.shdwc = of_iomap(np, 0); 897 of_node_put(np); 898 } 899 } 900 901 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || 902 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) { 903 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); 904 if (!np) { 905 pr_warn("%s: failed to find sfrbu!\n", __func__); 906 907 /* 908 * Use ULP0 if it doesn't need SHDWC or if SHDWC 909 * was already located. 910 */ 911 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) || 912 soc_pm.data.shdwc) 913 mode = AT91_PM_ULP0; 914 else 915 mode = AT91_PM_STANDBY; 916 917 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU)) 918 soc_pm.data.standby_mode = mode; 919 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) 920 soc_pm.data.suspend_mode = mode; 921 } else { 922 soc_pm.data.sfrbu = of_iomap(np, 0); 923 of_node_put(np); 924 } 925 } 926 927 /* Unmap all unnecessary. */ 928 if (soc_pm.data.shdwc && 929 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || 930 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) { 931 iounmap(soc_pm.data.shdwc); 932 soc_pm.data.shdwc = NULL; 933 } 934 935 if (soc_pm.data.sfrbu && 936 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || 937 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) { 938 iounmap(soc_pm.data.sfrbu); 939 soc_pm.data.sfrbu = NULL; 940 } 941 942 return; 943 } 944 945 struct pmc_info { 946 unsigned long uhp_udp_mask; 947 unsigned long mckr; 948 unsigned long version; 949 }; 950 951 static const struct pmc_info pmc_infos[] __initconst = { 952 { 953 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP, 954 .mckr = 0x30, 955 .version = AT91_PMC_V1, 956 }, 957 958 { 959 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, 960 .mckr = 0x30, 961 .version = AT91_PMC_V1, 962 }, 963 { 964 .uhp_udp_mask = AT91SAM926x_PMC_UHP, 965 .mckr = 0x30, 966 .version = AT91_PMC_V1, 967 }, 968 { .uhp_udp_mask = 0, 969 .mckr = 0x30, 970 .version = AT91_PMC_V1, 971 }, 972 { 973 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, 974 .mckr = 0x28, 975 .version = AT91_PMC_V2, 976 }, 977 { 978 .mckr = 0x28, 979 .version = AT91_PMC_V2, 980 }, 981 982 }; 983 984 static const struct of_device_id atmel_pmc_ids[] __initconst = { 985 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] }, 986 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] }, 987 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] }, 988 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] }, 989 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] }, 990 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] }, 991 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] }, 992 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] }, 993 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] }, 994 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, 995 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, 996 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, 997 { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] }, 998 { /* sentinel */ }, 999 }; 1000 1001 static void __init at91_pm_modes_validate(const int *modes, int len) 1002 { 1003 u8 i, standby = 0, suspend = 0; 1004 int mode; 1005 1006 for (i = 0; i < len; i++) { 1007 if (standby && suspend) 1008 break; 1009 1010 if (modes[i] == soc_pm.data.standby_mode && !standby) { 1011 standby = 1; 1012 continue; 1013 } 1014 1015 if (modes[i] == soc_pm.data.suspend_mode && !suspend) { 1016 suspend = 1; 1017 continue; 1018 } 1019 } 1020 1021 if (!standby) { 1022 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY) 1023 mode = AT91_PM_ULP0; 1024 else 1025 mode = AT91_PM_STANDBY; 1026 1027 pr_warn("AT91: PM: %s mode not supported! Using %s.\n", 1028 pm_modes[soc_pm.data.standby_mode].pattern, 1029 pm_modes[mode].pattern); 1030 soc_pm.data.standby_mode = mode; 1031 } 1032 1033 if (!suspend) { 1034 if (soc_pm.data.standby_mode == AT91_PM_ULP0) 1035 mode = AT91_PM_STANDBY; 1036 else 1037 mode = AT91_PM_ULP0; 1038 1039 pr_warn("AT91: PM: %s mode not supported! Using %s.\n", 1040 pm_modes[soc_pm.data.suspend_mode].pattern, 1041 pm_modes[mode].pattern); 1042 soc_pm.data.suspend_mode = mode; 1043 } 1044 } 1045 1046 static void __init at91_pm_init(void (*pm_idle)(void)) 1047 { 1048 struct device_node *pmc_np; 1049 const struct of_device_id *of_id; 1050 const struct pmc_info *pmc; 1051 1052 if (at91_cpuidle_device.dev.platform_data) 1053 platform_device_register(&at91_cpuidle_device); 1054 1055 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id); 1056 soc_pm.data.pmc = of_iomap(pmc_np, 0); 1057 of_node_put(pmc_np); 1058 if (!soc_pm.data.pmc) { 1059 pr_err("AT91: PM not supported, PMC not found\n"); 1060 return; 1061 } 1062 1063 pmc = of_id->data; 1064 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask; 1065 soc_pm.data.pmc_mckr_offset = pmc->mckr; 1066 soc_pm.data.pmc_version = pmc->version; 1067 1068 if (pm_idle) 1069 arm_pm_idle = pm_idle; 1070 1071 at91_pm_sram_init(); 1072 1073 if (at91_suspend_sram_fn) { 1074 suspend_set_ops(&at91_pm_ops); 1075 pr_info("AT91: PM: standby: %s, suspend: %s\n", 1076 pm_modes[soc_pm.data.standby_mode].pattern, 1077 pm_modes[soc_pm.data.suspend_mode].pattern); 1078 } else { 1079 pr_info("AT91: PM not supported, due to no SRAM allocated\n"); 1080 } 1081 } 1082 1083 void __init at91rm9200_pm_init(void) 1084 { 1085 int ret; 1086 1087 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200)) 1088 return; 1089 1090 /* 1091 * Force STANDBY and ULP0 mode to avoid calling 1092 * at91_pm_modes_validate() which may increase booting time. 1093 * Platform supports anyway only STANDBY and ULP0 modes. 1094 */ 1095 soc_pm.data.standby_mode = AT91_PM_STANDBY; 1096 soc_pm.data.suspend_mode = AT91_PM_ULP0; 1097 1098 ret = at91_dt_ramc(false); 1099 if (ret) 1100 return; 1101 1102 /* 1103 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. 1104 */ 1105 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); 1106 1107 at91_pm_init(at91rm9200_idle); 1108 } 1109 1110 void __init sam9x60_pm_init(void) 1111 { 1112 static const int modes[] __initconst = { 1113 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, 1114 }; 1115 static const int iomaps[] __initconst = { 1116 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC), 1117 }; 1118 int ret; 1119 1120 if (!IS_ENABLED(CONFIG_SOC_SAM9X60)) 1121 return; 1122 1123 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1124 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1125 ret = at91_dt_ramc(false); 1126 if (ret) 1127 return; 1128 1129 at91_pm_init(NULL); 1130 1131 soc_pm.ws_ids = sam9x60_ws_ids; 1132 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; 1133 } 1134 1135 void __init at91sam9_pm_init(void) 1136 { 1137 int ret; 1138 1139 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9)) 1140 return; 1141 1142 /* 1143 * Force STANDBY and ULP0 mode to avoid calling 1144 * at91_pm_modes_validate() which may increase booting time. 1145 * Platform supports anyway only STANDBY and ULP0 modes. 1146 */ 1147 soc_pm.data.standby_mode = AT91_PM_STANDBY; 1148 soc_pm.data.suspend_mode = AT91_PM_ULP0; 1149 1150 ret = at91_dt_ramc(false); 1151 if (ret) 1152 return; 1153 1154 at91_pm_init(at91sam9_idle); 1155 } 1156 1157 void __init sama5_pm_init(void) 1158 { 1159 static const int modes[] __initconst = { 1160 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, 1161 }; 1162 int ret; 1163 1164 if (!IS_ENABLED(CONFIG_SOC_SAMA5)) 1165 return; 1166 1167 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1168 ret = at91_dt_ramc(false); 1169 if (ret) 1170 return; 1171 1172 at91_pm_init(NULL); 1173 } 1174 1175 void __init sama5d2_pm_init(void) 1176 { 1177 static const int modes[] __initconst = { 1178 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, 1179 AT91_PM_BACKUP, 1180 }; 1181 static const u32 iomaps[] __initconst = { 1182 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC), 1183 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) | 1184 AT91_PM_IOMAP(SFRBU), 1185 }; 1186 int ret; 1187 1188 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) 1189 return; 1190 1191 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1192 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1193 ret = at91_dt_ramc(false); 1194 if (ret) 1195 return; 1196 1197 at91_pm_init(NULL); 1198 1199 soc_pm.ws_ids = sama5d2_ws_ids; 1200 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws; 1201 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws; 1202 1203 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); 1204 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); 1205 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); 1206 soc_pm.sfrbu_regs.pswbu.state = BIT(3); 1207 } 1208 1209 void __init sama7_pm_init(void) 1210 { 1211 static const int modes[] __initconst = { 1212 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP, 1213 }; 1214 static const u32 iomaps[] __initconst = { 1215 [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU), 1216 [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) | 1217 AT91_PM_IOMAP(SHDWC), 1218 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) | 1219 AT91_PM_IOMAP(SHDWC), 1220 }; 1221 int ret; 1222 1223 if (!IS_ENABLED(CONFIG_SOC_SAMA7)) 1224 return; 1225 1226 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1227 1228 ret = at91_dt_ramc(true); 1229 if (ret) 1230 return; 1231 1232 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1233 at91_pm_init(NULL); 1234 1235 soc_pm.ws_ids = sama7g5_ws_ids; 1236 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; 1237 1238 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); 1239 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); 1240 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); 1241 soc_pm.sfrbu_regs.pswbu.state = BIT(2); 1242 } 1243 1244 static int __init at91_pm_modes_select(char *str) 1245 { 1246 char *s; 1247 substring_t args[MAX_OPT_ARGS]; 1248 int standby, suspend; 1249 1250 if (!str) 1251 return 0; 1252 1253 s = strsep(&str, ","); 1254 standby = match_token(s, pm_modes, args); 1255 if (standby < 0) 1256 return 0; 1257 1258 suspend = match_token(str, pm_modes, args); 1259 if (suspend < 0) 1260 return 0; 1261 1262 soc_pm.data.standby_mode = standby; 1263 soc_pm.data.suspend_mode = suspend; 1264 1265 return 0; 1266 } 1267 early_param("atmel.pm_modes", at91_pm_modes_select); 1268