1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * arch/arm/mach-at91/pm.c 4 * AT91 Power Management 5 * 6 * Copyright (C) 2005 David Brownell 7 */ 8 9 #include <linux/genalloc.h> 10 #include <linux/io.h> 11 #include <linux/of_address.h> 12 #include <linux/of.h> 13 #include <linux/of_platform.h> 14 #include <linux/parser.h> 15 #include <linux/suspend.h> 16 17 #include <linux/clk/at91_pmc.h> 18 #include <linux/platform_data/atmel.h> 19 20 #include <asm/cacheflush.h> 21 #include <asm/fncpy.h> 22 #include <asm/system_misc.h> 23 #include <asm/suspend.h> 24 25 #include "generic.h" 26 #include "pm.h" 27 28 /* 29 * FIXME: this is needed to communicate between the pinctrl driver and 30 * the PM implementation in the machine. Possibly part of the PM 31 * implementation should be moved down into the pinctrl driver and get 32 * called as part of the generic suspend/resume path. 33 */ 34 #ifdef CONFIG_PINCTRL_AT91 35 extern void at91_pinctrl_gpio_suspend(void); 36 extern void at91_pinctrl_gpio_resume(void); 37 #endif 38 39 struct at91_soc_pm { 40 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); 41 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); 42 const struct of_device_id *ws_ids; 43 struct at91_pm_data data; 44 }; 45 46 static struct at91_soc_pm soc_pm = { 47 .data = { 48 .standby_mode = AT91_PM_STANDBY, 49 .suspend_mode = AT91_PM_ULP0, 50 }, 51 }; 52 53 static const match_table_t pm_modes __initconst = { 54 { AT91_PM_STANDBY, "standby" }, 55 { AT91_PM_ULP0, "ulp0" }, 56 { AT91_PM_ULP0_FAST, "ulp0-fast" }, 57 { AT91_PM_ULP1, "ulp1" }, 58 { AT91_PM_BACKUP, "backup" }, 59 { -1, NULL }, 60 }; 61 62 #define at91_ramc_read(id, field) \ 63 __raw_readl(soc_pm.data.ramc[id] + field) 64 65 #define at91_ramc_write(id, field, value) \ 66 __raw_writel(value, soc_pm.data.ramc[id] + field) 67 68 static int at91_pm_valid_state(suspend_state_t state) 69 { 70 switch (state) { 71 case PM_SUSPEND_ON: 72 case PM_SUSPEND_STANDBY: 73 case PM_SUSPEND_MEM: 74 return 1; 75 76 default: 77 return 0; 78 } 79 } 80 81 static int canary = 0xA5A5A5A5; 82 83 static struct at91_pm_bu { 84 int suspended; 85 unsigned long reserved; 86 phys_addr_t canary; 87 phys_addr_t resume; 88 } *pm_bu; 89 90 struct wakeup_source_info { 91 unsigned int pmc_fsmr_bit; 92 unsigned int shdwc_mr_bit; 93 bool set_polarity; 94 }; 95 96 static const struct wakeup_source_info ws_info[] = { 97 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true }, 98 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) }, 99 { .pmc_fsmr_bit = AT91_PMC_USBAL }, 100 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD }, 101 { .pmc_fsmr_bit = AT91_PMC_RTTAL }, 102 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE }, 103 }; 104 105 static const struct of_device_id sama5d2_ws_ids[] = { 106 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] }, 107 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] }, 108 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] }, 109 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, 110 { .compatible = "usb-ohci", .data = &ws_info[2] }, 111 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 112 { .compatible = "usb-ehci", .data = &ws_info[2] }, 113 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] }, 114 { /* sentinel */ } 115 }; 116 117 static const struct of_device_id sam9x60_ws_ids[] = { 118 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] }, 119 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, 120 { .compatible = "usb-ohci", .data = &ws_info[2] }, 121 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 122 { .compatible = "usb-ehci", .data = &ws_info[2] }, 123 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] }, 124 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] }, 125 { /* sentinel */ } 126 }; 127 128 static int at91_pm_config_ws(unsigned int pm_mode, bool set) 129 { 130 const struct wakeup_source_info *wsi; 131 const struct of_device_id *match; 132 struct platform_device *pdev; 133 struct device_node *np; 134 unsigned int mode = 0, polarity = 0, val = 0; 135 136 if (pm_mode != AT91_PM_ULP1) 137 return 0; 138 139 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids) 140 return -EPERM; 141 142 if (!set) { 143 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR); 144 return 0; 145 } 146 147 if (soc_pm.config_shdwc_ws) 148 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity); 149 150 /* SHDWC.MR */ 151 val = readl(soc_pm.data.shdwc + 0x04); 152 153 /* Loop through defined wakeup sources. */ 154 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) { 155 pdev = of_find_device_by_node(np); 156 if (!pdev) 157 continue; 158 159 if (device_may_wakeup(&pdev->dev)) { 160 wsi = match->data; 161 162 /* Check if enabled on SHDWC. */ 163 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit)) 164 goto put_device; 165 166 mode |= wsi->pmc_fsmr_bit; 167 if (wsi->set_polarity) 168 polarity |= wsi->pmc_fsmr_bit; 169 } 170 171 put_device: 172 put_device(&pdev->dev); 173 } 174 175 if (mode) { 176 if (soc_pm.config_pmc_ws) 177 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity); 178 } else { 179 pr_err("AT91: PM: no ULP1 wakeup sources found!"); 180 } 181 182 return mode ? 0 : -EPERM; 183 } 184 185 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode, 186 u32 *polarity) 187 { 188 u32 val; 189 190 /* SHDWC.WUIR */ 191 val = readl(shdwc + 0x0c); 192 *mode |= (val & 0x3ff); 193 *polarity |= ((val >> 16) & 0x3ff); 194 195 return 0; 196 } 197 198 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity) 199 { 200 writel(mode, pmc + AT91_PMC_FSMR); 201 writel(polarity, pmc + AT91_PMC_FSPR); 202 203 return 0; 204 } 205 206 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity) 207 { 208 writel(mode, pmc + AT91_PMC_FSMR); 209 210 return 0; 211 } 212 213 /* 214 * Called after processes are frozen, but before we shutdown devices. 215 */ 216 static int at91_pm_begin(suspend_state_t state) 217 { 218 switch (state) { 219 case PM_SUSPEND_MEM: 220 soc_pm.data.mode = soc_pm.data.suspend_mode; 221 break; 222 223 case PM_SUSPEND_STANDBY: 224 soc_pm.data.mode = soc_pm.data.standby_mode; 225 break; 226 227 default: 228 soc_pm.data.mode = -1; 229 } 230 231 return at91_pm_config_ws(soc_pm.data.mode, true); 232 } 233 234 /* 235 * Verify that all the clocks are correct before entering 236 * slow-clock mode. 237 */ 238 static int at91_pm_verify_clocks(void) 239 { 240 unsigned long scsr; 241 int i; 242 243 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR); 244 245 /* USB must not be using PLLB */ 246 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) { 247 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 248 return 0; 249 } 250 251 /* PCK0..PCK3 must be disabled, or configured to use clk32k */ 252 for (i = 0; i < 4; i++) { 253 u32 css; 254 255 if ((scsr & (AT91_PMC_PCK0 << i)) == 0) 256 continue; 257 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; 258 if (css != AT91_PMC_CSS_SLOW) { 259 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); 260 return 0; 261 } 262 } 263 264 return 1; 265 } 266 267 /* 268 * Call this from platform driver suspend() to see how deeply to suspend. 269 * For example, some controllers (like OHCI) need one of the PLL clocks 270 * in order to act as a wakeup source, and those are not available when 271 * going into slow clock mode. 272 * 273 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have 274 * the very same problem (but not using at91 main_clk), and it'd be better 275 * to add one generic API rather than lots of platform-specific ones. 276 */ 277 int at91_suspend_entering_slow_clock(void) 278 { 279 return (soc_pm.data.mode >= AT91_PM_ULP0); 280 } 281 EXPORT_SYMBOL(at91_suspend_entering_slow_clock); 282 283 static void (*at91_suspend_sram_fn)(struct at91_pm_data *); 284 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data); 285 extern u32 at91_pm_suspend_in_sram_sz; 286 287 static int at91_suspend_finish(unsigned long val) 288 { 289 flush_cache_all(); 290 outer_disable(); 291 292 at91_suspend_sram_fn(&soc_pm.data); 293 294 return 0; 295 } 296 297 static void at91_pm_suspend(suspend_state_t state) 298 { 299 if (soc_pm.data.mode == AT91_PM_BACKUP) { 300 pm_bu->suspended = 1; 301 302 cpu_suspend(0, at91_suspend_finish); 303 304 /* The SRAM is lost between suspend cycles */ 305 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 306 &at91_pm_suspend_in_sram, 307 at91_pm_suspend_in_sram_sz); 308 } else { 309 at91_suspend_finish(0); 310 } 311 312 outer_resume(); 313 } 314 315 /* 316 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup' 317 * event sources; and reduces DRAM power. But otherwise it's identical to 318 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks. 319 * 320 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must 321 * suspend more deeply, the master clock switches to the clk32k and turns off 322 * the main oscillator 323 * 324 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh 325 */ 326 static int at91_pm_enter(suspend_state_t state) 327 { 328 #ifdef CONFIG_PINCTRL_AT91 329 at91_pinctrl_gpio_suspend(); 330 #endif 331 332 switch (state) { 333 case PM_SUSPEND_MEM: 334 case PM_SUSPEND_STANDBY: 335 /* 336 * Ensure that clocks are in a valid state. 337 */ 338 if (soc_pm.data.mode >= AT91_PM_ULP0 && 339 !at91_pm_verify_clocks()) 340 goto error; 341 342 at91_pm_suspend(state); 343 344 break; 345 346 case PM_SUSPEND_ON: 347 cpu_do_idle(); 348 break; 349 350 default: 351 pr_debug("AT91: PM - bogus suspend state %d\n", state); 352 goto error; 353 } 354 355 error: 356 #ifdef CONFIG_PINCTRL_AT91 357 at91_pinctrl_gpio_resume(); 358 #endif 359 return 0; 360 } 361 362 /* 363 * Called right prior to thawing processes. 364 */ 365 static void at91_pm_end(void) 366 { 367 at91_pm_config_ws(soc_pm.data.mode, false); 368 } 369 370 371 static const struct platform_suspend_ops at91_pm_ops = { 372 .valid = at91_pm_valid_state, 373 .begin = at91_pm_begin, 374 .enter = at91_pm_enter, 375 .end = at91_pm_end, 376 }; 377 378 static struct platform_device at91_cpuidle_device = { 379 .name = "cpuidle-at91", 380 }; 381 382 /* 383 * The AT91RM9200 goes into self-refresh mode with this command, and will 384 * terminate self-refresh automatically on the next SDRAM access. 385 * 386 * Self-refresh mode is exited as soon as a memory access is made, but we don't 387 * know for sure when that happens. However, we need to restore the low-power 388 * mode if it was enabled before going idle. Restoring low-power mode while 389 * still in self-refresh is "not recommended", but seems to work. 390 */ 391 static void at91rm9200_standby(void) 392 { 393 asm volatile( 394 "b 1f\n\t" 395 ".align 5\n\t" 396 "1: mcr p15, 0, %0, c7, c10, 4\n\t" 397 " str %2, [%1, %3]\n\t" 398 " mcr p15, 0, %0, c7, c0, 4\n\t" 399 : 400 : "r" (0), "r" (soc_pm.data.ramc[0]), 401 "r" (1), "r" (AT91_MC_SDRAMC_SRR)); 402 } 403 404 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 405 * remember. 406 */ 407 static void at91_ddr_standby(void) 408 { 409 /* Those two values allow us to delay self-refresh activation 410 * to the maximum. */ 411 u32 lpr0, lpr1 = 0; 412 u32 mdr, saved_mdr0, saved_mdr1 = 0; 413 u32 saved_lpr0, saved_lpr1 = 0; 414 415 /* LPDDR1 --> force DDR2 mode during self-refresh */ 416 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR); 417 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 418 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD; 419 mdr |= AT91_DDRSDRC_MD_DDR2; 420 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr); 421 } 422 423 if (soc_pm.data.ramc[1]) { 424 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); 425 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; 426 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 427 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR); 428 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 429 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD; 430 mdr |= AT91_DDRSDRC_MD_DDR2; 431 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr); 432 } 433 } 434 435 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 436 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 437 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 438 439 /* self-refresh mode now */ 440 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 441 if (soc_pm.data.ramc[1]) 442 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); 443 444 cpu_do_idle(); 445 446 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0); 447 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 448 if (soc_pm.data.ramc[1]) { 449 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1); 450 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); 451 } 452 } 453 454 static void sama5d3_ddr_standby(void) 455 { 456 u32 lpr0; 457 u32 saved_lpr0; 458 459 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 460 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 461 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN; 462 463 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 464 465 cpu_do_idle(); 466 467 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 468 } 469 470 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 471 * remember. 472 */ 473 static void at91sam9_sdram_standby(void) 474 { 475 u32 lpr0, lpr1 = 0; 476 u32 saved_lpr0, saved_lpr1 = 0; 477 478 if (soc_pm.data.ramc[1]) { 479 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); 480 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; 481 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 482 } 483 484 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); 485 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; 486 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 487 488 /* self-refresh mode now */ 489 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); 490 if (soc_pm.data.ramc[1]) 491 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); 492 493 cpu_do_idle(); 494 495 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); 496 if (soc_pm.data.ramc[1]) 497 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); 498 } 499 500 struct ramc_info { 501 void (*idle)(void); 502 unsigned int memctrl; 503 }; 504 505 static const struct ramc_info ramc_infos[] __initconst = { 506 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC}, 507 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC}, 508 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 509 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 510 }; 511 512 static const struct of_device_id ramc_ids[] __initconst = { 513 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] }, 514 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, 515 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, 516 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, 517 { /*sentinel*/ } 518 }; 519 520 static __init void at91_dt_ramc(void) 521 { 522 struct device_node *np; 523 const struct of_device_id *of_id; 524 int idx = 0; 525 void *standby = NULL; 526 const struct ramc_info *ramc; 527 528 for_each_matching_node_and_match(np, ramc_ids, &of_id) { 529 soc_pm.data.ramc[idx] = of_iomap(np, 0); 530 if (!soc_pm.data.ramc[idx]) 531 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx); 532 533 ramc = of_id->data; 534 if (!standby) 535 standby = ramc->idle; 536 soc_pm.data.memctrl = ramc->memctrl; 537 538 idx++; 539 } 540 541 if (!idx) 542 panic(pr_fmt("unable to find compatible ram controller node in dtb\n")); 543 544 if (!standby) { 545 pr_warn("ramc no standby function available\n"); 546 return; 547 } 548 549 at91_cpuidle_device.dev.platform_data = standby; 550 } 551 552 static void at91rm9200_idle(void) 553 { 554 /* 555 * Disable the processor clock. The processor will be automatically 556 * re-enabled by an interrupt or by a reset. 557 */ 558 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); 559 } 560 561 static void at91sam9_idle(void) 562 { 563 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); 564 cpu_do_idle(); 565 } 566 567 static void __init at91_pm_sram_init(void) 568 { 569 struct gen_pool *sram_pool; 570 phys_addr_t sram_pbase; 571 unsigned long sram_base; 572 struct device_node *node; 573 struct platform_device *pdev = NULL; 574 575 for_each_compatible_node(node, NULL, "mmio-sram") { 576 pdev = of_find_device_by_node(node); 577 if (pdev) { 578 of_node_put(node); 579 break; 580 } 581 } 582 583 if (!pdev) { 584 pr_warn("%s: failed to find sram device!\n", __func__); 585 return; 586 } 587 588 sram_pool = gen_pool_get(&pdev->dev, NULL); 589 if (!sram_pool) { 590 pr_warn("%s: sram pool unavailable!\n", __func__); 591 goto out_put_device; 592 } 593 594 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz); 595 if (!sram_base) { 596 pr_warn("%s: unable to alloc sram!\n", __func__); 597 goto out_put_device; 598 } 599 600 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); 601 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase, 602 at91_pm_suspend_in_sram_sz, false); 603 if (!at91_suspend_sram_fn) { 604 pr_warn("SRAM: Could not map\n"); 605 goto out_put_device; 606 } 607 608 /* Copy the pm suspend handler to SRAM */ 609 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 610 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); 611 return; 612 613 out_put_device: 614 put_device(&pdev->dev); 615 return; 616 } 617 618 static bool __init at91_is_pm_mode_active(int pm_mode) 619 { 620 return (soc_pm.data.standby_mode == pm_mode || 621 soc_pm.data.suspend_mode == pm_mode); 622 } 623 624 static int __init at91_pm_backup_init(void) 625 { 626 struct gen_pool *sram_pool; 627 struct device_node *np; 628 struct platform_device *pdev = NULL; 629 int ret = -ENODEV; 630 631 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) 632 return -EPERM; 633 634 if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) 635 return 0; 636 637 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); 638 if (!np) { 639 pr_warn("%s: failed to find sfrbu!\n", __func__); 640 return ret; 641 } 642 643 soc_pm.data.sfrbu = of_iomap(np, 0); 644 of_node_put(np); 645 646 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); 647 if (!np) 648 goto securam_fail_no_ref_dev; 649 650 pdev = of_find_device_by_node(np); 651 of_node_put(np); 652 if (!pdev) { 653 pr_warn("%s: failed to find securam device!\n", __func__); 654 goto securam_fail_no_ref_dev; 655 } 656 657 sram_pool = gen_pool_get(&pdev->dev, NULL); 658 if (!sram_pool) { 659 pr_warn("%s: securam pool unavailable!\n", __func__); 660 goto securam_fail; 661 } 662 663 pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); 664 if (!pm_bu) { 665 pr_warn("%s: unable to alloc securam!\n", __func__); 666 ret = -ENOMEM; 667 goto securam_fail; 668 } 669 670 pm_bu->suspended = 0; 671 pm_bu->canary = __pa_symbol(&canary); 672 pm_bu->resume = __pa_symbol(cpu_resume); 673 674 return 0; 675 676 securam_fail: 677 put_device(&pdev->dev); 678 securam_fail_no_ref_dev: 679 iounmap(soc_pm.data.sfrbu); 680 soc_pm.data.sfrbu = NULL; 681 return ret; 682 } 683 684 static void __init at91_pm_use_default_mode(int pm_mode) 685 { 686 if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP) 687 return; 688 689 if (soc_pm.data.standby_mode == pm_mode) 690 soc_pm.data.standby_mode = AT91_PM_ULP0; 691 if (soc_pm.data.suspend_mode == pm_mode) 692 soc_pm.data.suspend_mode = AT91_PM_ULP0; 693 } 694 695 static const struct of_device_id atmel_shdwc_ids[] = { 696 { .compatible = "atmel,sama5d2-shdwc" }, 697 { .compatible = "microchip,sam9x60-shdwc" }, 698 { /* sentinel. */ } 699 }; 700 701 static void __init at91_pm_modes_init(void) 702 { 703 struct device_node *np; 704 int ret; 705 706 if (!at91_is_pm_mode_active(AT91_PM_BACKUP) && 707 !at91_is_pm_mode_active(AT91_PM_ULP1)) 708 return; 709 710 np = of_find_matching_node(NULL, atmel_shdwc_ids); 711 if (!np) { 712 pr_warn("%s: failed to find shdwc!\n", __func__); 713 goto ulp1_default; 714 } 715 716 soc_pm.data.shdwc = of_iomap(np, 0); 717 of_node_put(np); 718 719 ret = at91_pm_backup_init(); 720 if (ret) { 721 if (!at91_is_pm_mode_active(AT91_PM_ULP1)) 722 goto unmap; 723 else 724 goto backup_default; 725 } 726 727 return; 728 729 unmap: 730 iounmap(soc_pm.data.shdwc); 731 soc_pm.data.shdwc = NULL; 732 ulp1_default: 733 at91_pm_use_default_mode(AT91_PM_ULP1); 734 backup_default: 735 at91_pm_use_default_mode(AT91_PM_BACKUP); 736 } 737 738 struct pmc_info { 739 unsigned long uhp_udp_mask; 740 unsigned long mckr; 741 unsigned long version; 742 }; 743 744 static const struct pmc_info pmc_infos[] __initconst = { 745 { 746 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP, 747 .mckr = 0x30, 748 .version = AT91_PMC_V1, 749 }, 750 751 { 752 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, 753 .mckr = 0x30, 754 .version = AT91_PMC_V1, 755 }, 756 { 757 .uhp_udp_mask = AT91SAM926x_PMC_UHP, 758 .mckr = 0x30, 759 .version = AT91_PMC_V1, 760 }, 761 { .uhp_udp_mask = 0, 762 .mckr = 0x30, 763 .version = AT91_PMC_V1, 764 }, 765 { 766 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, 767 .mckr = 0x28, 768 .version = AT91_PMC_V2, 769 }, 770 }; 771 772 static const struct of_device_id atmel_pmc_ids[] __initconst = { 773 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] }, 774 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] }, 775 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] }, 776 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] }, 777 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] }, 778 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] }, 779 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] }, 780 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] }, 781 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] }, 782 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, 783 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, 784 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, 785 { /* sentinel */ }, 786 }; 787 788 static void __init at91_pm_modes_validate(const int *modes, int len) 789 { 790 u8 i, standby = 0, suspend = 0; 791 int mode; 792 793 for (i = 0; i < len; i++) { 794 if (standby && suspend) 795 break; 796 797 if (modes[i] == soc_pm.data.standby_mode && !standby) { 798 standby = 1; 799 continue; 800 } 801 802 if (modes[i] == soc_pm.data.suspend_mode && !suspend) { 803 suspend = 1; 804 continue; 805 } 806 } 807 808 if (!standby) { 809 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY) 810 mode = AT91_PM_ULP0; 811 else 812 mode = AT91_PM_STANDBY; 813 814 pr_warn("AT91: PM: %s mode not supported! Using %s.\n", 815 pm_modes[soc_pm.data.standby_mode].pattern, 816 pm_modes[mode].pattern); 817 soc_pm.data.standby_mode = mode; 818 } 819 820 if (!suspend) { 821 if (soc_pm.data.standby_mode == AT91_PM_ULP0) 822 mode = AT91_PM_STANDBY; 823 else 824 mode = AT91_PM_ULP0; 825 826 pr_warn("AT91: PM: %s mode not supported! Using %s.\n", 827 pm_modes[soc_pm.data.suspend_mode].pattern, 828 pm_modes[mode].pattern); 829 soc_pm.data.suspend_mode = mode; 830 } 831 } 832 833 static void __init at91_pm_init(void (*pm_idle)(void)) 834 { 835 struct device_node *pmc_np; 836 const struct of_device_id *of_id; 837 const struct pmc_info *pmc; 838 839 if (at91_cpuidle_device.dev.platform_data) 840 platform_device_register(&at91_cpuidle_device); 841 842 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id); 843 soc_pm.data.pmc = of_iomap(pmc_np, 0); 844 of_node_put(pmc_np); 845 if (!soc_pm.data.pmc) { 846 pr_err("AT91: PM not supported, PMC not found\n"); 847 return; 848 } 849 850 pmc = of_id->data; 851 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask; 852 soc_pm.data.pmc_mckr_offset = pmc->mckr; 853 soc_pm.data.pmc_version = pmc->version; 854 855 if (pm_idle) 856 arm_pm_idle = pm_idle; 857 858 at91_pm_sram_init(); 859 860 if (at91_suspend_sram_fn) { 861 suspend_set_ops(&at91_pm_ops); 862 pr_info("AT91: PM: standby: %s, suspend: %s\n", 863 pm_modes[soc_pm.data.standby_mode].pattern, 864 pm_modes[soc_pm.data.suspend_mode].pattern); 865 } else { 866 pr_info("AT91: PM not supported, due to no SRAM allocated\n"); 867 } 868 } 869 870 void __init at91rm9200_pm_init(void) 871 { 872 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200)) 873 return; 874 875 /* 876 * Force STANDBY and ULP0 mode to avoid calling 877 * at91_pm_modes_validate() which may increase booting time. 878 * Platform supports anyway only STANDBY and ULP0 modes. 879 */ 880 soc_pm.data.standby_mode = AT91_PM_STANDBY; 881 soc_pm.data.suspend_mode = AT91_PM_ULP0; 882 883 at91_dt_ramc(); 884 885 /* 886 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. 887 */ 888 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); 889 890 at91_pm_init(at91rm9200_idle); 891 } 892 893 void __init sam9x60_pm_init(void) 894 { 895 static const int modes[] __initconst = { 896 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, 897 }; 898 899 if (!IS_ENABLED(CONFIG_SOC_SAM9X60)) 900 return; 901 902 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 903 at91_pm_modes_init(); 904 at91_dt_ramc(); 905 at91_pm_init(NULL); 906 907 soc_pm.ws_ids = sam9x60_ws_ids; 908 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; 909 } 910 911 void __init at91sam9_pm_init(void) 912 { 913 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9)) 914 return; 915 916 /* 917 * Force STANDBY and ULP0 mode to avoid calling 918 * at91_pm_modes_validate() which may increase booting time. 919 * Platform supports anyway only STANDBY and ULP0 modes. 920 */ 921 soc_pm.data.standby_mode = AT91_PM_STANDBY; 922 soc_pm.data.suspend_mode = AT91_PM_ULP0; 923 924 at91_dt_ramc(); 925 at91_pm_init(at91sam9_idle); 926 } 927 928 void __init sama5_pm_init(void) 929 { 930 static const int modes[] __initconst = { 931 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, 932 }; 933 934 if (!IS_ENABLED(CONFIG_SOC_SAMA5)) 935 return; 936 937 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 938 at91_dt_ramc(); 939 at91_pm_init(NULL); 940 } 941 942 void __init sama5d2_pm_init(void) 943 { 944 static const int modes[] __initconst = { 945 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, 946 AT91_PM_BACKUP, 947 }; 948 949 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) 950 return; 951 952 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 953 at91_pm_modes_init(); 954 at91_dt_ramc(); 955 at91_pm_init(NULL); 956 957 soc_pm.ws_ids = sama5d2_ws_ids; 958 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws; 959 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws; 960 } 961 962 static int __init at91_pm_modes_select(char *str) 963 { 964 char *s; 965 substring_t args[MAX_OPT_ARGS]; 966 int standby, suspend; 967 968 if (!str) 969 return 0; 970 971 s = strsep(&str, ","); 972 standby = match_token(s, pm_modes, args); 973 if (standby < 0) 974 return 0; 975 976 suspend = match_token(str, pm_modes, args); 977 if (suspend < 0) 978 return 0; 979 980 soc_pm.data.standby_mode = standby; 981 soc_pm.data.suspend_mode = suspend; 982 983 return 0; 984 } 985 early_param("atmel.pm_modes", at91_pm_modes_select); 986